Open Lead Detection Based on Supply Current of CMOS Logic Circuits by AC Voltage Signal Application


Test Time Reduction Method for Scan Design with Clock-Control DFT

Proc. RISP International Workshop on Nonlinear Circuit and Signal Processing

This paper presents a test generation method for sequential circuits. Our method utilizes the test vectors obtained for full scan design. In this parer, we combined two design-for- testability(DFT) method:one is transparent scan, the other is clock-control DFT. The simulation results for some benchmark circuits are shown.


Current Testable Design of Resistor String DACs

The IEEE International Workshop on Electronic Design, Test and Applications

In this paper, supply current testability is examined experimentally for opens and shorts in a general 3 bit resistor string digital/analog converter (DAC). The results show that all of the shorts and the opens are detected by supply current testing, while opens of the MOS switches are not detected. A DFT method for resistor string DACs is proposed in this paper to detect the opens by supply current testing. Also, testability of a resistor string DAC designed with the DFT method is examined. It is shown that all of the targeted shorts and opens in the testable designed DAC are detected by supply current testing.


Test Generation for Scan Circuits Using Random Selection of the Operations of Scan Flip-flops

6th Workshop on RTL and High Level Testing (WRTLT05)

This paper presents a test generation method for scan circuits. In the proposed method control signals of scan flip-flops are treated as the same as the primary inputs. Our method utilizes the test vectors obtained for full scan design and apply the vectors repeatedly in the given order to achieve low test data volume. For each test vector, the operation of scan flip-flops is selected from one of the following: normal, scan and freeze operation. The simulation results for some benchmark circuits are shown.


Electric Field for Detecting Open Leads in CMOS Logic Circuits by Supply Current Testing

Proc. of IEEE International Symposium on Circuits and Systems

Open leads are one type of defect occurring frequently when logic circuits are implemented on printed circuit boards (PCBs) with ICs. A powerful supply current test method has been proposed for detecting an open lead in a CMOS logic circuit. The method is based on the supply current of a circuit under test which flows when a time-varying electric field is supplied from the outside of the circuit. The paper proposes a time-varying electric field which enables us to detect open leads in a CMOS logic circuit with an inexpensive test setup.


Vectorless Open Pin Detection Method for CMOS Logic Circuits

Proc. of International Conference on Electronics Packaging


Fail-Safe Evaluation Method for Boiler Control Circuits by Circuit Simulation

The fail-safe property is strongly requested for boiler control circuits. A boiler control circuit is a microprocessor based circuit and the operation is specified by a control program. Until now, there have been no methods to evaluate fail-safe property of boiler control circuits. In this paper, a fail safe evaluation method is proposed for boiler control circuits. The method utilizes a circuit simulator to check it. It is checked by the method whether it is stopped supplying fuel to a boiler when a fault occurs inside the boiler control circuit in operation. In order to evaluate the feasibility of fail-safe evaluation by the method, fail-safe property in a general boiler control circuit is examined by using the method. The result shows that fail-safe property will be checked by using the evaluation method.


Electrical Detection of Pin Shorts by Supply Current of PIC

In this paper, we propose a new test method for detecting pin shorts of a PIC. This test method is based on supply current of the PIC. Targeted faults of this test method are input/output pins of the PIC. The property is used for detecting the shorts in the test method that input/output mode of each of the pins is programmable. Each of the fault is excited by executing a test program so that supply current change can appear. We checked the feasibility of the test method by some experiments. The results shows that the shorts will be detected by the test method.


Test Equipment for CMOS Lead Open Detection Based on Supply Current under AC Electric Field Application

Open leads have often occurred in logic circuits implemented on printed circuit boards with the state-of-art technology. We proposed an electrical test method to detect them with high fault coverage. The test method is based on supply current change of a circuit under test that is caused with AC electric field supplied from the outside of the circuit. In this paper, we propose a test equipment for the test method. A voltage signal that is obtained by mixing a rectangle waveform signal and a sine waveform one is supplied between electrodes to generate the electric field. Amplitude of the signal continues to increase in proportion to time during a specified time. When supply current change that is larger than a threshold value appears, it stops increasing the amplitude and it is concluded that open leads occur in the circuit. If the supply current change does not appear within the specified time, it is concluded that no open leads occur in the circuit. In this paper, it is shown experimentally that an open lead at a CPLD of PLCC package is detected with the test equipment.


IDDQ Test Method Based on Wavelet Transformation for Noisy Current Measurement Environment

An IDDQ test method is proposed in this paper, which is applicable even if supply current measurement is impaired by noise. Wavelet transformation is used for noise elimination in the test method. In this paper, it is shown by some experiments that bridging faults will be detected by using the proposed test method. Since expert knowledge on filter design is not needed in noise elimination of the IDDQ test method, it is expected that the test method will be used in many IDDQ tests.


Test Circuit for CMOS Lead Open Detection by Supply Current Testing under AC Electric Field Application

Proc. of the 2004 47-th Midwest Symposium on Circuits and Systems

A test circuit is proposed for detecting lead opens of CMOS ICs by measuring the supply current of a CMOS circuit made of the ICs which flows when AC electric field is applied from the outside. A signal of a sine waveform is provided to the test circuit. In the test circuit, the amplitude of the signal increases in proportion to time during a prespecified time. The amplified signal is provided to electrodes for AC electric field to be supplied to a circuit under test. When supply current change which is larger than a threshold value appears, it stops increasing the amplitude and the test circuit concludes that a lead open occurs in the circuit. If the elevated supply current change does not appear within the specified time, the test circuit concludes that the circuit is fault-free. It is shown by our experiments that lead opens in a CMOS IC is detected with the test circuit.


AC Electric Field for Detecting Pin Opens by Supply Current of CMOS ICs

International Microelectronics and Packaging Society Japan


A Power Supply Circuit Recycling Charge in Adiabatic Dynamic CMOS Logic Circuits

Proc. of the second IEEE International Workshop on Electronic Design, Test, and Applications

In this paper, a power supply circuit is proposed for adiabatic dynamic CMOS logic circuit. Charge in load capacitors of gates can be recycled by using this power supply circuit. It leads to lower power consumption than without recycling. In this paper, source voltage of adiabatic dynamic CMOS inverter chain circuits is supplied with the circuit to evaluate the usefulness of the circuit. The results show that the circuits can work with smaller power consumption than without recycling.


Practical Fault Coverage of Supply Current Tests for Bipolar ICs

Bipolar logic circuits are indispensable for implementing high-speed logic circuits. Since quiescent supply current flows into the circuits without faults, they can not be tested by a conventional IDDQ test method. We proposed a quiescent supply current test method which is applicable for the bipolar circuit tests, and examined the testability of open faults under an ideal assumption that there are not any process variations. Actually, there are some variations in the quiescent supply current of each gate in implemented logic circuits. Thus, It is necessary to examine the practical testability of the test method before applying to production tests of bipolar logic ICs. In this paper, the practical testability obtained under an assumption that there are some unit-to-unit variations of supply current among gates is examined for ISCAS-85 benchmark circuits. The experimental results show that larger fault coverage can be obtained with a smaller number of test input vectors by our supply current test method than the functional test one based on stuck-at fault models.


CMOS Open Fault Detection by Appearance Time of Switching Supply Current

In this paper, a new dynamic supply current test method is proposed for detecting open defects on signal lines in CMOS logic circuits. The method is based on the appearance time of dynamic supply current that flows when a test input vector is provided to a circuit under test. Also, we introduce our designed sensor circuit of the appearance time. Feasibility of tests based on the test method is examined by some experiments. The experimental results show that open defects on signal lines in CMOS logic circuits will be detected by the test method.


In this paper, an IDDQ test time reduction method is proposed which is suitable for BIST approaches. Also, a BIST circuit for IDDQ tests, based on the method, is proposed. The layout of a CMOS logic circuit having the BIST circuit is designed and the performance is evaluated by SPICE simulation. The results show us that IDDQ test time can be reduced by using this test circuit.


Testability of Supply Current Test in an AGC Circuit

Proc. of 2003 International Technical Conference on Circuits/Systems, Computers and Communications

In this paper, it is examined whether AGC circuits can be tested by measuring supply current of the circuits. A general AGC circuit is designed and a fault, which is one of shorts, opens and parametric faults, is inserted to the circuit. Supply current waveforms of faulty circuits are derived by circuit simulation and compared to the one of the fault-free circuit. The experimental results show that many faults in the AGC circuit can be detected by measuring the supply current.


Testability of Pin Open in Small Outline Package ICs by Supply Current Test

Proc. of the 2003 International Technical Conference on Circuits/Systems, Computers and Communications


Electric Field Application Method Effective for Pin Open Detection Based on Supply Current in CMOS Logic Circuits

Proc. of International Conference on Electronics Packaging


Simplification of Incompletely Specified Machine Based on Genetic Algorithm Implementing Dormant Mechanism

3rd Workshop on RTL and High Level Testing (WRTLT02)


Test Time Reduction for IDDQ Testing by Arranging Test Vectors

In this paper, test time reduction for IDDQ testing is discussed. Although IDDQ testing is known to be effective in detecting faults in CMOS circuits, the test time of IDDQ testing is larger than that of logic testing. It is shown that the test time of IDDQ test mostly depends on the switching current. To reduce the test time of IDDQ testing, a procedure to arrange test vectors such that the switching current quickly disappears is proposed for combinational circuits. The procedure utilizes a unit delay model to estimate the time of the last transition of logic values from low to high in a circuit. Experimental results for benchmark circuits show the effectiveness of the procedure.


Oscillation Frequency Estimation for Detecting Feedback Bridging Faults

Proc. of 2002International Technical Conference on Circuits/Systems, Computers and Communications

When a feedback bridging fault is activated in a circuit, logical oscillation may occur at a signal line. If the oscillation appears, the fault may not be detected by logic testing. In order to detect such bridging faults, output logic values of the circuit should be measured at higher frequency than frequency of the logical oscillation. In this paper, a method for estimating the maximum frequency of logical oscillation is proposed to detect such bridging faults in a circuit by logic testing. Also, it is shown by some experiments that such bridging faults can be detected by measuring output logic values at the frequency obtained by the method.


Testability of Current Testing for Open Faults Undetected by Functional Testing in TTL Combinational Circuits

A new test approach based on a supply current test method is proposed for testing open faults in bipolar logic circuits. In the approach, only the open faults are detected by the supply current test method, which are difficult to be detected by functional test methods. The effectiveness of the approach is examined experimentally on open fault detection in TTL combinational circuits. The results shows that higher fault coverage can be established by applying a small number of test input vectors of the supply current test method after test vectors of functional test methods based on stuck-at models.


Power-off Vectorless Test Method for Pin Opens in CMOS Logic Circuits

A new test method is proposed in this paper for detecting pin opens in CMOS logic circuits fabricated on printed circuit boards, which are generated by missing solder and so on. Our test method is based on the current which flows through a protection circuit connecting to each pin by supplying a voltage source between the targeted pin and VSS line of a circuit under test. The test method does not require test input generation. When a pin open occurs, smaller current will be supplied from the voltage source than in the case of the fault-free circuit. Our test method uses the property for detecting pin opens. In this paper, the feasibility of the test method is evaluated by some experiments.


Power Supply Circuit for High Speed Operation of Adiabatic Dynamic CMOS Logic Circuits

Proc. of the IEEE International Workshop on Electronic Design, Test, and Applications

In this paper, a power supply circuit is proposed for adiabatic dynamic CMOS logic circuits proposed by K. Takahashi et. al. With this supply circuit, the circuits can work at higher speed. In this paper, source voltage of adiabatic dynamic CMOS inverter gates is supplied by the circuit and the power consumption is examined. The results show that the gates can work with smaller power dissipation than conventional static CMOS circuits


Random Pattern Testability of the Open Defect Detection Method using Application of Time-variable Electric Field

In this paper, random pattern testability of the open defect detection method is discussed. In the test method, time-variable electric field is applied from the outside of ICs so as to vary the voltage at floating nodes caused by a defect. To detect opens the excessive supply current caused by the applied electric field is measured. The test pattern requirements for detecting opens are shown. The fault coverage for open defects is calculated for benchmark circuits. The experimental results shows random pattern can be effectively utilized for the test method even if it cannot attain high fault coverage for stuck-at-faults


CMOS Open Defect Detection Based on Supply Current in Time-variable Electric Field and Supply Voltage Application

In this paper, a new test method is proposed for detecting open defects in CMOS ICs. The method is based on supply current of ICs generated by applying time-variable supply voltage and electric field from the outside of the ICs. The feasibility of the test is examined by some experiments. The empirical results show that, by using the method, open defects in CMOS ICs can be detected. Also, the test input vectors for the test method are proposed and it is shown that they can be generated more easily than functional test methods based on stuck-at fault models


Sequential Redundancy Removal Using Test Generation and Multiple Unreachable States

In this paper, a procedure to reduce sequential circuits by removing undetectable faults in sequential circuits is proposed. To identify whether an undetectable fault is removable or not, strongly unreachable states, which are the states with no incoming transitions, are utilized. It is proved that part of undetectable faults related to strongly unreachable states can be removed from a circuit. Test generation method is used to find undetectable faults related to two or more strongly, unreachable states. Experimental results for ISCAS benchmark circuits are shown


Test Pattern for Supply Current Test of Open Defects by Applying Time-variable Electric Field

Proc. of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Test input vectors for a supply current test method are discussed which is used for detecting open defects in CMOS ICs. In the test method, time-variable electric field is applied from the outside of ICs so as to vary the voltage at a floating node. To generate excessive supply current by the induced voltage change at the floating node, test pattern must be provided so that a conducting path from VDD to GND can be generated in the faulty circuit. In this paper, the requirements are denoted to be satisfied as a test input vector of the test method. Also, it is shown that test pattern of functional tests based on stuck-at fault models can be used for the open defect detection method. Furthermore, the experimental results in this paper promise that high fault coverage can be achieved by applying the subset of the stuck-at test pattern to the detection of open defects


Proc. of 2001 International Technical Conference on Circuits/Systems, Computers and Communications


Fault Simulator for Test Program Generation in Supply Current Tests of Microprocessor Based Boiler Control Circuits


Pin Open Detection Method Based on Supply Current in Time-variable Magnetic Field


Supply Current Test for Pin Opens in CMOS Logic Circuits

Proc. of International Conference on Electronics Packaging


CMOS Open Defect Detection by Supply Current Test

Proc. of Design, Automation and Test in Europe Conference 2001

In this paper, a new test method is proposed for detecting open defects in CMOS ICs. The method is based on supply current of ICs generated by applying time-variable electric field from the outside of the ICs. The feasibility of the test is examined by some experiments. The empirical results promised that, by using the method, open defects in CMOS ICs can be detected by measuring supply current which flows when time-variable electric field is applied


High Speed IDDQ Test and Its Testability for Process Variation

A new high speed IDDQ test method is proposed. It is based on charge current for load capacitances of gates whose output logic values are changed from L to H by test input vector application. In this paper, the testability of the test method is examined for some process variations generated in CMOS IC production


Testability Analysis of IDDQ Testing with Large Threshold Value

IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

By using large threshold value in IDDQ tests, test time can be shortened. However, the fault coverage of the IDDQ tests will be affected by process variation. In this paper, effects on fault coverage of IDDQ tests generated by variations of zero biased threshold voltage of each MOS transistor in a circuit under test are examined with a circuit simulator. The result suggests us that IDDQ testing with large threshold value is applicable to production tests of CMOS ICs


Power Supply Circuits with Small Size for Adiabatic Dynamic CMOS Logic Circuits

Proc. of 2000 International Technical Conference on Circuits/Systems, Computers and Communications


Practical Fault Coverage of Supply Current Testing for Open Fault in TTL Combinational Circuits


A Test Input Sequence for Test Time Reduction of IDDQ Testing

It is shown that IDDQ testing is very useful for shipping fault-free CMOS ICs. However, test time of IDDQ testing is extremely larger than one of logic testing. In this paper, a new test input sequence generation methodology is proposed to reduce the test time of lDDQ testing. At first, it is shown that IDDQ test time will be denominated by charge supply current for load capacitance of gates whose output logic values are changed by test input vector application and the charge current depends on input sequence of test vectors. After that, a test input sequence generation methodology is proposed, The feasibility is checked by some experiments.


IDDQ Testable Design of Static CMOS PLAs with Low Power Consumption


Oscillation Frequency Estimation of Feedback Bridging Faults for Test Circuit Design


Synthesis for Testability by Adding Transitions of Undefined States to State Transition Tables

In this paper we propose procedures to enhance testability by modifying state transition tables. In these procedures, transitions about undefined states, which are not described in state transition tables but exist in a synthesized gate level circuit, are added to a state transition table. Experimental results for MCNC benchmarks are shown.


IDDQ Testable Design of Static CMOS PLAs

IEEE International Workshop on Defect Based Testing

A new IDDQ testable design method is proposed for static CMOS PLA circuits. A testable PLA circuit of NOR-NOR type is designed by using this method. It is shown that all bridging faults in NOR planes of the testable designed PLA circuit can be detected by IDDQ testing with 4 kinds of test input vectors. The test input vectors are independent of the logical functions to be realized in the PLA circuit. PLA circuits are designed by using this method so that quiescent supply current generated when they are tested can be zero. Thus, high resolution of IDDQ tests for the PLA circuits can be obtained by using this testable design method.


Identification of Feedback Bridging Faults with Oscillation

When a feedback bridging fault occurs in a combinational circuit and it is activated, logical oscillation may be generated in the circuit. In this paper, the necessary conditions are presented for feedback bridging faults to generate logical oscillation. Also, a method is proposed to identify such faults in feedback bridging ones. It is based on piecewise-linearized models obtained from input/output characteristics of logic gates and does not require circuit simulation of large size of circuits to identify them. In the experiments for evaluating the method, all of the feedback bridging faults to generate logical oscillation are identified by using the method


Supply Current testing for Bridging Faults in Microprocessor Based Sequence Control Circuits

Proc. of Electronic Circuits World Convention 8


Power Supply Circuit for Adiabatic Dynamic CMOS Logic Circuits

Proc. of 1999 International Technical Conference on Circuits/Systems, Computers and Communications


State Reduction of Incompletely Specified Machines based on Genetic Approach

The 1999 International Technical Conference on Circuits/Systems, Computers and Communications


A High Speed IDDQ Sensor for Low Voltage ICs


Test Input Generation for Supply Current Testing of Bridging Faults in Bipolar Combinational Logic Circuits

Proc. of the IEEE International Workshop on IDDQ Testing


CMOS SRAM Functional Test with Quiescent Write Supply Current


Supply Current Measurement Circuit for Bridging Fault Detection in Microprocessor Based Circuit

Proceedings of ITC-CSCC'97 International Technical Conference on Circuits Systems, Computers and Comunications


Genetic Approaches to State Reduction of Incompletely Specified Machines

The 1997 International Technical Conference on Circuits/Systems, Computers and Communications


Supply Current Test Program for Pin Short Detection in Z80

Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers


Power Consumption of a Time Varying Power Supplied Dynamic CMOS Adder

時変電源電圧駆動ダイナミックCMOS加算器の消費電力評価

電気関係学会四国支部連合大会講演論文集


Testability Evaluation of Open Faults in Consideration of the Voltage of the Adjacent Lines

隣接信号線の電圧値を考慮する断線故障の検査可能性評価

電気関係学会四国支部連合大会講演論文集


Design of Scan Tree Configuration of Sequential Circuits using CAD

スキャンツリー構成順序回路のCADによる設計

電気関係学会四国支部連合大会講演論文集


Torelance of a Built-in IDDQ Test Circuit for Process Variation

組み込み型IDDQテスト回路の製造ばらつきの影響

電気関係学会四国支部連合大会講演論文集


Testabillity Analysis System of IDDQ Testing Based on Wavelet Transformation

ウェーブレット変換を用いたIDDQテスト法の検査能力評価システム

電気関係学会四国支部連合大会講演論文集


Effects on Testability of Logic Value Outputting to Faulty Line in Lead Open Detection by Supply Current Testing

交流電界印加時のリード浮き電流テストでのリード浮き発生信号線への出力論理値の影響

電気関係学会四国支部連合大会講演論文集


Power Consumption in a Time Varying Power Supplied Dynamic CMOS Timer Circuit

時変電源電圧駆動ダイナミックCMOS時計回路の消費電力評価

電子情報通信学会ソサイエティ大会講演論文集


At-Speed Test for Pin Shorts in Z80 by Supply Current Testing

電源電流によるZ80ピン間ブリッジ故障の実時間テスト

電子情報通信学会ソサイエティ大会講演論文集


Fail-safe Evaluation System for Boiler Control Circuits

ボイラ制御回路のフェールセーフ性自動評価システム

電気関係学会四国支部連合大会講演論文集


A Supply Current Test Method for Pin Shorts in PIC ICs

PICの電源電流によるピン間ブリッジ故障検出法

電気関係学会四国支部連合大会講演論文集


Detection of Open Fault Realized by Transmission Gate with IDDT Disappearance Time Detection Circuit

IDDT消滅時間検出回路による伝送ゲートで模擬した断線故障の検出

電気関係学会四国支部連合大会講演論文集


Operating Speed of Dynamic CMOS Logic Circuit Driven by Supply Voltage of Rectangle Waveform

矩形波電圧源駆動ダイナミックCMOS論理回路の動作速度

電気関係学会四国支部連合大会講演論文集


IDDQ Test Circuit with a High Speed External Current Sensor

ゲートの負荷容量の高速充電による高速IDDQテスト回路の開発

電気関係学会四国支部連合大会講演論文集


Testability of Supply Current Testing for DA Converters of Resistor String Type

抵抗ストリング型DA変換器の電流テストの可能性

電気関係学会四国支部連合大会講演論文集


Pin Open Detection in CMOS TQFP ICs of Low Supply Voltage by Measuring Supply Current under AC Electric Field

低電源電圧CMOS TQFP ICの交流電界印加時の電流テストによるピン浮き検出

電気関係学会四国支部連合大会講演論文集


Deterministic Test Vector Generation of Supply Current Test for Open Faults Undetected by Functional Tests in TTL ICs

TTL IC内の論理値テストによる未検出断線故障に対する電流テストの検査入力生成

Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers

電気関係学会四国支部連合大会講演論文集


Spice Model for Deriving Fault Model of Charge Coupled Devices

CCDの故障モデル導出のためのSpiceモデルの開発

電気関係学会四国支部連合大会講演論文集


Constructing Scan Trees based on a Circuit Structure

回路構造を基にするスキャンツリー構成法

電気関係学会四国支部連合大会講演論文集


Test Generation for Sequential Circuits using Structure Based Partitioning

構造分割による状態集合を用いた順序回路のテスト生成

電気関係学会四国支部連合大会講演論文集


A Power Supply Circuit for Dynamic CMOS Logic Circuits

ダイナミックCMOS論理回路のゲートの負荷容量の電荷回収可能な時変電源回路

電気関係学会四国支部連合大会講演論文集


低消費電力ダイナミックCMOS論理回路

電気関係学会四国支部連合大会講演論文集


IDDT Test Circuit for Detecting Open Faults in CMOS ICs

IDDTによるCMOS IC 内断線故障検査回路

電気関係学会四国支部連合大会講演論文集


Fail-safe Analysis for a Breaker Valve Circuit in a Boiler Control Circuit

ボイラ制御用遮断弁回路の動作時のフェールセーフ性の評価

電気関係学会四国支部連合大会講演論文集


Pin Open Detection for CMOS Logic ICs of TQFP Package by Measuring Supply Current under AC Electric Field

交流電界印加時の電源電流によるCMOS TQFP ICのピン浮き検出

電気関係学会四国支部連合大会講演論文集


IDDQ Testing with Wavelet Transformation Technique

ウェーブレット変換を用いたIDDQテストの可能性評価

電気関係学会四国支部連合大会講演論文集


Practical Fault Coverage of Supply Current Tests for TTL ICs

TTL IC内故障に対する電流テストの現実的故障検出率

電気関係学会四国支部連合大会講演論文集


Testability of Current Tests in an AGC Circuit

AGC回路の電流テストの可能性評価

電気関係学会四国支部連合大会講演論文集


Bridging Faults for Oscillation Frequency to be Estimated for the Fault Detection

ブリッジ故障検出のための発振周波数予測対象故障について

電気関係学会四国支部連合大会講演論文集


Finding Invalid States Using Strongly Unreachable States

強到達不能状態を用いる無効状態探索法

電気関係学会四国支部連合大会講演論文集


An Improvement of Generating Test Sequence for Test Time Reduction of Current Testing

電流テスト時間短縮のための検査入力系列生成法の改良

電気関係学会四国支部連合大会講演論文集


Reduction of Test Vectors by Focusing on the Number of Detection of Stuck-at Faults in Combinational Circuits

縮退故障の検出回数に着目した組合せ回路のテストベクトル数の削減

電気関係学会四国支部連合大会講演論文集


Test Set Compaction for Supply Current Test of Open Defects in CMOS ICs

電流テストによるCMOS ICの断線故障検出法におけるテスト集合圧縮

電気関係学会四国支部連合大会講演論文集


Noise Removal for IDDQ Testing by Wavelet Transformation

IDDQテストのためのウェーブレット変換によるノイズ除去

Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers

電気関係学会四国支部連合大会講演論文集


Feasibility of IDDQ Test Time Reduction by Changing Test Input Application Interval

検査入力印加間隔可変によるIDDQテスト時間短縮の可能性評価

電気関係学会四国支部連合大会講演論文集


A Power-off Test Method for IC Pin Opens

ICピン浮きのパワー·オフ·テスト法

電気関係学会四国支部連合大会講演論文集


Feasibility of Pin Open Detection in BGA ICs by Supply Current Test under AC Magnetic Field

BGA ICの交流磁界印加時の電流テストによるピン浮きの検出可能性

電気関係学会四国支部連合大会講演論文集


Pin Open Detection for CMOS Logic ICs of PLCC Package by Measuring Supply Current under AC Electric Field

交流電界印加時の電源電流によるCMOS PLCC ICのピン浮き検出

電気関係学会四国支部連合大会講演論文集


Effectivity of Current Testing for Open Faults Undetected by Functional Testing in TTL Combinational Circuits

TTL組合せ論理回路の論理値テストによる未検出断線故障に対する電流テストの有効性

電気関係学会四国支部連合大会講演論文集


Logic Simulator for Test Input Sequence Evaluation for IDDQ Testing

IDDQテスト用検査入力系列評価に用いる論理シミュレータの開発

電気関係学会四国支部連合大会講演論文集


Evaluation of Stuck-at Pattern and Random Pattern in Supply Current Test of Open Defects

電流テストによるCMOS ICの断線故障検出法における縮退故障の検査入力と乱数パターンの評価

電気関係学会四国支部連合大会講演論文集


Sequential Redundancy Removal Based on Multiple Unreachable States

複数の到達不能状態を考慮する順序回路の冗長除去法

電気関係学会四国支部連合大会講演論文集


Finding Unreachable States with Reducing Search Space

探索空間省略による到達不能状態探索法の効率化

電気関係学会四国支部連合大会講演論文集


Power Consumption in High Speed ADCL Circuits

ADCL回路の高速動作用電源回路による回路動作時の消費電力

電気関係学会四国支部連合大会講演論文集


Experimental Evaluation of Pin Open Detection Method with Time-variable Magnetic Field

交流電界印加によるICピン浮きの検出実験

電気関係学会四国支部連合大会講演論文集


Preventive Saturation Amplifier of Electrical Diagnostic System for Entrapment Neuropathy

圧迫性神経障害の電気診断装置のための飽和防止アンプの開発

電気関係学会四国支部連合大会講演論文集


Fault Coverages of Supply Current Testing for Open Faults in TTL Circuits

TTL組合せ回路の断線故障に対する電流テスト法の故障検出能力

電気関係学会四国支部連合大会講演論文集


A Solder Floating Test by Current Testing with AC Electric Field Applied

交流電界印加時の電流テストによるICピン浮き検出法

電気関係学会四国支部連合大会講演論文集


Functional Fault Simulator for Bridging Faults in Boiler Control Microcomputer

ボイラ制御用マイクロコンピュータの短絡故障シミュレータの開発

電気関係学会四国支部連合大会講演論文集


Synthesis for Testability by Adding State Transitions and Redundancy Removal

状態遷移表への遷移追加と冗長除去によるテスト容易化

Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers

電気関係学会四国支部連合大会講演論文集


A Test Input Sequence for Test Time Reduction of IDDQ Testing

伝搬遅延時間の短い検査入力系列によるIDDQテストの高速化

電気関係学会四国支部連合大会講演論文集


Open Fault Detection Based on Supply Current in CMOS ICs

交流電界印加時の電源電流によるCMOS IC内断線故障検出法

電気関係学会四国支部連合大会講演論文集


Oscillation Frequency Estimation Method of Feedback Bridging Faults

フィードバックブリッジ故障の発振周波数予測法

電気関係学会四国支部連合大会講演論文集


Improvement of IDDQ Testable Design for Static CMOS PLAs

スタティック型CMOS PLAの電流テスト容易化設計法の改良

電気関係学会四国支部連合大会講演論文集


High Speed Current Test Circuit for CMOS Logic Circuits

CMOS論理回路の高速電流テスト用検査回路

電気関係学会四国支部連合大会講演論文集


Power Supply Circuit for High Speed ADCL Circuits

ADCL回路駆動用矩形波電源回路

電気関係学会四国支部連合大会講演論文集


At-Speed Current Test Method of Open and Short Defects at Buses in Microcomputers

マイクロコンピュータ回路のバス故障の実時間テスト法

第54回FTC研究会資料

第54回FTC研究会資料


On Configuring Scan Trees for Multiple-core Design Based on Circuit Structure

回路構造に基づく複数コアのスキャンツリー構成

第54回FTC研究会資料

第54回FTC研究会資料


On Test Generation for Sequential Circuits Using Limited Scan Operation Considering Initial States

初期状態を考慮する部分スキャンシフトを用いたテスト生成について

第52回FTC研究会資料

第52回FTC研究会資料


Extraction of Fault Candidate Areas with Layout Information

レイアウト情報を用いた故障候補エリアの抽出

電子情報通信学会技術研究報告

Institute of Electronics, Information and Communication Engineers

In this paper, we present a method for extracting fault candidate areas using layout information obtained by CAD. In highly-integrated circuits, a bridging fault may affect not only between two signal lines, but also among multiple signal lines. In this work, we propose a procesure for extracting fault candidate areas of bridging faults between two lines and bridging faults among three lines. The procedure extracts pairs of signal lines whose distance is within the given distance and identifies them as the fault candidate of a bridging fault, and also extracts groups of three signal lines within the given distance and identifies them as the fault candidate of a multinode bridging fault. The procedure that utilizes a layout information obtained from CAD tools to extract fault candidate areas of bridging faults among two or three lines is shown. The experimental results for benchmark circuits are shown for the comparison between the number of the fault candidate areas obtained by the proposed method and the number of the bridging faults between two lines assumed from gate-level.

本論文では,CADによるレイアウト情報を用いた故障候補エリアの抽出について述べる.集積度の高い回路においては,ブリッジ故障が2線間のみならず複数信号線に影響をもたらす可能性がある.本研究では,2信号線間のブリッジ故障と3信号線間のブリッジ故障を仮定し,その故障候補エリアの抽出法を提案する.本手法では,信号線間の距離が,ある一定間隔内である信号線の組をブリッジ故障候補とし,その間隔内に存在する3つの信号線の組を複数信号線間ブリッジ故障候補として抽出する.CADツールより得られるレイアウト情報から,2信号線間および,3信号線間のブリッジ故障候補エリアの抽出を行う手法について提案し,ベンチマーク回路に対するブリッジ故障候補エリア抽出実験から得られた故障候補エリア数とゲートレベルにて仮定される2線間のブリッジ故障数との比較結果を示す.


ウェーブレット変換を用いるIDDQテスト法

第50回FTC研究会資料

第50回FTC研究会資料


Test Generation for Sequential Circuits by Logic Simulation using State Partitioning

状態集合分割を用いる論理シミュレーションによる順序回路のテスト生成

電子情報通信学会技術研究報告

本論文では,状態集合分割を用いた論理シミュレーションによるテスト生成について述べる.本研究で行うテスト生成では,複数の候補ベクトルを作成し,未到達状態へ遷移可能なベクトルをテストベクトルとして採用する.故障検出に有効な状態遷移を得るために,フリップフロップを複数の集合に分割し,重み付けによる状態変化の優先度の設定を行う.状態集合の分割法として,フリップフロップの論理値の制御容易性に基づく分割法と,未検出故障への影響の大きいフリップフロップを回路構造から求め集合分割を行う手法の2つを用いる.本研究では各未検出故障の励起,伝搬に必要なフリップフロップを考慮した集合分割を用いることで,未検出故障の検出に必要な状態遷移を優先する.提案する集合分割法をテスト生成に適用した結果により,集合分割法の有効性について示す.


Built-in Supply Current Sensor Circuit for Detecting Open Faults in CMOS ICs

CMOS ICの断線故障検出用電流センサ回路

第49回FTC研究会資料

第49回FTC研究会資料


AC Electric Field Application Method in Supply Current Tests for IC Pin Open Detection

電流テストによるICピン浮き検出のための外部交流電界印加法

第48回FTC研究会資料

第48回FTC研究会資料


Oscillation Frequency Estimation for Detecting Feedback Bridging Faults

発振を生じるフィードバックブリッジ故障検出のための発振周波数予測法

第47回FTC研究会資料

第47回FTC研究会資料


A Test Input Sequence for Test Time Reduction of IDDQ Testing

検査入力系列並び換えによるIDDQテスト時間の短縮化

第46回FTC研究会資料

第46回FTC研究会資料


Pin Open Detection Method Based on Supply Current in Time-variable Magnetic Field

電流テストによるICピン浮き検出のための外部交流電界印加法

第45回FTC研究会資料

第45回FTC研究会資料


On Detecting CMOS Open Defect by Applying Electric Field and Generating Its Test Pattern

外部交流電界印加によるCMOS ICのオープン故障検出法と検査入力生成について

第44回FTC研究会資料

第44回FTC研究会資料


Adding Transitions of Undefined States to State Transition Tables for Testability Enhancement

In this paper we propose procedures to enhance testability by adding transitions of undefined states to state transition tables. In these procedures, transitions about undefined states, which are not described in state transition tables but exist in a synthesized gate level circuit, are added to a state transition table. Experimental results for MCNC benchmarks are shown.


Power Supply Circuit for Adiabatic Dymanic CMOS Circuits

断熱的ダイナミックCMOS論理回路用電源回路

電子情報通信学会技術研究報告

本論文では，断熱的ダイナミックCMOS論理回路用の電源回路を提案している．断熱的ダイナミックCMOS回路では従来のCMOS論理回路の場合のような一定電圧でなく, 正弦波や三角波のような時変電圧を発生する電源を必要とする．断熱的ダイナミックCMOS回路の動作速度はその電源波形の周波数で決まることから, 高速に電源電圧を変化させ, かつ寄生容量に蓄積されたエネルギーを急速に回収できる電源が必要である．本論文ではそれが可能な電源回路を提案し, 断熱的ダイナミックCMOSインバータ回路を駆動し, その消費電力を回路シミュレーションにより調査している．その結果は, ADCL回路を本電源回路で駆動することにより, 従来のCMOS回路に比べ大幅な低消費電力化が実現できることを示している．


A Method for Removing Sequentially Redundant Lines Simultaneously Based on Unreachable States

到達不能状態に基づく順序回路の冗長信号線の同時除去法

電子情報通信学会技術研究報告

We propose a redundancy removal method based on strongly unreachable states, which are states that have no incoming transition from any state. If a fault affects the output sequence or the state transition only when the circuit starts from strongly unreachable states, then the fault is undetectable. More over, if the unreachable states are also strongly unreachable in the faulty circuit, the line corresponding the fault is redundant. In this paper, we present the theorem that the undetectable faults obtained from a strongly unreachable state remain undetectable for the circuit after removing the redundant lines corresponding to one of the faults. We also consider the condition for removing redundant lines simultaneously. Experimental results for benchmark circuits are shown.

本論文では, いかなる状態からの遷移も存在しない強到達不能状態に着目した冗長除去法を提案する. 強到達不能状態における出力と状態遷移だけが正常回路と異なる縮退故障は検出不能故障であり, 故障回路においてもその状態が強到達不能状態であるならば, 対応する信号線は冗長信号線である. 本研究では, 強到達不能状態から得られた検出不能故障は, その一部に冗長除去を行った後の回路においても検出不能となることを示し, 同時除去可能な冗長信号線について考察する. ベンチマーク回路に対する実験結果により, 同時除去可能な冗長信号線があることを示す.


上肢切断者のための顔面方位による計算機への入力キー選択法

上肢切断者のための顔面方位による計算機への入力キー選択法

第14回バイオメカニカルシンポジウム

第14回バイオメカニカルシンポジウム


電源電流による組合せ回路の故障検出法

電源電流による組合せ回路の故障検出法

電子情報通信学会技術研究報告


A Tr-Amplifier Design Utilizing a Circuit Simulator


回路モジュールのタイミングチャートを利用した論理シミュレータ

回路モジュールのタイミングチャートを利用した論理シミュレータ

電子情報通信学会技術研究報告


電源電流波形による論理回路の故障診断法

電源電流波形による論理回路の故障診断法

電子情報通信学会技術研究報告


マイクロコンピュータの編集設計システムの試作

マイクロコンピュータの編集設計システムの試作

情報処理学会設計自動化研究会

情報処理学会設計自動化研究会


内容検索メモリの性能評価

内容検索メモリの性能評価

電子情報通信学会技術研究報告


リープフロッグ形SCF構成法に関する一検討

リープフロッグ形SCF構成法に関する一検討

Institute of Electronics, Information and Communication Engineers