Deep-BMNN: Implementing Sparse Binary Neural Networks in Memory-Based Reconfigurable Processor (MRP)

Proc. of 2024 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)


Dependence of Threshold Values for Interconnect Testing with Relaxation Oscillators on Unit-to-unit Variations of ICs

2024 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)


Design of an Efficient PRPG for Testing an Approximate Multiplier Using Truncation


On the application of boundary scan design with embedded time-to-digital converter to 3D stacked IC

Proc. 2023 IEEE International Test Conference in Asia


On Test Pattern Generation Method for an Approximate Multiplier Considering Acceptable Faults


Evaluation of a PUF Embedded in the Delay Testable Boundary Scan Circuit

Proc. of 2023 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)

In recent years, as a security technology against counterfeit IC, Physically unclonable function (PUF) has been proposed that generates unique values based on manufacturing variability information that is difficult to be replicated. However, it requires area overhead to embed the PUF design into an IC to generate unique responses. In order to reduce the area overhead, we propose a method to make delay testing using design-for-testability also function as a PUF. In addition, we applied the unanimous selection method to generate unique values using the proposed method. We fabricated the prototype ICs in two different manufacturing lots and evaluated the stability and uniqueness of the PUF. The results show that different eigenvalues were generated for all chips, including those with different manufacturing lots.


Enhanced Interconnect Test Method for Resistive Open Defects in Final Tests with Relaxation Oscillators

Resistive open defects may occur at interconnects between a printed circuit board and ICs in solder process. An enhanced test method in final tests and a built-in test circuit are proposed to detect resistive open defects of small resistance with relaxation oscillator embedded in ICs in this paper. It is examined by Spice simulations what resistive open defects can be detected. The results show that resistive open defects of 23.4 Ω and above are detected by the test method in a test speed of 1 MHz per an interconnect.


Detectability of Open Defects at Interconnects between Dies in 3D Stacked ICs with Relaxation Oscillators

Detectability of a test method utilizing a relaxation oscillator is examined by circuit simulations for open defects between dies in 3D stacked ICs, The results show that resistive open defects of O.6Ω above are detected.


Scan Shift Reduction in Delay Testing using Bounary Scan with Embedded TDC

the 22nd IEEE Workshop on RTL and High Level Testing


Detectable Resistance Increase of Open Defects in Assembled PCBs by Quiescent Currents through Embedded Diodes

Proc. of 2021 International Conference on Electronics Packaging (ICEP)

It is discussed in this paper what resistance increase can be detected by an electrical interconnect test method that occurs after shipping to market at interconnects between ICs and printed circuit boards. The test method is based on a quiescent current made flow through a diode embedded for the tests. Independently of the current variations caused by process variations of ICs, we show by Spice simulations that resistance increase of 0.5 Ω can be detected by the test method with a measurement tool of 0.1mV resolution.


Recovery of Defective TSVs with A Small Number of Redundant TSVs in 3D Stacked ICs

the 21st IEEE Workshop on RTL and High Level Testing

A repair circuit is proposed to recover defective Through Silicon Vias (TSVs) in a 3D stacked ICs in this paper. A defective TSV is replaced to a defect-free one in a small number of redundant TSVs with the circuit. The number is specified from yield of TSVs in the fabrication process. The circuit size is small, since the number of redundant TSVs is small. The circuit is evaluated by Spice simulation. The results show that a TSV is connected to a defect-free one with a small area overhead and a small additional delay.


Test Time Reduction of Small Delay Testing for Scan Design with Embedded TDC


Temperature Sensing with a Relaxation Oscillator in CMOS ICs

Proc. of The 35th International Technical Conference on Circuits/Systems, Computers and Communications

Temperature monitoring is indispensable for realizing a long life in ICs, since reliability of ICs is affected by the temperature. We propose a temperature sensor based on an oscillation frequency of a relaxation oscillator embedded in an IC. In order to examine feasibility of the temperature monitoring, we designed a sensor circuit utilizing a relaxation oscillator and examined it by SPICE simulations. The simulation results show that temperatures in ICs can be estimated by a single regression straight line with a small error under process variations of MOSs in the ICs.


On Delay Elements in Boundary Scan Cells for Delay Testing of 3D IC Interconnection

Proc. of The IEEE 2019 International 3D Systems Integration Conference

For testing delay faults in 3D IC interconnection, we have proposed a DFT (Design-for-Testability) method for TSVs using a modified boundary scan circuit with embedded Time-to-Digital Converter (TDCBS). A TDCBS cell has a delay element to form a delay line. In this paper, for improving delay resolution, delay gates that have small propagation delay time are investigated and implemented as a delay line. In order to prevent pulse shrinking of transition signal through a delay line, the proposed cell is designed to reduce the difference in transition delay between the delay for rising transition and for falling transition. The measurement results for an experimental chip show the effectiveness of our new design.


Electrical Field Test Method of Resistive Open Defects between Dies by Quiescent Currents through Embedded Diodes

Dies in 3D stacked ICs are connected with Through-Silicon-Vias or micro bumps. Resistive open defects may occur at interconnects between the dies in fabrication process. The defects may grow to an open circuit fault in the field after shipping to a market. In this paper, a field test method is proposed so as the defect to be detected after shipping to a market before it becomes an open circuit fault. This test method is based on a quiescent supply current that is made flow through an interconnect between dies only in tests. It is shown by Spice simulation that an increase of 0.01Ω is detected by the test method in field tests.


On Delay Measurement under Delay Variations in Boundary Scan Circuit with Embedded TDC

Proc. 2019 IEEE International Test Conference in Asia

With the high integration of integrated circuits, small delay faults have occurred as the cause of a circuit failure. We have proposed a method for testing small delay faults using a boundary scan circuit with embedded TDC (TDCBS). In this method, delay faults are detected by using the number of stages in which a transition signal has propagated through a delay line. However, there exists delay variation in a delay line. This paper investigated delay variation by measuring transition delay for different paths in the delay line. In addition, to calibrate delay variation, we investigated a calibration method for considering the variation of wire length and delay in a delay line in TDCBS. Measurement results for an experimental chip show that the method can compensate the variations in the delay line.


Stand-by Mode Test Method of Interconnects between Dies in 3D ICs with IEEE 1149.1 Test Circuits

In this paper, we propose a stand-by interconnect test method of 3D stacked ICs with IEEE 1149.1 test circuits embedded in dies. Resistive open defects are detected after shipping to a market by the test method that occur at input interconnects of dies operating at a stand-by mode. Feasibility of the stand-by tests is examined by SPICE simulation. It is shown that a resistive open defect of 83kΩ and above can be detected at a test speed of 20MHz by the test method.


Resistive Open Defect Detection in SoCs by a Test Method Based on Injected Charge Volume after Test Input Application

A test method is proposed of resistive open defects in an SoC by means of charge volume injected from the VDD terminal. The charge is injected after providing a test input vector from a charge injector instead of a DC power voltage source. It is shown by Spice simulation that a resistive open defect in four parallel inverter chain circuits of 30 stages whose resistance is larger than 10kΩ can be detected by the test method.


Test Time Reduction on Testing Delay Faults in 3D ICs Using Boundary Scan Design

A boundary scan design with embedded time-to- digital converter (TDCBS) has been proposed for testing small delay faults. In this paper, the TDCBS is applied for testing TSVs in 3D IC. To reduce test application time of the TDCBS, we propose a modified TAP controller that utilizes the bypass mode for reducing unnecessary scan shifts during observation of the captured results. The simulation for an experimental circuit is shown to evaluate the effectiveness of the proposed method. Keywords delay


Resistive Open Defects in 3D Stacked ICs Detected by Electrical Interconnect Testing with a Charge Injector Made of MOS Capacitors

Proc. of 33rd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2018)


On Design and Evaluation of a TDC Cell Embedded in the Boundary Scan Circuit for Delay Fault Testing of 3D ICs


A Sequentially Untestable Fault Identification Method Based on n-Bit State Cube Justification

24th IEEE International Symposium on On-Line Testing and Robust System Design

Non-scan based test generation is required to reduce test cost and improve security. However, sequential test generation consumes a lot of time to identify untestable faults. Therefore, it is important to identify untestable faults in the preprocessing of the test generation. In this paper, an unreachable state identification method, which identifies whether states on a few flip-flops can be justified using SAT, and an untestable fault identification method using the unreachable states are proposed. Experimental results show that our proposed method was effective compared with conventional methods.


Effect of Routing in Testing a TSV Array Using Boundary Scan Circuit with Embedded TDC

Proc. of International Forum on Advanced Technologies 2018


Electrical Tests for Capacitive Open Defects in Assembled PCBs


Resistive Open Defect Detection in 3D ICs with a Comparator of Offset Cancellation Type under Process Variation


Oscillation Frequency Estimation of Ring Oscillator for Interconnect Tests in 3D Stacked ICs

Proc. of 2018 RISP International Workshop on Nonlinear Circuits, Communications

A powerful electrical test method with a ring oscillator has been proposed to detect resistive open defects at interconnects between dies in 3D ICs. An oscillation frequency of the ring oscillator and the testability of the test method may change with temperature. Thus, we designed a ring oscillator and examined what extend the oscillation frequency of the ring oscillator changed with temperature by Spice simulation. The simulation results show that the frequency depends on temperature but is able to be estimated by a linear regression method precisely.


Detectable Resistive Open Defects in 3D ICs with Electrical Interconnect Test Circuit Made of Diodes

We have proposed an electrical test method for detecting open defects that occur at interconnect between dies in 3D ICs and a built-in test circuits for the tests. The test method is based on supply current that is made flowthrough an interconnect to be tested. Testability of the test method may depend on process variation, since the test method utilizes the built-in test circuit. We have examined what resistance of an open defect can be detected by the test method under a process variation by Spice simulation.The results show that resistive open defects of 56 or more can be detected by the test method.


A Sequentially Untestable Fault Identification Method Based on State Cube Justification

the 18th IEEE Workshop on RTL and High Level Testing


Reordering Delay Elements in Boundary Scan Circuit with Embedded TDC


Fault-Aware Page Address Remapping Techniques for Enhancing Yield and Reliability of Flash Memories


Open Defect Detection with a Built-in Test Circuit by IDDT Appearance Time in CMOS ICs


Resistive Open Defects Detected by Interconnect Testing Based on Charge Volume Injected to 3D ICs


A Built-in Current Sensor Made of a Comparator of Offset Cancellation Type for Electrical Interconnect Tests of 3D ICs


A Defective Level Monitor of Open Defects in 3D ICs with a Comparator of Offset Cancellation Type

2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

3D IC内にIEEE1149.1テスト回路が適用されたIC間の接続の欠陥レベルモニタとしてIC内の静的電源電流を用いる手法を提案する．オフセットキャンセル型比較回路を用いることで5Ωの精度での断線故障の観測可能性を示す．


On Selection of Adjacent Lines in Test Pattern Generation for Delay Faults Considering Crosstalk Effects

Proc. of 17th International Symposium on Communications and Information Technologies

With miniaturization of semiconductor manufacturing process, line spacing becomes narrower and hence the influence of coupling capacitance cannot be ignored. The signal delay on a defective line is affected by the signal transitions on its adjacent lines through the coupling capacitance. In addition, the delay size depends on the timing skew between signal transitions on the defective line and its adjacent lines. In test pattern generation, not all adjacent lines are required to have signal transitions to excite the fault effect if a large relative timing skew exists between the faulty line and the adjacent line. In this paper, we propose a selection method of adjacent lines for assigning signal transitions in test pattern generation. The proposed method can reduce the number of adjacent lines used in test pattern generation without degrading the quality of test pattern that can excite the fault effect.


A Defect Level Monitor of Resistive Open Defect at Interconnects in 3D ICs by Injected Charge Volume

Resistive open defects may occur at interconnects among dies in 3D stacked ICs. A defect level monitor is proposed so as for the defects to be detected before they change into a hard open defect that generates logical errors. The changing process of resistive open defects is monitored by means of charge volume injected from the monitor. It is shown by Spice simulation that resistive open defects whose resistance is greater than 2Ω can be detected by online tests with the monitor before changing them to hard open defects in the field.


Capacitive Open Detection in 3D ICs with A Built-in Comparator of Offset Cancellation Type

IEEE 2017 Taiwan and Japan Conference on Circuits and Systems


A Built-in Test Circuit Using A Comparator of Offset Cancel Type for Electrical Interconnect Tests of 3D Stacked ICs

Proc. of International Forum on Advanced Technologies 2017


Test Input Vectors for Detecting Stuck-at Faults at Address and Data Buses in 3D Stacked Memory ICs


A Modified PRPG for Test Data Reduction Using BAST Structure

Proc. RISP International Workshop on Nonlinear Circuit and Signal Processing


Capacitive Open Defect Detection by Electrical Interconnect Test of 3D ICs without Boundary Scan Flip Flops

Proc. of the 17th IEEE Workshop on RTL and High Level Testing

Three-dimensional (3D) integration using Through-Silicon Via (TSV) has been proposed as an excellent alternative to cope with the challenges faced by the current 2D technology. A 3D IC using TSV is fabricated by stacking multiple dies and vertically connected by TSVs and/or micro bumps. This enables the interconnects in the 3D IC to be shortened and high performance improvement to be achieved. However, there are open defects, such as voids and cracks, that occur between dies in 3D IC that can decrease the performance of the chip. Conventionally, a boundary scan embedded inside IC is used in order to test the interconnects. On the other hand, there is also a case where the IC not embedded with boundary scan is used. In this paper, we propose an electrical test circuit of 3D IC that does not implement boundary scan flip flops. The testability of the electrical test is evaluated by SPICE simulation. Capacitive open defects occuring at interconnect are detected by the test method. Simulation results show that capacitive open defect generating no logical errors can be detected by our method at a test speed of 1MHz.


On Control Circuit and Observation Conditions for Testing Multiple TSVs Using Boundary Scan Circuit with Embedded TDC

In this study, we design the control circuit for boundary scan circuit with embedded Time-to-Digital Converter (TDCBS) and derive the observation condition of delay amounts of TSVs (Through Silicon Via) to implement TDCBS for testing TSVs in 3-Dimensional IC (3DIC). TSVs may cause small delay fault that is impossible to detect using conventional logic testing methods due to the complexity of the manufacturing process of interconnects in 3DIC including TSVs and microbumps. Although we have been proposed a DFT (Design For Testability) method for TSVs using TDCBS, the application of TDCBS in 3DIC will cause an increase in number of dedicated control pins and TSVs. In addition, it maybe difficult to observe each delay amounts of TSV in case of testing multiple TSVs. In this paper, to implement TDCBS for testing TSVs in 3DIC, we designed a circuit which can control the pins inside TDCBS circuit and explain the observation conditions for measuring delay of each TSV in case of testing multiple TSVs.


Testability for Resistive Open Defects by Electrical Interconnect Test of 3D ICs without Boundary Scan Flip Flops

A three-dimensional integrated circuit is fabricated by stacking multiple dies. A resistive open defect may occur at interconnects between the dies by a void and a crack in the fabrication process. We have proposed an electrical test method for an IC made of dies in which boundary scan flip flops are not embedded. In this paper, testability of the test method for resistive open defects is examined by Spice simulation. The results show that a resistive open defect whose resistance is greater than 150 is able to be detected at a test speed of 500kHz.


A Power Supply Circuit for Interconnect Tests Based on Injected Charge Volume of 3D IC

A power supply circuit and an electrical interconnect test method are proposed to detect open defects at interconnects between dies in 3D ICs. The test method is based on the amount of charge injected from the power supply voltage source. It is shown by Spice simulation that resistive open defects whose resistance is greater than 20 can be detected with the power supply circuit by the test method.


A Built-in Defective Level Monitor of Resistive Open Defects in 3D ICs with Logic Gates

Resistive open defects in 3D ICs may change into hard open ones. In this paper, a built-in test circuit is proposed to monitor the changing process of the resistive open defects occurring at interconnects between dies embedding an IEEE 1149.1 test circuit. Feasibility of the process monitoring is examined experimentally in a PCB circuit made of ICs embedding the test circuit. It is shown that the changing process of a resistive open defect can be monitored at a test speed of 500 kHz.


Electrical Tests for Capacitive Open Defects in Assembled PCBs

Proc. of International Design and Concurrent Engineering Conference 2016


Electrical Test of Resistive and Capacitive Open Defects at Data Bus in 3D Memory IC

an electrical test method of resistive and capacitive open defects occurring at data bus lines between dies in a 3D memory IC is proposed. The test method is based on supply current of the IC. The number of test vectors for a 3D memory IC made of ND memory dies in the test method is 10*ND and small. Also, a defective interconnect is located by the test method. Feasibility of the tests is examined by some experiments for a circuit made of an SRAM IC on a printed circuit board. The experimental results show that a capacitive open defect and a resistive open one whose resistance is greater than 200 can be detected by the test method.


A Built-in Test Circuit for Injected Charge Tests of Open Defects in CMOS ICs

Proc. of International Technical Conference on Circuits/Systems, Computers and Communications 2016

CMOS ICの断線故障検査のために電圧源からの注入電荷量に基づき故障判定を行う手法を提案する．試作ICに提案回路を実装し，実験により検査可能性について評価する．


A Built-in Test Circuit to Monitor Changing Process of Resistive Open Defects in 3D ICs

抵抗性断線欠陥の進行プロセスを監視するための3D IC用組込みテスト回路を提案する．IEEE1149.1テスト回路と検査容易化設計された入出力バッファを用いた提案回路における監視の可能性をシミュレーションにより評価する．


A Built-in Electrical Test Circuit for Detecting Open Leads in Assembled PCB Circuits with RC Integrator

Proceedings of International Conference on Electronics Packaging 2016

BGA ICのリードとプリント基板間の断線について積分回路により生成する時変信号を印加することで検査する組込み電気的検査回路を提案する．断線故障は入力バッファをセンサとして用いることで電源電流の異常として検出される．


Electrical Tests of Capacitive Open Defects at BGA ICs in Assembled PCB

Proc. of International Forum on Advanced Technologies 2016


Die Design for Cost reduction of 3F Stacked Memory ICs


Feasibility of Electrical Test for Open Defects at Address Bus in 3D Memory IC


Test Circuit for Electrical Interconnect Tests of 3D ICs without Boundary Scan Flip Flops

Proc. of the 16th IEEE Workshop on RTL and High Level Testing

A test circuit for an electrical interconnect test method is proposed of a 3D stacked ICs made of dies in which boundary scan flip flops are not embedded in this paper. Hard and resistive open defects occurring at interconnects between dies embedding the test circuit are detected by the test method. Feasibility of the electrical tests with the test circuit is evaluated by some experiments in a circuit made of a prototype IC and by Spice simulation. The experimental results show that a hard open defect and a resistive open one are able to be detected by the test method at a test speed of 500Hz. In the simulation results, they are detected at a test speed of 250MHz.


Electrical Interconnect Test Method of 3D ICs without Boundary Scan Flip Flops

3D IC の接続テスト手法として，バウンダリスキャン回路を用いない電気的検査法を提案する．試作回路により実験を行い500kHzの検査速度での完全断線故障と抵抗性断線の検査可能であることを示す．


A Design for Testability with nMOS Switches to Detect Open pins in Assembled PCBs

Proc. of International Design and Concurrent Engineering Conference 2015

ICとプリント基板間のはんだオープンについてnMOSスイッチとダイオードを用いた検査容易化設計を提案する．入力保護回路とICコア間に付加回路を挿入し，バウンダリスキャンテスト回路を用いてテストパターンを印加し，供給電流の測定により検査を行う．シミュレーションと試作ICにより提案手法の有効性を評価する．


On TSV Array Defect Detection Method Using Two Ring-oscillators Considering Signal Transitions at Adjacent TSVs

Proc. of IEEE 3D System Integration Conference 2015


Electrical Interconnect Test Method of 3D ICs by Injected Charge Volume


Electrical Interconnect Test of 3D ICs Made of Dies without ESD Protection Circuits with a Built-in Test Circuit


Electrically Testable CMOS Image Pixel Circuit

Proc. of IEEE 2015 European Conference on Circuit Theory and Design

CMOS画素回路の電気的検査法として，光を照射せずに検査可能な検査容易化設計手法を提案する．SPICEシミュレーションにより断線故障の89%が提案手法にて検出可能であることを示す．


Electrical Test for Open Defects in CMOS ICs by Injected Charge

Proc. of International Technical Conference on Circuits/Systems, Computers and Communications 2015

CMOS ICの断線故障の検査手法として，電源電圧源からの電荷供給量に基づき故障を検出する手法を提案する．インバータチェイン回路内に発生する断線故障に対して提案手法を適用し故障検出が可能であることを示す．


Repair Circuit of TSVs in a 3D Stacked Memory IC

3D IC のシリコン貫通ビアのリペア回路を提案する．故障TSVを正常TSVに接続変更するためのスイッチ回路を設計し，小面積で付加遅延も小さいことをSpiceシミュレーションにて評価した．


A Testable Design for Electrical Interconnect Tests of 3D ICs

Proceedings of 2015 International Conference on Electronics Packaging and iMAPS All Asia Conference

3D ICのダイ間の断線故障を検出する電気的検査法としてIEEE1149.1テスト回路を用いてテストパターンを印加する手法を提案する．シミュレーションにて1GHzのテスト速度の下で完全断線故障と抵抗性断線故障の検出可能性を評価する．


Switch Circuit for Repairing Defective TSVs in a 3D Stacked Memory IC

Proc. of International Forum on Advanced Technologies 2015


A Built-in Supply Current Test Circuit for Electrical Interconnect Tests of 3D ICs

Proc. of IEEE 3D System Integration Conference 2014

3D ICの接続テストのための組込み電流テスト回路を提案する．試作ICとシミュレーションにより，1MHzのテスト速度の下で10nFの容量断線，1kΩの抵抗断線が検出可能であることを示す．


A Test Pattern Matching Method on BAST Architecture for Test Data Reduction by Controlling Scan Shift

Proc. of the 15th IEEE Workshop on RTL and High Level Testing

To reduce test data volume, BIST-Aided Scan Test (BAST) technique that combines Automatic Test Pattern Generator (ATPG) and Built-In-Self-Test had been proposed. In this paper, we propose a test pattern matching method used on BAST architecture which can reduce test data required for bit-flips and skipping random patterns. To find a better matching with less BAST codes, we propose a procedure to modify matching obtained by the previous method. In this procedure, the ATPG pattern matched with the last part in the PRPG patterns is selected to find another matching that can reduce BAST codes. The experimental results for some benchmark circuits are also shown.


On SAT-based Test Generation for Resistive Open Using Delay Variation Caused by Effect of Adjacent Lines

Small delay faults caused by the resistive opens may induce the incorrect operation in present ICs. The small delay is hard to detect since it is difficult to distinguish faulty effect from process variations. Coupling capacitances have greater effect on the faulty circuit than that of the normal circuit. In this paper, we present a procedure for generating test pattern pairs for the resistive open faults by SAT-based ATPG. The difference of the path delay between test pattern pairs is used to detect the resistive open fault. Experimental results for some benchmarks are shown to our proposed method. Furthermore, to estimate a difference of path delay between pattern pairs, we utilize an open fault simulator.


Threshold Setting of Electrical Test Method for Open Defects at Data Bus in 3D SRAM IC

A Threshold setting method of an electrical test method is proposed for detecting an open defect occurring at a data bus of a 3D SRAM IC. Targeted defects are a hard open defect and a soft one in a data bus. The test method is based on supply current of the IC. The threshold setting method is evaluated by some experiments for a circuit made of an SRAM IC on a printed circuit board. The experimental results reveal us that threshold values of the test method should be prepared for each of data buses of memories accessed in the tests and the data stored in them.


Threshold Value Estimation of Electrical Interconnect

An estimation method of a threshold value for electrical interconnect tests is proposed for detecting open defects at interconnects between dies in a 3D IC. Threshold values of a circuit made of our prototyping IC on a printed circuit board are derived by the estimation method. The results show us that resistive open defects whose resistance is larger than 16.1Ω can be detected with a threshold value estimated by the method.


Delay Line Embedded in Boundary Scan for Testing TSVs

Fifth IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits

In this paper, we propose a test method that utilizes a time-to-digital converter (TDC) embedded in boundary-scan design to detect an excessive delay occurred at interconnects in 3D-IC. The boundary scan cells are used as the delay line in the lower die to provide the input transition to the upper die. The input transition is delayed by delay elements and is captured at the boundary scan cells in the upper die. The proposed boundary scan design is implemented in an experimental chip and is examined to evaluate the feasibility to detect delay at TSVs in 3D ICs.


A Built-in Test Circuit for Detecting Open Defects by IDDT Appearance Time in CMOS ICs

Proc. of the 3rd International Conference on Design and Concurrent Engineering


Electrical Test Method of Open Defects at Data Buses in 3D SRAM IC

Proc. of International Conference on Electronics Packaging 2014

An electrical test method is proposed for detecting an open defect occurring at a data bus of a 3D SRAM IC. Targeted defects are a hard open defect and a soft one in a data bus. The test method is based on supply current of the IC. There is no need to add a circuit for the test method to an original circuit. Feasibility of the tests is examined by some experiments for a circuit made of an SRAM IC on a printed circuit board. The experimental results show us that resistive open defects whose resistance is greater than 300 can be detected by the test method.


A Built-in Supply Current Test Circuit for Pin Opens in Assembled PCBs

Proceedings of International Conference on Electronics Packaging 2014

In this paper, a built-in test circuit of electrical tests is proposed to detect pin opens of CMOS ICs. When a circuit is tested by the test method, current is made to flow through a targeted pin. An open defect is detected by means of the difference between the current of a defect-free circuit and the measured one. Feasibility of tests with the built-in supply current test circuit is examined by Spice simulation. It is shown that a pin open in a CMOS IC can be detected with the test circuit at a speed of 1MHz.


Pin Open Detection of BGA IC by Supply Current Testing

In this paper, we propose a test method for detecting pin opens of CMOS logic ICs in assembled PCBs. The test method is based on supply current of a circuit under test which flows when a time-varying signal is provided to a targeted pin with a test probe as a stimulus. Test signal's amplitude is less than VDD. Test vector generations are not needed for the tests. In the test, the test probe also can be checked simultaneously. The test can be used on devices such as BGA ICs which solder parts are hidden from a field of view. We show by some experiments that pin opens of BGA ICs can be detected by the supply current test method.


DFT for Supply Current Testing to Detect Open Defects at Interconnects in 3D ICs

Proc. of IEEE Electrical Design of Advanced Packaging & Systems (EDAPS) Symposium

In this paper, a Design-for-Testability method is proposed to detect an open defect occurring at an interconnect between dies in a 3D IC. The open defect is detected by means of a supply current flowing whenever a time-varying voltage signal is provided to the targeted interconnect as a test input stimulus. Feasibility of the test method is examined by targeted experiments and circuit simulations. It is shown that an open defect in a testable designed IC is capable of being detected by measuring the supply current of the IC.


On SAT-based Test Generation for Observing Delay Variation Caused by a Resistive Open Fault and Its Adjacent Lines

Digest of Papers of the 14-th IEEE Workshop on RTL and High Level Testing

Testing small delay fault is becoming more important in recent ICs. Especially when small delay caused by a resistive open, a delay size is affected by the signal transition of the adjacent lines. In this paper, we present a procedure for detecting delay faults by the difference of the path delay between test pattern pair. To increase the difference of the path delay, the test pattern pair assign the signal transition to as many adjacent lines as possible. To determine the set of adjacent lines, we utilize the SAT-based method. Experimental results for some benchmarks are shown to our proposed method.


Supply Current Test Method for Pin Open Defects in Assembled PCB Circuits

In this paper, we propose a test method for detecting pin opens of CMOS logic ICs in assembled PCBs. The test method is based on supply current of a circuit under test which flows when a time-varying signal is provided to a targeted pin with a test probe as a stimulus. We show by some experiments that pin opens of BGA ICs can be detected by the supply current test method.


Feasibility of Interconnect Tests of Open Defects in a 3D IC with a Built-in Supply Current Test Circuit

We have proposed a supply current test method and a built-in test circuit to detect open defects occurring at interconnects between dies in a 3D IC. In the test circuit, IEEE 1149.1 test architecture is used to provide a test vector to a targeted interconnect. In this paper, it is examined whether open defects can be detected by some experiments for a printed circuit board made of a prototype IC in which the built-in test circuit is implemented. The experimental results show us that resistive open defects of greater than 1kΩ and capacitive ones of smaller than 1nF can be detected at a test speed of 1MHz.


Diagnosing Resistive Open Faults Using Small Delay Fault Simulation

Modern high performance, high density integrated circuits use a very large number of metal layers, necessitating the need to deal with the problem of resistive open defects. Resistive opens often manifest as and are modeled as small delay faults. Furthermore, in deep sub-micron technologies, it is known that the additional delay of a line with resistive open fault is not only a function of the resistant of the faulty line but it is also dependent on the signal transition(s) on its adjacent lines. In this paper, we propose an efficient simulation method to simulate small delay faults and we use this simulator to diagnose resistive open faults. The fault simulator developed by us simulates all delay faults for one signal line simultaneously. This information is then used to deduce the candidate faulty lines in two steps. Experimental results for ISCAS'89 benchmark circuits show that by using the method proposed by us the faulty lines can be identified correctly in most cases.


Testable Design for Electrical Testing of Open Defects at Interconnects in 3D ICs

A testable design method for electrical testing is proposed in this paper to detect open defects occurring at interconnects between dies in a 3D IC and locate the defective interconnects. An IEEE 1149.1 test circuit is utilized to provide a test input vector to a targeted interconnect in the electrical tests. Feasibility of the electrical tests is evaluated by Spice simulation and some experiments with a prototyping IC. It is shown by the experiments that an open defect can be detected at a test speed of 1MHz.


Reduction Method of Number of Electromagnetic Simulation Times for Estimating Output Voltage at Hard Open TSV in 3D IC

Proc. of IEEE CPMT Symposium Japan(ICSJ2013)

An estimation method of quiescent output voltage of a defective TSV is proposed at which a hard open defect occurs in a 3D IC. The method enables us to reduce the number of times of 3D electromagnetic simulation.


Built-in IDDT Appearance Time Sensor for Detecting Open Faults in 3D IC

A built-in sensor is proposed for detecting open faults in a 3D IC by means of appearance time of dynamic supply current. It is shown by Spice simulation that they can be detected with the sensor.


Time-to-Digital Converter Embedded in Boundary-Scan Circuit and Its Application to 3D iC Testing

In this study, we propose a test method that utilizes a time-to-digital converter (TDC) embedded in boundary-scan design to estimate the excessive delay occurs at interconnects in 3D-IC. The boundary scan cells are used as an the input generation block in the lower die and as a delay detection block in the upper die. The other testing method is also proposed to utilize the effect of adjacent TSVs to enhance the fault effects.


Testability of Open Defects at Interconnections in 3D ICs with a Built-in Test Circuit for Supply Current Testing

We proposed a supply current test method and the DFT one for detecting open defects between dies in 3D ICs[1]. The test method utilizes an IEEE 1149.1 test mechanism to provide test vectors to interconnects between dies. We present feasibility analysis results of the tests obtained by some experiments in a PCB circuit made of our testable designed IC.


Open Defect Detection in Assembled PCBs by Supply Current Testing with Electrodes Embedded inside ICs


Electrical Test Method of Open Defects at Bi-directional Interconnects in 3D ICs


Size Reduction of a Built-in Test Circuit for Locating Open Interconnects in 3D ICs

Proc. of International Conference on Electronics, Information and Communication

In this paper, a built-in test circuit with a test selector is proposed to detect open defects at interconnects between dies in a 3D IC. The test selector is used to select which interconnects will be tested. An inverter gate is used as open sensors for detecting open defects. An AC voltage signal is provided to targeted interconnects and open sensors. Feasibility of tests is examined by Spice simulation. The simulation results show that targeted interconnects can be selected and also open defect can be detected.


A Built-in Electrical Test Circuit for Interconnect tests in Assembled PCBs

In this paper, a built-in electrical test circuit is proposed to detect an open defect at an interconnect between a land in a printed circuit board and an IC. An inverter gate is used as an open sensor in the test circuit. An AC voltage signal is provided to a targeted interconnect and the sensor as a test input signal to detect the defect. The defect is detected by means of supply current of the sensor. We examine by Spice simulation whether open defects can be detected with the test circuit. The results reveal us that an open defect can be detected at a test speed of 1 MHz for each interconnect.


On Detectability Analysis of Open Faults Using SAT-based Test Pattern Generation Considering Adjacent Lines

Digest of Papers of the 13-th IEEE Workshop on RTL and High Level Testing

The floating line caused by an open fault is difficult to test since its voltage is unpredicted and depends on the voltage at the adjacent lines. The fault effect can be easily detected if a test pattern provides the opposite logic value to most of the adjacent lines. We define detection probability for test pattern to estimate how much preferable logic values the test pattern assigns to adjacent lines. This paper proposes a procedure for testing open faults with high detection probability. Experimental results for some benchmarks are also shown to prove the effectiveness of our procedure.


Output Voltage Estimation Method of Hard Open TSV in 3D ICs

In this paper, we propose a method to estimate output voltage of a defective TSV at which a hard open defect occurs in a 3D IC. The voltage is estimated by an approximate function that is extracted from 3D magnetic simulation results of a targeted layout. The estimation precision is evaluated for a layout made of 10 TSVs inserted a hard open defect. The result shows us that output voltage of a defective TSV in the layout can be estimated within an error rate of 4.1%.


Electrical Interconnect Testing of Open Defects in Assembled PCBs Utilizing IEEE 1149.1 Test Mechanism

We propose an electrical test method for detecting open defects between ICs and PCBs. The test method utilizes IEEE 1149.1 test mechanism to provide test vectors to each interconnect between an IC and a PCB. The test method requests us to modify ESD input protection circuits. However, hard open defects and resistive ones can be detected by the test method. Feasibility of the testing is examined by some experiments. The results show us that hard open defects and resistive ones of larger than 100Ω will be detected in a test speed of 20MHz and also defective interconnects will be located by the test method.


A Built-in Test Circuit for Supply Current Testing of Open Defects at Interconnects in 3D ICs

Proc. of 4-th Electronics System Integration Technologies Conference(ESTC 2012)

In this paper, a built-in test circuit is proposed to detect and locate open defects occurring at interconnects between dies in a 3D IC by means of the quiescent supply current. In the test circuit, IEEE 1149.1 test architecture is used to provide a test vector to a targeted interconnect. Testability of the testing with the test circuit is evaluated by Spice simulation. The simulation results show us that a hard open defect and a soft open one generating additional delay of 0.58nsec can be detected at a test speed of 100MHz.


Test Generation for Resistive Open Faults with Considering Adjacent Lines

Proc. of 2012 International Technical Conference on Circuits/Systems, Computers and Communications

We propose an extended delay fault model where the size of the delay fault is affected by the signal transitions at the adjacent lines. We also propose a method for generating the test patterns for the resistive open faults under the launch-off-capture (LOC) test. From the experimental results, we demonstrated that the proposed method can generate the test patterns for resistive open faults that cannot be detected by the given test patterns for the transition faults.


A Built-in Sensor for IDDT Testing of CMOS ICs

In this paper, a built-in sensor is proposed for detecting open defects on signal lines in CMOS logic circuits by IDDT testing. The test method is based on the appearance time of dynamic supply current that flows when a test input vector is provided to a circuit under test. Feasibility of tests with the sensor is examined by Spice simulation. The results show that open defects on signal lines in CMOS logic circuits can be detected with the sensor.


Testable Design of CMOS Image Pixel Circuits for Electrical Testing

We propose a CMOS image pixel circuit that is designed so as to be tested by an electrical test method. The pixel circuit can be tested without a light source and test time reduction may be realized. We designed a CMOS image sensor module made of the pixel circuit and examined the testability by Spice simulation. The results show that 69% of our inserted open and short defects can be detected by our electrical test method.


An Electrical Test Circuit for Detecting Interconnect Open Defects in 3D ICs


Output Voltage of a Floating Metal Line Caused by a Neighboring Metal Line Bending at a Right Angle

Proc. RISP International Workshop on Nonlinear Circuit and Signal Processing

We analyzed faulty effects caused by a hard open defect at a metal line inside an IC with a 3D electromagnetic simulator. In our targeted layout, a metal line that runs in parallel to the defective one bends at a right angle. Also, we examined whether the faulty effects can be estimated from simulation results of a layout made of straight metal lines running in parallel. The result reveals us that since large fringing effect is caused by the bending metal line, faulty effects at an opened metal line in a layout should be estimate from simulation results of the layout.


The Test Vector Compaction Considering Compatible Flip-Flops for BIST-Aided Scan Test

In this paper, we propose the modified test vector compaction procedure for BIST-Aided Scan Test(BAST). In our method, test compaction is applied for test vectors even if a few bits in compatible flip-flops have conflicts to reduce the number of test vectors. We also show the effectiveness of our method by the experimental results for ISCAS 89 and ITC99 benchmark circuits.


On Measuring Timing Slack Using Boundary Scan with Time-to-Digital Converter for Detecting Delay Faults

This paper presents a new boundary scan architecture with time-to-digital converter(TDC) for detecting delay faults by measuring timing slack. In our boundary scan cells, flip-flops are utilized for both making a scan path and capturing circuit response. The architecture of the boundary scan design is proposed to detect delay from the other cores and chips or their interconnects. In this paper, we presents the boundary scan circuit modified from [15] for observing timing slack to reduce test application time. The proposed basic operation of the design is evaluated by simulation.


Supply Current Testing of Open Defects at Interconnects in 3D ICs with IEEE 1149.1 Architecture

International 3D System Integration Conference

In this paper, a supply current test method of 3D ICs is proposed to detect open defects occurring at interconnects between two dies in which IEEE 1149.1 architecture is implemented and locate the defective interconnects. Also, a testable design method is proposed for the test method and a testable designed IC is prototyped. Furthermore, testability of the test method is evaluated by some experiments with the prototyped IC and by Spice simulation. The simulation results show that an open defect can be detected within 10nsec which generates only additional delay of 0.7nsec.


A Built-in Test Circuit for Open Defects at Interconnects between Dies in 3D ICs

In this paper, a built-in test circuit is proposed to detect open defects that occur at interconnects between dies inside 3D ICs. An inverter gate is used in the test circuit as an open sensor. Open defects are detected by means of supply current of the inverter gate flowing when an AC voltage signal is provided to targeted interconnects as a stimulus. The interconnect at which an open defect occurs can be located with the test circuit. Feasibility of tests with the test circuit is examined by circuit simulation. The results promise us that open defects can be detected and also defective interconnects can be located with the test circuit.


A Boundary Scan Circuit with Time-to-Digital Converter for Delay Testing

This paper presents a design-for-testability method for detecting delay faults. In order to observe the effect of small delay defects, we present modified boundary scan cells in which a time-to-digital converter (TDC) is embedded. In our boundary scan cells, flip-flops are utilized for both making a scan path and capturing circuit response. The architecture of the boundary scan design is proposed to detect delay from the other cores or chips or its interconnects. The basic operation of the design is evaluated by simulation and by experimental ICs. Experimental results show that the measurement of the transition delay can be achieved by the boundary scan design with the time-to-digital converter.


A Supply Current Testable Register String DAC of Decoder Type

Proc. of 11th International Symposium on Communications and Information Technologies

In this paper, we propose a supply current testable resistor string DAC of decoder type whose area overhead is small and a supply current test method. Open defects and short ones in the DAC can be detected by the test method with about 50% of the exhausted test vectors. It is shown by some experiments that most of the targeted defects in our testable DACs of 4 and 8 bits can be detected by the test method.


Feasibility of Operating Point Estimation in Lighting Circuit with Measured I-V Characteristics of LEDs

Proc. of 2011 International Technical Conference on Circuits/Systems, Computers and Communications

We proposed a numerical analysis method for estimating an operating point of an LED lighting circuit that is based on measured DC characteristics of LEDs used in it. In this paper, we examine feasibility of the estimation of operating points of LED lighting circuits. The results show us that this analysis method can be used for designing LED lighting circuits.


Practical Testability of Supply Current Testable DACs of Resistor Type

We proposed supply current testable DACs of resistor string type. In order to examine practical testability of the DACs, we examine testability of 3 bits and 8 bits DACs by TR analysis of a circuit simulator. The results show us that all of defects in MOSs can not be detected by our test method but the test method can be used in the first stage of production tests of DACs owing to the short test time.


Feasibility of Electrical Testing for Lead Opens of QFP ICs

In this paper, an electrical test method is proposed to detect open leads of CMOS QFP ICs. When a circuit is tested, current is made to flow through one of targeted leads. An open defect is detected by means of the difference between the current of a defect-free circuit and the measured one. Feasibility of tests with the test method is examined by some experiments. It is shown that an open lead in a CMOS QFP IC can be detected by the test method at a speed of 1MHz.


Faulty Effect of Soft Open Defect in TSV Caused by Logic Values of Neighboring TSVs

In this paper, faulty effect of a soft open defect in Through Silicon Via(TSV) that is caused by logic values of the neighboring TSVs is examined with a 3 dimensional electromagnetic simulator. The results show us that propagation delay depends on the size of an open defect and the logic signals of the neighboring TSVs. Also, when a soft open defect caused by a void occurs in a TSV, logical errors can be generated.


Estimation of Faulty Effects Caused by a Clack at an Interconnect Line in 90nm ICs


Fault Analysis of Soft Open Defects in TSVs with Electromagnetic Simulator


A Supply Current Testable DAC of Resistor String Type

Proc. RISP International Workshop on Nonlinear Circuit and Signal Processing


Test Data Reduction for BIST-aided Scan Test Using Compatible Flip-flops and Shifting Inverter Code

In this paper, a method for reducing test data volume of BIST-aided scan test (BAST) is proposed. In our BAST method, scan chains are ordered using compatible flip-flops to reduce the conflicting bits between ATPG pattern and random pattern obtained by LFSR. The inverter block in BIST-aided scan architecture is modified for shifting inverter code such that the random pattern produced by LFSR has less conflicting bits with ATPG patterns when providing the test pattern to the scan chains. The experimental results show the method can reduce the test data volume than the previous method.


A Method for Diagnosing Resistive Open Faults with Considering Adjacent Lines

Proc. of 10th International Symposium on Communications and Information Technologies

It is believed that resistive open faults can cause small delay defects at wires, contacts, and/or vias of a circuit. However, it remains to be elucidated whether any methods could diagnose resistive open faults. We propose a method for diagnosing resistive open faults by using a diagnostic delay fault simulation with the minimum detectable delay fault size. We also introduce a fault excitation function for the resistive open fault to improve the accuracy of the diagnostic result. The fault excitation function for the resistive open fault can determine a size of an additional delay at a faulty line with considering the effect of the adjacent lines. We demonstrated that the proposed method is capable of identifying fault locations for the resistive open fault with a small computation cost.


Output Voltage Estimation of a Floating Interconnect Line Caused by a Hard Open in 90nm ICs

Faulty effects caused by a hard open defect at an interconnect line in a 90nm CMOS IC are analyzed by device simulation in this paper. The simulation results reveal us that output voltage of the floating interconnect line is obtained as linear sum of effects from logic signals of the adjacent interconnect lines and the defective one. Also, an estimation model of voltage at the floating interconnect line is proposed. Feasibility of the estimation is examined in this paper. The result shows us that the voltage can be estimated within error of about 0.03V.


Lighting Circuit Analysis Method with Measured I-V Characteristics of LEDs

Proc. of 2010 International Technical Conference on Circuits/Systems, Computers and Communications


Possibility of Logical Error Caused by Open Defects in TSVs


Current-Based Testable Design of Level Shifters in Liquid Crystal Display Drivers

Proc. of 2010 15th European Test Symposium

We propose a testable design method of level shifters inside a liquid crystal display driver IC. The design method enables us to detect open defects in level shifters by supply current testing that are difficult to be tested by voltage testing. Also, we show by circuit simulation that more resistive open defects may be detected by supply current testing than voltage testing, if the level shifter is designed by using the proposed DFT method.


Built-in Test Circuit for Opens at Interconnects between Dies inside SiPs


Faulty Effects on Logic Signal of a Hard Open Via from Adjacent Ones


Test Generation for Open Faults Considering the Effects of Adjacent Lines

10th IEEE Workshop on RTL and High Level Testing (WRTLT09)

Open faults are difficult to test since the voltage at the floating line is unpredicted and depends on the voltage at the adjacent lines. This paper presents a procedure to generate test pattern for open faults considering the effects of adjacent lines. The experimental results for the benchmark circuits are shown.


New Class of Tests for Open Faults with Considering Adjacent Lines

Under the open fault model with considering the effects of adjacent lines, the open fault excitation is depended on the tests. Therefore, the layout information is needed to generate a test for an open fault. However, it is not easy to extract accurate circuit parameters of a deep sub-micron LSI. We have already proposed an open fault model without using the accurate circuit parameters. In this paper, we propose a new class of the pair of tests for the open fault called Ordered Pair of Tests (OPT). OPT is generated based on the fault excitation function as a threshold function of the adjacent lines. Also we propose a method for generating OPTs from the given stuck-at fault test set. The proposed method generates OPTs using only information about adjacent lines of the target open fault. Experimental results show that the proposed method can generate the OPTs for the open faults with high fault coverage.


Feasibility of IDDQ Tests for Shorts in Deep Submicron ICs

Proc. of 2009 International Technical Conference on Circuits/Systems, Computers and Communications

Quiescent supply current (IDDQ) in deep submicron ICs is derived by circuit simulation and feasibility of IDDQ tests is examined for short defects in ICs fabricated with 0.18 um CMOS process. The results show that IDDQ of each gate depends on input logic values and that shorts can be detected by IDDQ testing if some process variation are small.


Preliminary Analysis of Interconnect Full Open Faults using TEG chips

As LSIs are scale-down, there is an increasing need to take measures against open faults. However, no practical model for open faults exists at present. Therefore, we fabricated Test Element Group (TEG) chips that intentionally incorporated full (complete) open defects and electrically measured the output signals relevant to its defective lines in order to create a new model for open fault behavior. This study reveals the effect boundary of adjacent signal lines on the line containing the full open defect for the first time using the TEG chips.


Current Testable Design of Resistor String DACs for Short Defects

In this paper, we propose a DFT method for resistor string DACs that enables us to test them easily by supply current test method. The targeted defects are shorts in the DACs. It is shown by some experiments that all of the targeted defects in a DAC designed with the DFT method can be detected with a smaller number of test vectors.


Open Lead Detection of QFP ICs Using Logic Gates as Open Sensors

Proc. of 2009 International Conference on Electronics Packaging


Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC

Proc. of 22nd International Conference on VLSI Design

Open faults are difficult to test since the voltage at the floating line is unpredicted and depends on the voltage at the adjacent lines. The modeling for open faults with considering adjacent lines has been proposed. In this work, the 90 nm IC is designed and fabricated to evaluate how the voltage at adjacent lines affect the defective line. The open fault macros with a transmission gate and with an intentional break are included in the IC. The nine lines are placed in parallel in three layers to observe the effect of the coupling capacitance when an open occurs. The benchmark circuits with the open fault macro are also included in the IC. The simulation and experimental results show that the relationship between the floating line and the adjacent lines. The experimental results are also compared with the open fault model that calculate the weighted sum of voltages at the adjacent lines.


A Novel Approach for Improving the Quality of Open Fault Diagnosis

With the shrinking process technologies and the use of copper process, open defects on interconnect wires, contacts and vias often cause failure. Development of an efficient fault diagnosis method for open faults is desired. However, the diagnosis method for open faults has not been established yet. In this paper, we propose a novel approach for improving the diagnostic quality of open faults by introducing a threshold function in which the logical value of the line with open defect depends on the weighted logical values of its adjacent lines. By using the threshold function, we can deduce not only a faulty line but also an open defect site at the faulty line. Experimental results show that the proposed method can identify an exact faulty line in most cases with a very small computation cost. The proposed method can also identify the open defect site within 25%-length of the faulty line.


Scan Chain Configuration for BIST-aided Scan Test using Compatible Scan Flip-flops

9th Workshop on RTL and High Level Testing (WRTLT08)

In this paper, the scan chain configuration for BIST-aided scan test for reducing test data and test application time is proposed. The scan flip-flops are arranged based on compatible set of flip-flops to attain less conflicts between the random pattern generated by LFSR and ATPG test pattern. The experimental results for some benchmark circuits are shown.


Test Circuit for Locating Open Leads of QFP ICs

IEEE 7-th International Board Test Workshop

In this paper, a test circuit is proposed, with which open leads of CMOS QFP ICs are located without generating test input vectors. Open leads are located by means of supply current of the test circuit that flows when an AC voltage signal is provided to targeted leads with test probes as a stimulus. Also, a design method of the test circuit is proposed. It is examined by circuit simulation whether the test circuit will be designed by the design method. The result shows that an open lead in CMOS QFP ICs of 50 leads will be located with the test circuit.


Current Testble Design of Resistor String DACs for Open Defects

Proc. of 2008 International Technical Conference on Circuits/Systems, Computers and Communications

In this paper, a DFT method of resistor string digital-to-analog converters (DACs) is proposed so as to be tested fully by supply current testing. Targeted defects are opens in the DACs. Testability of opens in testable designed DACs is examined experimentally. The results show that all of the opens in an N-bits testable designed DAC will be detected with test vectors of about 2(N-1) by supply current testing.


Open Lead Detection Based on Logical Change Caused by AC Voltage Signal Stimulus

In this paper, we propose a new test method for detecting an open lead which occurs when an IC is mounted on a printed circuit board. In the method, an open lead is detected by observing output logical change of an open lead detector. Since the test method is a vectorless test one, test generation and test input application are not needed. Testability of the test method is examined by some experiments. The results show that open leads of SSIs and LSIs will be detected by the method.


Fault Analysis of Interconnect Opens in 90nm ICs with Device Simulator

In this paper, faulty effects of interconnect opens in logic ICs fabricated with a 90nm CMOS process are analyzed by device simulation. In the analysis, it is examined whether a logical error can be caused at an opened input signal line by logic signals of the neighboring signal lines. The simulation results suggest us that a logical error may occur at an interconnect surrounding by 8 interconnects if the interconnects are longer than 5μm and the width of an open defect is greater than 2.0nm.


Test Method for DetectingOpen Leads of Low Voltage LSIs


Test Circuit for Vectorless Open Lead Detection of CMOS ICs

IEEE 6-th International Board Test Workshop

In this paper, a test circuit for a test method is proposed, with which open leads of CMOS logic ICs are detected without generating test input vectors. Open leads are detected by means of supply current of the test circuit that flows when an AC voltage signal is provided to targeted leads with test probes as a stimulus. It is examined by some experiments whether open leads will be detected with the test circuit. The empirical results show that open leads of CMOS ICs will be detected within 5μsec after attachment of test probes to targeted leads.


Interconnect Open Detection by Supply Current Testing under AC Electric Field Application

IEEE International Workshop on Current and Defect Based Testing

In this paper, it is examined by some experiments whether interconnect opens are detected by a supply current test method. The test method is based on supply current of a targeted IC that flows when AC electric field is provided outside of the IC. ICs fabricated with 0.35um CMOS process, into which open defects are inserted, are used in the experiments. The experimental results show that interconnect opens are detected by the test method except for opened interconnect lines coupled strongly with the neighboring ones. Also, it is shown that by embedding an electrode, which is used to generate AC electric field, inside a targeted IC, interconnect opens will be detected with smaller AC voltage supplied to the electrode.


On SoC Testing Using Multiple Scan Chains with Scan Tree Configurations

8th Workshop on RTL and High Level Testing (WRTLT07)

In this paper, we propose a method to configure multiple scan chains for SoC testing. The method utilizes two scan tree modes for each core: fully compatible mode and folding mode. Experimental results are obtained for the case that three ISCAS 89 and ITC99 benchmark circuits are assumed as the cores. Test application time required for providing the test pattern can be reduced with the method.


Current Testable Design of Resistor String DACs

In this paper, a DFT method of resistor string digital-to-analog converters (DACs) is proposed so as to be tested fully by supply current testing. Targeted defects are opens and shorts in the DACs. Testability of a testable designed DAC is examined experimentally. The results show that shorts and opens in a testable designed DAC will be detected with a smaller number of test vectors by supply current testing.


Clues for Modeling and Diagnosing Open Faults with Considering Adjacent Lines

Under the modern manufacturing technologies, the open defect is one of the significant issues to maintain the reliability of DSM circuits. However, the modeling and techniques for test and diagnosis for open faults have not been established yet. In this paper, we give an important clue for modeling an open fault with considering the affects of adjacent lines. Firstly, we use computer simulations to analyze the defective behaviors of a line with the open defect. From the simulation results, we propose a new open fault model that is excited depending on the logic values at the adjacent lines assigned by a test. Next, we propose a diagnosis method that uses the pass/fail information to deduce the candidate open fault. Finally, experimental results show that the proposed method is able to diagnose the open faults with good resolution. It takes about 6 minutes to diagnose the open fault on the large circuit (2M gates).


Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines

IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems

In order to ensure high quality of DSM circuits, testing for the open defect in the circuits is necessary. However, the modeling and techniques for test generation for open faults have not been established yet. In this paper, we propose a method for generating tests and diagnostic tests based on a new open fault model. Firstly, we show a new open fault model with considering adjacent lines [9]. Under the open fault model, we reveal more about the conditions to excite the open fault. Next we propose a method for generating tests for open faults by using a stuck-at fault test with don't cares. We also propose a method for generating a diagnostic test that can distinguish the pair of open faults. Finally, experimental results show that (1) the proposed method is able to achieve 100% fault coverages for almost all benchmark circuits and (2) the proposed method is able to reduce the number of indistinguished open fault pairs.


Open Lead Detection of CMOS Logic Circuits by Low Pressure Probing


At Speed Testing of Bus Interconnects in Microcomputers

7th Workshop on RTL and High Level Testing (WRTLT06)


Test Time Reduction for Scan Circuits by Selection of a Flip-flop with Hold Operation

This paper presents a test time reduction method for scan circuits. The method finds the last consecutive 0's and 1's in test vectors for a scan chain. To reduce the scan shifts one of the flip-flops in a scan chain is selected to hold the value to provide the last flip-flops on the chain.


A BIC Sensor Capable of Adjusting IDDQ Limit in Tests

A built-in-current sensor (BIC sensor) is proposed whose IDDQ limit is able to be adjusted in each IC test. IDDQ tests of identical IDDQ limit can be realized with the current sensor, even if process variation occurs in the sensor. Also, an IDDQ test method is proposed for ICs, in each of which the BIC sensor is implemented. It is shown by some experiments that IDDQ limit of 10mu A will be able to be set and IDDQ test results based on the limit will be obtained by adjusting the limit for each IC if size variation of MOSs in the BIC sensor is less than 50%


Current Testing of Interconnect Opens between CMOS LSIs Having Scan Cells

IEEE International Workshop on Current and Defect Based Testing


Test Circuit for Open Lead Detection of CMOS ICs Based on Supply Current

In this paper, a test circuit is proposed for detecting open leads of CMOS logic ICs by means of supply current of a circuit under test. The circuit consists of a supply current measurement circuit and a test stimulus generator. The test stimulus generator is designed so that high speed test can be realized. Also, it is shown by some experiments that open leads of CMOS ICs will be detected at test speed of 1MHz with the test circuit.


Open Lead Detection Based on Supply Current of CMOS Logic Circuits by AC Voltage Signal Application


Test Time Reduction Method for Scan Design with Clock-Control DFT

Proc. RISP International Workshop on Nonlinear Circuit and Signal Processing

This paper presents a test generation method for sequential circuits. Our method utilizes the test vectors obtained for full scan design. In this parer, we combined two design-for- testability(DFT) method:one is transparent scan, the other is clock-control DFT. The simulation results for some benchmark circuits are shown.


Current Testable Design of Resistor String DACs

The IEEE International Workshop on Electronic Design, Test and Applications

In this paper, supply current testability is examined experimentally for opens and shorts in a general 3 bit resistor string digital/analog converter (DAC). The results show that all of the shorts and the opens are detected by supply current testing, while opens of the MOS switches are not detected. A DFT method for resistor string DACs is proposed in this paper to detect the opens by supply current testing. Also, testability of a resistor string DAC designed with the DFT method is examined. It is shown that all of the targeted shorts and opens in the testable designed DAC are detected by supply current testing.


Test Generation for Scan Circuits Using Random Selection of the Operations of Scan Flip-flops

6th Workshop on RTL and High Level Testing (WRTLT05)

This paper presents a test generation method for scan circuits. In the proposed method control signals of scan flip-flops are treated as the same as the primary inputs. Our method utilizes the test vectors obtained for full scan design and apply the vectors repeatedly in the given order to achieve low test data volume. For each test vector, the operation of scan flip-flops is selected from one of the following: normal, scan and freeze operation. The simulation results for some benchmark circuits are shown.


Electric Field for Detecting Open Leads in CMOS Logic Circuits by Supply Current Testing

Proc. of IEEE International Symposium on Circuits and Systems

Open leads are one type of defect occurring frequently when logic circuits are implemented on printed circuit boards (PCBs) with ICs. A powerful supply current test method has been proposed for detecting an open lead in a CMOS logic circuit. The method is based on the supply current of a circuit under test which flows when a time-varying electric field is supplied from the outside of the circuit. The paper proposes a time-varying electric field which enables us to detect open leads in a CMOS logic circuit with an inexpensive test setup.


Vectorless Open Pin Detection Method for CMOS Logic Circuits

Proc. of International Conference on Electronics Packaging


Fail-Safe Evaluation Method for Boiler Control Circuits by Circuit Simulation

The fail-safe property is strongly requested for boiler control circuits. A boiler control circuit is a microprocessor based circuit and the operation is specified by a control program. Until now, there have been no methods to evaluate fail-safe property of boiler control circuits. In this paper, a fail safe evaluation method is proposed for boiler control circuits. The method utilizes a circuit simulator to check it. It is checked by the method whether it is stopped supplying fuel to a boiler when a fault occurs inside the boiler control circuit in operation. In order to evaluate the feasibility of fail-safe evaluation by the method, fail-safe property in a general boiler control circuit is examined by using the method. The result shows that fail-safe property will be checked by using the evaluation method.


Electrical Detection of Pin Shorts by Supply Current of PIC

In this paper, we propose a new test method for detecting pin shorts of a PIC. This test method is based on supply current of the PIC. Targeted faults of this test method are input/output pins of the PIC. The property is used for detecting the shorts in the test method that input/output mode of each of the pins is programmable. Each of the fault is excited by executing a test program so that supply current change can appear. We checked the feasibility of the test method by some experiments. The results shows that the shorts will be detected by the test method.


Test Equipment for CMOS Lead Open Detection Based on Supply Current under AC Electric Field Application

Open leads have often occurred in logic circuits implemented on printed circuit boards with the state-of-art technology. We proposed an electrical test method to detect them with high fault coverage. The test method is based on supply current change of a circuit under test that is caused with AC electric field supplied from the outside of the circuit. In this paper, we propose a test equipment for the test method. A voltage signal that is obtained by mixing a rectangle waveform signal and a sine waveform one is supplied between electrodes to generate the electric field. Amplitude of the signal continues to increase in proportion to time during a specified time. When supply current change that is larger than a threshold value appears, it stops increasing the amplitude and it is concluded that open leads occur in the circuit. If the supply current change does not appear within the specified time, it is concluded that no open leads occur in the circuit. In this paper, it is shown experimentally that an open lead at a CPLD of PLCC package is detected with the test equipment.


IDDQ Test Method Based on Wavelet Transformation for Noisy Current Measurement Environment

An IDDQ test method is proposed in this paper, which is applicable even if supply current measurement is impaired by noise. Wavelet transformation is used for noise elimination in the test method. In this paper, it is shown by some experiments that bridging faults will be detected by using the proposed test method. Since expert knowledge on filter design is not needed in noise elimination of the IDDQ test method, it is expected that the test method will be used in many IDDQ tests.


Test Circuit for CMOS Lead Open Detection by Supply Current Testing under AC Electric Field Application

Proc. of the 2004 47-th Midwest Symposium on Circuits and Systems

A test circuit is proposed for detecting lead opens of CMOS ICs by measuring the supply current of a CMOS circuit made of the ICs which flows when AC electric field is applied from the outside. A signal of a sine waveform is provided to the test circuit. In the test circuit, the amplitude of the signal increases in proportion to time during a prespecified time. The amplified signal is provided to electrodes for AC electric field to be supplied to a circuit under test. When supply current change which is larger than a threshold value appears, it stops increasing the amplitude and the test circuit concludes that a lead open occurs in the circuit. If the elevated supply current change does not appear within the specified time, the test circuit concludes that the circuit is fault-free. It is shown by our experiments that lead opens in a CMOS IC is detected with the test circuit.


AC Electric Field for Detecting Pin Opens by Supply Current of CMOS ICs

International Microelectronics and Packaging Society Japan


A Power Supply Circuit Recycling Charge in Adiabatic Dynamic CMOS Logic Circuits

Proc. of the second IEEE International Workshop on Electronic Design, Test, and Applications

In this paper, a power supply circuit is proposed for adiabatic dynamic CMOS logic circuit. Charge in load capacitors of gates can be recycled by using this power supply circuit. It leads to lower power consumption than without recycling. In this paper, source voltage of adiabatic dynamic CMOS inverter chain circuits is supplied with the circuit to evaluate the usefulness of the circuit. The results show that the circuits can work with smaller power consumption than without recycling.


On Configuring Scan Trees to Reduce Scan Shifts based on a Circuit Structure

In this paper, a new method for reducing test application time of sequential circuits with scan design is proposed. Scan design is one of most popular design for testability techniques. To reduce scan shifts required to provide the scan pattern, a fully testable scan tree configuration is proposed. The method can configure scan trees before generating test vectors without degrading fault coverage by considering a circuit structure. In a fully testable scan tree, flip-flops are placed in parallel in case that they have no overlap in the set of the outputs connected from them. To reduce much scan shifts, a folding scan tree, which is configured based on a fully testable scan tree by placing more flip-flops in parallel, is also configured. Moreover, a scan tree configuration considering scan-out operation is also presented. Experimental results for benchmark circuits are shown.


Practical Fault Coverage of Supply Current Tests for Bipolar ICs

Bipolar logic circuits are indispensable for implementing high-speed logic circuits. Since quiescent supply current flows into the circuits without faults, they can not be tested by a conventional IDDQ test method. We proposed a quiescent supply current test method which is applicable for the bipolar circuit tests, and examined the testability of open faults under an ideal assumption that there are not any process variations. Actually, there are some variations in the quiescent supply current of each gate in implemented logic circuits. Thus, It is necessary to examine the practical testability of the test method before applying to production tests of bipolar logic ICs. In this paper, the practical testability obtained under an assumption that there are some unit-to-unit variations of supply current among gates is examined for ISCAS-85 benchmark circuits. The experimental results show that larger fault coverage can be obtained with a smaller number of test input vectors by our supply current test method than the functional test one based on stuck-at fault models.


CMOS Open Fault Detection by Appearance Time of Switching Supply Current

In this paper, a new dynamic supply current test method is proposed for detecting open defects on signal lines in CMOS logic circuits. The method is based on the appearance time of dynamic supply current that flows when a test input vector is provided to a circuit under test. Also, we introduce our designed sensor circuit of the appearance time. Feasibility of tests based on the test method is examined by some experiments. The experimental results show that open defects on signal lines in CMOS logic circuits will be detected by the test method.


In this paper, an IDDQ test time reduction method is proposed which is suitable for BIST approaches. Also, a BIST circuit for IDDQ tests, based on the method, is proposed. The layout of a CMOS logic circuit having the BIST circuit is designed and the performance is evaluated by SPICE simulation. The results show us that IDDQ test time can be reduced by using this test circuit.


Reducing Scan Shifts using Folding Scan Trees

In this paper, a new method for reducing scan shifts is presented. Scan design is one of the most popular design for test technologies for sequential circuits. However, it requires much test application time and test data when applied to circuits with many flip-flops. The new scan method utilizes two configurations of scan chains, a folding scan tree and a fully compatible scan tree. A test pattern including many don't care values is used to configure a fully compatible scan tree in order to reduce the scan shift without degrading fault coverage. And then a folding scan tree is configured to reduce the length of the scan chain and thus reduce the scan shift. Experimental results for benchmark circuits shows this scan method can reduce many scan shifts.


Testability of Supply Current Test in an AGC Circuit

Proc. of 2003 International Technical Conference on Circuits/Systems, Computers and Communications

In this paper, it is examined whether AGC circuits can be tested by measuring supply current of the circuits. A general AGC circuit is designed and a fault, which is one of shorts, opens and parametric faults, is inserted to the circuit. Supply current waveforms of faulty circuits are derived by circuit simulation and compared to the one of the fault-free circuit. The experimental results show that many faults in the AGC circuit can be detected by measuring the supply current.


Testability of Pin Open in Small Outline Package ICs by Supply Current Test

Proc. of the 2003 International Technical Conference on Circuits/Systems, Computers and Communications


Electric Field Application Method Effective for Pin Open Detection Based on Supply Current in CMOS Logic Circuits

Proc. of International Conference on Electronics Packaging


Simplification of Incompletely Specified Machine Based on Genetic Algorithm Implementing Dormant Mechanism

3rd Workshop on RTL and High Level Testing (WRTLT02)


Test Time Reduction for IDDQ Testing by Arranging Test Vectors

In this paper, test time reduction for IDDQ testing is discussed. Although IDDQ testing is known to be effective in detecting faults in CMOS circuits, the test time of IDDQ testing is larger than that of logic testing. It is shown that the test time of IDDQ test mostly depends on the switching current. To reduce the test time of IDDQ testing, a procedure to arrange test vectors such that the switching current quickly disappears is proposed for combinational circuits. The procedure utilizes a unit delay model to estimate the time of the last transition of logic values from low to high in a circuit. Experimental results for benchmark circuits show the effectiveness of the procedure.


Oscillation Frequency Estimation for Detecting Feedback Bridging Faults

Proc. of 2002International Technical Conference on Circuits/Systems, Computers and Communications

When a feedback bridging fault is activated in a circuit, logical oscillation may occur at a signal line. If the oscillation appears, the fault may not be detected by logic testing. In order to detect such bridging faults, output logic values of the circuit should be measured at higher frequency than frequency of the logical oscillation. In this paper, a method for estimating the maximum frequency of logical oscillation is proposed to detect such bridging faults in a circuit by logic testing. Also, it is shown by some experiments that such bridging faults can be detected by measuring output logic values at the frequency obtained by the method.


Testability of Current Testing for Open Faults Undetected by Functional Testing in TTL Combinational Circuits

A new test approach based on a supply current test method is proposed for testing open faults in bipolar logic circuits. In the approach, only the open faults are detected by the supply current test method, which are difficult to be detected by functional test methods. The effectiveness of the approach is examined experimentally on open fault detection in TTL combinational circuits. The results shows that higher fault coverage can be established by applying a small number of test input vectors of the supply current test method after test vectors of functional test methods based on stuck-at models.


Power-off Vectorless Test Method for Pin Opens in CMOS Logic Circuits

A new test method is proposed in this paper for detecting pin opens in CMOS logic circuits fabricated on printed circuit boards, which are generated by missing solder and so on. Our test method is based on the current which flows through a protection circuit connecting to each pin by supplying a voltage source between the targeted pin and VSS line of a circuit under test. The test method does not require test input generation. When a pin open occurs, smaller current will be supplied from the voltage source than in the case of the fault-free circuit. Our test method uses the property for detecting pin opens. In this paper, the feasibility of the test method is evaluated by some experiments.


Power Supply Circuit for High Speed Operation of Adiabatic Dynamic CMOS Logic Circuits

Proc. of the IEEE International Workshop on Electronic Design, Test, and Applications

In this paper, a power supply circuit is proposed for adiabatic dynamic CMOS logic circuits proposed by K. Takahashi et. al. With this supply circuit, the circuits can work at higher speed. In this paper, source voltage of adiabatic dynamic CMOS inverter gates is supplied by the circuit and the power consumption is examined. The results show that the gates can work with smaller power dissipation than conventional static CMOS circuits


Random Pattern Testability of the Open Defect Detection Method using Application of Time-variable Electric Field

In this paper, random pattern testability of the open defect detection method is discussed. In the test method, time-variable electric field is applied from the outside of ICs so as to vary the voltage at floating nodes caused by a defect. To detect opens the excessive supply current caused by the applied electric field is measured. The test pattern requirements for detecting opens are shown. The fault coverage for open defects is calculated for benchmark circuits. The experimental results shows random pattern can be effectively utilized for the test method even if it cannot attain high fault coverage for stuck-at-faults


CMOS Open Defect Detection Based on Supply Current in Time-variable Electric Field and Supply Voltage Application

In this paper, a new test method is proposed for detecting open defects in CMOS ICs. The method is based on supply current of ICs generated by applying time-variable supply voltage and electric field from the outside of the ICs. The feasibility of the test is examined by some experiments. The empirical results show that, by using the method, open defects in CMOS ICs can be detected. Also, the test input vectors for the test method are proposed and it is shown that they can be generated more easily than functional test methods based on stuck-at fault models


IDDQ Sensing Technique for High Speed IDDQ Testing

In this paper, a useful technique is proposed for realizing high speed IDDQ tests. By using the technique, load capacitors of the CMOS logic gates can be charged quickly, where the output logic level changes L to H by applying a test input vector to a circuit under test. The technique is applied to built-in IDDQ sensor design and external IDDQ sensor design. It is shown experimentally that high speed IDDQ tests can be realized by using the technique


Sequential Redundancy Removal Using Test Generation and Multiple Unreachable States

In this paper, a procedure to reduce sequential circuits by removing undetectable faults in sequential circuits is proposed. To identify whether an undetectable fault is removable or not, strongly unreachable states, which are the states with no incoming transitions, are utilized. It is proved that part of undetectable faults related to strongly unreachable states can be removed from a circuit. Test generation method is used to find undetectable faults related to two or more strongly, unreachable states. Experimental results for ISCAS benchmark circuits are shown


Test Pattern for Supply Current Test of Open Defects by Applying Time-variable Electric Field

Proc. of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Test input vectors for a supply current test method are discussed which is used for detecting open defects in CMOS ICs. In the test method, time-variable electric field is applied from the outside of ICs so as to vary the voltage at a floating node. To generate excessive supply current by the induced voltage change at the floating node, test pattern must be provided so that a conducting path from VDD to GND can be generated in the faulty circuit. In this paper, the requirements are denoted to be satisfied as a test input vector of the test method. Also, it is shown that test pattern of functional tests based on stuck-at fault models can be used for the open defect detection method. Furthermore, the experimental results in this paper promise that high fault coverage can be achieved by applying the subset of the stuck-at test pattern to the detection of open defects


Proc. of 2001 International Technical Conference on Circuits/Systems, Computers and Communications


Fault Simulator for Test Program Generation in Supply Current Tests of Microprocessor Based Boiler Control Circuits


Pin Open Detection Method Based on Supply Current in Time-variable Magnetic Field


Supply Current Test for Pin Opens in CMOS Logic Circuits

Proc. of International Conference on Electronics Packaging


CMOS Open Defect Detection by Supply Current Test

Proc. of Design, Automation and Test in Europe Conference 2001

In this paper, a new test method is proposed for detecting open defects in CMOS ICs. The method is based on supply current of ICs generated by applying time-variable electric field from the outside of the ICs. The feasibility of the test is examined by some experiments. The empirical results promised that, by using the method, open defects in CMOS ICs can be detected by measuring supply current which flows when time-variable electric field is applied


High Speed IDDQ Test and Its Testability for Process Variation

A new high speed IDDQ test method is proposed. It is based on charge current for load capacitances of gates whose output logic values are changed from L to H by test input vector application. In this paper, the testability of the test method is examined for some process variations generated in CMOS IC production


Testability Analysis of IDDQ Testing with Large Threshold Value

IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

By using large threshold value in IDDQ tests, test time can be shortened. However, the fault coverage of the IDDQ tests will be affected by process variation. In this paper, effects on fault coverage of IDDQ tests generated by variations of zero biased threshold voltage of each MOS transistor in a circuit under test are examined with a circuit simulator. The result suggests us that IDDQ testing with large threshold value is applicable to production tests of CMOS ICs


Power Supply Circuits with Small Size for Adiabatic Dynamic CMOS Logic Circuits

Proc. of 2000 International Technical Conference on Circuits/Systems, Computers and Communications


Practical Fault Coverage of Supply Current Testing for Open Fault in TTL Combinational Circuits


A Test Input Sequence for Test Time Reduction of IDDQ Testing

It is shown that IDDQ testing is very useful for shipping fault-free CMOS ICs. However, test time of IDDQ testing is extremely larger than one of logic testing. In this paper, a new test input sequence generation methodology is proposed to reduce the test time of lDDQ testing. At first, it is shown that IDDQ test time will be denominated by charge supply current for load capacitance of gates whose output logic values are changed by test input vector application and the charge current depends on input sequence of test vectors. After that, a test input sequence generation methodology is proposed, The feasibility is checked by some experiments.


IDDQ Testable Design of Static CMOS PLAs with Low Power Consumption


Oscillation Frequency Estimation of Feedback Bridging Faults for Test Circuit Design


Synthesis for Testability by Adding Transitions of Undefined States to State Transition Tables

In this paper we propose procedures to enhance testability by modifying state transition tables. In these procedures, transitions about undefined states, which are not described in state transition tables but exist in a synthesized gate level circuit, are added to a state transition table. Experimental results for MCNC benchmarks are shown.


IDDQ Testable Design of Static CMOS PLAs

IEEE International Workshop on Defect Based Testing

A new IDDQ testable design method is proposed for static CMOS PLA circuits. A testable PLA circuit of NOR-NOR type is designed by using this method. It is shown that all bridging faults in NOR planes of the testable designed PLA circuit can be detected by IDDQ testing with 4 kinds of test input vectors. The test input vectors are independent of the logical functions to be realized in the PLA circuit. PLA circuits are designed by using this method so that quiescent supply current generated when they are tested can be zero. Thus, high resolution of IDDQ tests for the PLA circuits can be obtained by using this testable design method.


Identification of Feedback Bridging Faults with Oscillation

When a feedback bridging fault occurs in a combinational circuit and it is activated, logical oscillation may be generated in the circuit. In this paper, the necessary conditions are presented for feedback bridging faults to generate logical oscillation. Also, a method is proposed to identify such faults in feedback bridging ones. It is based on piecewise-linearized models obtained from input/output characteristics of logic gates and does not require circuit simulation of large size of circuits to identify them. In the experiments for evaluating the method, all of the feedback bridging faults to generate logical oscillation are identified by using the method


Supply Current testing for Bridging Faults in Microprocessor Based Sequence Control Circuits

Proc. of Electronic Circuits World Convention 8


Power Supply Circuit for Adiabatic Dynamic CMOS Logic Circuits

Proc. of 1999 International Technical Conference on Circuits/Systems, Computers and Communications


Undetectable Fault Removal of Sequential Circuits Based on Unreachable States

We present a procedure to reduce sequential circuits by removing undetectable faults based on unreachable states. Procedures for obtaining unreachable stares and for identifying undetectable faults which can be the target of fault removal are presented. Experimental results for ISCAS benchmark circuits are shown


Synthesis for Testability by Redundancy Removal Using Retiming

Proc. 25th International Symposium on Fault-Tolerant Computing

The existence of sequential redundancy will degrade testability of sequential circuits. By using retiming which rearranges flip-flops, some sequential redundancy are converted into combinational redundancy, which can be easily identified and removed by a combinational test generation technique. In this paper retiming is utilized for two purposes: one is for finding sequential redundancy and another is for reducing the number of flip-flops. Applying retiming and redundancy removal techniques concurrently, testability of sequential circuits will be enhanced. Experimental results for ISCAS'89 benchmark circuits show effectiveness of this method to optimize the circuits.


Resynthesis for Sequential Circuits Designed with a Specified Initial State

This paper presents a retiming and redundancy removal method for a sequential circuit with a specified initial state so that the resynthesized circuit has a state corresponding to the initial state and gives same behavior for any input sequences of the original circuit. Experimental results show the proposed method can optimize circuits as well as the method which does not consider the specified initial state


A Study on the Application of Charge Injection Test Method Using Charge Pump for Hardware Trojan Detection

チャージポンプ型電荷注入回路を用いるトロイ回路検出の検討

電子情報通信学会技術研究報告

Institute of Electronics, Information and Communication Engineers


Testing and design for testability techniques for 3D stacked ICs

3次元積層チップの実装テストとテスト容易化設計

電気学会全国大会講演論文集

The Institute of Electrical Engineers of Japan


An FPGA Implementation of design for testability circuit for detecting resistive interconnect opens

半断線故障検査容易化設計のFPGAへの実装に関する検討

第38回エレクトロニクス実装学会春季講演大会

第38回エレクトロニクス実装学会春季講演大会

Japan Institute of Electronics Packaging

社団法人 エレクトロニクス実装学会


On Reducing Area Overhead of BIST for Approximate Multiplier Considering Truncated Bits

切り捨てビットを考慮する近似乗算器用BIST回路の面積削減について

電子情報通信学会技術研究報告


Temperature Dependence on Amplitude of Invertor in Comparator of Offset Cancellation Type

オフセットキャンセル型コンパレータ内インバータゲートの増幅度の温度依存性

Shikoku-Section Joint Convention Record of the Institutes of Electrical and Related Engineers

電気・電子・情報関係学会四国支部連合大会講演論文集


On the Evaluation of Boundary Scan Design for Testing Interconnects between ICs in a Stand-by Mode

待機モード IC の配線検査可能なバウンダリスキャンの動作検証

電気・電子・情報関係学会四国支部連合大会講演論文集


アナログ素子のみで構成する弛緩発振器によるIC間抵抗断線の検出可能性調査

アナログ素子のみで構成する弛緩発振器によるIC間抵抗断線の検出可能性調査

第33回マイクロエレクトロニクスシンポジウム論文集

第33回マイクロエレクトロニクスシンポジウム論文集

社団法人 エレクトロニクス実装学会


A Study on Boundary Scan Design for Testing Interconnects between ICs in a Stand-by Mode

待機モード IC からの配線テスト可能なバウンダリスキャン設計についての検討

第37回エレクトロニクス実装学会春季講演大会

第37回エレクトロニクス実装学会春季講演大会

社団法人 エレクトロニクス実装学会


On reduction of test patterns for a Multiplier Using Approximate Computing

近似演算を用いる乗算器に対するテストパターン削減について

電子情報通信学会技術研究報告


Evaluation of testing TSVs using the delay testable circuit implemented in a 3D IC

3次元積層ICに実装した遅延検査容易化回路によるTSV検査能力評価

電子情報通信学会技術研究報告


On the Performance Evaluation of a PUF Circuit Using the Delay Testable Circuit under Temperature Effects

遅延検査容易化設計を用いる PUF 回路の周囲温度による動作性能調査

電子情報通信学会技術研究報告


On Testing Resistive Open at Interconnections between an IC with Boundary-scan with Embedded TDC and a Non-JTAG Device

TDCBS 内蔵 IC と非 JTAG デバイス間の半断線故障検査法について

電気・電子・情報関係学会四国支部連合大会講演論文集


Combination of Test Pattern for Discrimination of a Resistive Open and Delay Fault

半断線故障と遅延故障検出用テストパターンの組合せについて

電気・電子・情報関係学会四国支部連合大会講演論文集


On Input Dependency of Open Fault Detection Method Using a Charge Pump

チャージポンプを用いた断線検出法に対する検査入力が与える影響調査

電気・電子・情報関係学会四国支部連合大会講演論文集


On a circuit to identify scan segments to be observed for optimizing scan operation of boundary scan with embedded TDC

TDC組込み型バウンダリスキャンの遅延信号観測対象判別回路の設計

第36回エレクトロニクス実装学会春季講演大会

第36回エレクトロニクス実装学会春季講演大会

社団法人 エレクトロニクス実装学会


Applicability Evaluation of the Delay Testable Circuit to PUF

遅延検査容易化回路のPUFへの適用可能性評価

電子情報通信学会技術研究報告

Institute of Electronics, Information and Communication Engineers


Delay Fault Test Pattern Generation of Fault Tolerant Design Using Approximate Computing

近似演算回路を用いた耐故障設計における遅延故障用テストパターン生成について

電子情報通信学会技術研究報告


A study on the application of a testable design of pixel circuits in interconnect testing of stacked CMOS image sensor

積層型 CMOS イメージセンサの接続検査における検査容易化画素回路の適用について

電子情報通信学会技術研究報告


On testing interconnects of stacked chips in a stacked CMOS image sensor using voltage-to-delay cells

電圧-遅延セルを用いる積層型イメージセンサ回路の接続検査について

電気・電子・情報関係学会四国支部連合大会講演論文集

電気・電子・情報関係学会四国支部連合大会講演論文集


A study on application of a delay test architecture to Physically Unclonable Function (PUF)

遅延検査容易化設計のPUFへの適用に関する検討

電気・電子・情報関係学会四国支部連合大会講演論文集

電気・電子・情報関係学会四国支部連合大会講演論文集


On Test Time Reduction by Selecting Cells for Observing Delay Using Boundary Scan with Embedded TDC

TDC組込み型バウンダリスキャンの観測セル部分選択による検査時間削減について

第35回エレクトロニクス実装学会春季講演大会

第35回エレクトロニクス実装学会春季講演大会

Japan Institute of Electronics Packaging

社団法人 エレクトロニクス実装学会


A Study on Test Clock Control Circuit for the Design-for-Testability Circuit to Detect Small Delay Faults

微小遅延故障検査容易化設計用テストクロック制御回路の検討

第35回エレクトロニクス実装学会春季講演大会

第35回エレクトロニクス実装学会春季講演大会

社団法人 エレクトロニクス実装学会


A Clock Control Circuit in Design-for-Testability Method for Delay Fault in 3D IC

3D IC における遅延故障検査容易化設計用のクロック制御回路について

電気・電子・情報関係学会四国支部連合大会講演論文集

電気・電子・情報関係学会四国支部連合大会講演論文集


A target path selection method for delay test using design-for-testability circuit

遅延故障検査容易化設計を用いる検査対象経路の選択手法

電気・電子・情報関係学会四国支部連合大会講演論文集

電気・電子・情報関係学会四国支部連合大会講演論文集


Temperature Sensingwith a Built-in Relaxation Oscillator in CMOS ICs

弛緩発振器を用いた組込み型温度センサによる温度推定の可能性

電気・電子・情報関係学会四国支部連合大会講演論文集

電気・電子・情報関係学会四国支部連合大会講演論文集


Temperature Measurement in CMOS ICs with a Relaxation Oscillator Made of Analog Elements

アナログ素子で構成する弛緩発振器によるCMOS IC内温度測定

Proceedings of the Society Conference of IEICE

電子情報通信学会ソサイエティ大会講演論文集


Resistance Estimationof Open Defects between Dies in 3D ICs from pMOS On-Resistance for Open Defect Detection by Supply Current Test Method

電流テストによるダイ間断線検出のためのpMOSのオン抵抗値を用いた断線抵抗値の推定

電子情報通信学会ソサイエティ大会講演論文集


Experimental Examination of Open Defect Detectability by Injected Charge Volume in CMOS ICs

電荷注入量によるCMOS IC内断線の実験による検出可能性調査

電子情報通信学会ソサイエティ大会講演論文集


Development of a Die Selection Circuit in the Delay Test Architecture for 3D IC

3D ICの検査容易化設計における遅延故障検査用ダイ選択回路の開発

電子情報通信学会ソサイエティ大会講演論文集