Testing of Weak Open Defects in Interconnects Using Boundary Scan

バウンダリスキャンを用いる不完全接続の検査

Journal of Japan Institute of Electronics Packaging

エレクトロニクス実装学会誌


エレクトロニクス実装学会誌


Design for Testability Methods for Detecting Resistive Opens at Chip Interconnects

チップ間接続の半断線検出のための検査容易化設計手法

エレクトロニクス実装学会誌


Delay Testable Design Using Modified Boundary Scan

ディレイテスト可能なバウンダリスキャン設計手法

エレクトロニクス実装学会誌


Open Defect Detection in Assembled Circuit Boards with Built-In Relaxation Oscillators

In this article, we propose two kinds of electrical interconnect test methods for production tests and field ones of assembled circuit boards, which are performed prior to and after shipping to market, respectively. For these tests, we also propose a built-in test circuit. The methods we followed are based on the oscillation frequency of a relaxation oscillator (ROsc) embedded in integrated circuits (ICs). The frequency is measured as the number of pulse signals within a specified test time. Using the test methods, open defects at the interconnects between IC pins and a printed circuit board (PCB) are detected that are modeled as a resistor, a capacitor, and an open-circuit fault. We examined the detectability of open defects using the process variations afforded by SPICE simulation. The simulation results show that open defects were detected, modeled as a resistor of 45.8 Ω or above, along with open defects modeled as a capacitor and an open-circuit fault using the production test method. In addition, a resistance increase of 1.2 Ω at defect-free interconnects occurred after shipping to market was detected using the field test method. We also prototyped ICs with embedded ROscs and built an experimental circuit made of the ICs on PCBs. Moreover, we experimentally examined whether open defects could be detected. The results show that with the production test method, open defects modeled as a resistor of 10 Ω or above and modeled as a capacitor and an open-circuit fault can be detected.

IEEE Transactions on Components, Packaging, and Manufacturing Technology


Open Defect Detection Not Utilizing Boundary Scan Flip-Flops in Assembled Circuit Boards

An electrical interconnect test method is proposed to detect and locate open defects occurring at interconnects between integrated circuits (ICs) and a printed circuit board. The test method does not utilize boundary scan flip-flops. It is based on a quiescent supply current that is made to flow through an interconnect under test by embedding a test circuit into the ICs. The circuit consists of MOS switches for each input pin of the ICs and its switch control circuit. SPICE simulations are used to examine whether open defects at the interconnects can be detected using this method. The simulation results indicate that the following defective interconnects are detected in addition to defective ones modeled as an open-circuit fault at a test speed of 25 MHz: defective interconnects modeled as a resistor of 150 Ω generating an additional propagation delay of 482 psec and as a capacitor of 4 pF generating an additional propagation delay of 128 psec and no logical changes. Testability of open defects using this test method is also examined experimentally by prototyping an IC in which the test circuit is embedded. The experiments indicate that a resistive interconnect of 150 Ω and a defective one modeled as a capacitor of 2.2 nF can be detected by the test method at a test speed of 0.5 MHz.


Fault-Aware Dependability Enhancement Techniques for Flash Memories

By analyzing the fault behaviors of conventional flash memory fault models, two new concise fault types are proposed: the 1-safe fault and the 0-safe fault. For a 1(0)-safe fault, if logic 1(0) is programmed into the faulty cell, the effect of the fault can be masked. Data shaping (DS) and the page address remapping (PAR) techniques are used to increase the masking probability. DS manipulates the data patterns so that they can be written into the flash pages safely. PAR scrambles the logical-to-physical address mapping for data words and buffer words. Since the effect of a fault is masked for a large proportion of faulty cells, the burden on the error-correction code (ECC) is reduced, as is the number of incorporated redundancies. A novel test-and-repair flow is proposed that uses DS and PAR and corresponding hardware architectures are also developed. A simulator is used to evaluate the hardware overhead, the repair rate, the yield, and the reliability. The experimental results show that these measures are significantly improved with an almost negligible hardware overhead.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems


A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs

A design-for-testability method and an electrical interconnect test method are proposed to detect open defects occurring at interconnects among dies and input/output pins in 3D stacked ICs. As part of the design method, an nMOS and a diode are added to each input interconnect. The test method is based on measuring the quiescent current that is made to flow through an interconnect to be tested. The testability is examined both by SPICE simulation and by experimentation. Our test method enabled the detection of open defects occurring at the newly designed interconnects of dies at experiments test speed of 1MHz. The simulation results reveal that an open defect generating additional delay of 279psec is detectable by the test method at a test speed of 200MHz beside of open defects that generate no logical errors.

本論文では3D積層IC内のダイ間配線に発生する断線欠陥を電気的検査法で発見する検査法とその検査を可能にする検査容易化設計法を提案している．その検査容易化設計法はnMOSとダイオードを各入力配線に追加するもので，それらに検査時に静的電源電流を流しその異常でダイ間配線に発生する断線欠陥を検出する．その検出可能性を実験と回路シミュレーションで調査し，論理変化を生じない断線欠陥まで検出できる能力をその検査法は有していることを明らかにしている．

IEICE Transactions on Information and Systems


Discrimination of a Resistive Open Using Anomaly Detection of Delay Variation Induced by Transitions on Adjacent Lines

Small delay caused by a resistive open is difficult to test since circuit delay varies depending on various factors such as process variations and crosstalk even in fault-free circuits. We consider the problem of discriminating a resistive open by anomaly detection using delay distributions obtained by the effect of various input signals provided to adjacent lines. We examined the circuit delay in a fault-free circuit and a faulty circuit by applying electromagnetic simulator and circuit simulator for a line structure with adjacent lines under consideration of process variations. The effectiveness of the method that discriminates a resistive open is shown for the results obtained by the simulation.

隣接線を持つ信号線の断線故障発生時は，隣接線での信号遷移の影響をより受けることが知られている．故障の有無による遅延変動とトランジスタばらつきによる遅延変動を区別するため，複数の入力信号に対する遅延量を特徴量とする異常検知で故障判別を行う手法を提案する．

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences


Electrical Tests for Capacitive Open Defects in Assembled PCBs

Nowadays, Ball Grid Array (BGA) becomes a major packaging type due to its high bulk for input/output (I/O) pins. However, there are defects such as voids and cracks occurring between a BGA IC and a PCB which may result in an electrical failure in the circuit. This paper presents electrical tests for capacitive open defects occurring at an interconnection between an IC and a PCB. Feasibility of the electrical test with the test circuit is evaluated by SPICE simulation and experiments. Capacitive open defects occurring at interconnects are detected by the test method. Both simulation and experimental results showed that capacitive open defects generating no logical errors can be detected by the test method at a test speed of 1kHz and 1MHz.

Journal of Telecommunication, Electronic and Computer Engineering


Electrical Test of Resistive and Capacitive Open Defects at Data Bus in 3D Memory IC

We propose an electrical test method of resistive and capacitive open defects occurring at data bus lines between dies, and between dies and I/O pins in 3D memory ICs. The test method is based on supply current of an IC. The number of test vectors for a 3D memory IC made of ND memory dies in the test method is 10ND and small. Also, defective interconnects are located by the test method. Feasibility of the tests is examined by some experiments for a circuit made of an SRAM IC on a printed circuit board. The experimental results show that capacitive open defects and resistive open ones whose resistance values are greater than 200 can be detected by the test method.


A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs

In this paper, a built-in test circuit for an electrical interconnect test method is proposed to detect an open defect occurring at an interconnect between an IC and a printed circuit board. The test method is based on measuring the supply current of an inverter gate in the test circuit. A time-varying signal is provided to an interconnect as a test signal by the built-in test circuit. In this paper, the test circuit is evaluated by SPICE simulation and by experiments with a prototyping IC. The experimental results reveal that a hard open defect is detectable by the test method in addition to a resistive open defect and a capacitive open one at a test speed of 400 kHz.


Electrical Interconnect Test of Solder Joint Part with Boudary Scan Flip Flops and a Built-in Test Circuit

バウンダリスキャンテスト機構を用いたはんだ接合部の電気検査法とその組込型検査回路

Journal of Japan Institute of Electronics Packaging

エレクトロニクス実装学会誌


SAT-Based Test Generation for Open Faults Using Fault Excitation Caused by Effect of Adjacent Lines

Open faults are difficult to test since the voltage at the floating line is unpredictable and depends on the voltage at the adjacent lines. The effect of open faults can be easily excited if a test pattern provides the opposite logic value to most of the adjacent lines. In this paper, we present a procedure to generate as high a quality test as possible. We define the test quality for evaluating the effect of adjacent lines by assigning an opposite logic value to the faulty line. In our proposed test generation method, we utilize the SAT-based ATPG method. We generate test patterns that propagate the faulty effect to primary outputs and assign logic values to adjacent lines opposite that of the faulty line. In order to estimate test quality for open faults, we define the excitation effectiveness Eeff. To reduce the test volume, we utilize the open fault simulation. We calculate the excitation effectiveness by open fault simulation in order to eliminate unnecessary test patterns. The experimental results for the benchmark circuits prove the effectiveness of our procedure.

断線故障の影響は故障線とは反対の論理値を隣接線に与えることでより顕在化される．本論文では，隣接線への反転論理値割り当ての影響を評価するテスト指標を定義する．SATベースのATPGを用いて故障の影響を外部出力へ伝搬し，かつ隣接線へ反転論理値を割り当てるテスト生成手法を提案する．断線故障に対するテストパターンの質を評価するため，活性化効率Eeffを定義し，断線故障シミュレーションにより不要ベクトルの削除を行う．ベンチマーク回路に対する実行結果より提案手法の有効性を示す．


Electrical Testable Design for Open Defects at Logic Signal Lines between Dies in 3D ICs

3次元実装IC内ダイ間論理信号線の断線に対する電気テスト用回路

本論文では3次元実装IC内のダイ間の論理信号線に発生する断線の電気テストを可能にする検査用回路とそれを用いたテスト法を提案する.その検査用回路はIEEE1149.1の検査回路を流用するもので,断線の検出と断線配線の特定を可能とするとともに,ESD入力保護回路を変更しないため,その保護能力低下を招かない.本検査用回路によるテスト法の検査能力は回路シミュレーションと,試作ICを用いてプリント配線板上に作製した回路における実験で調査した.その結果,本検査用回路を用いた電気テスト法により完全断線だけでなく,従来のテスト法で見逃す可能性のある抵抗断線,容量断線を検査速度20MHzで検出でき,また断線配線の特定も容易に行えることがわかった.

The Transactions of the Institute of Electronics, Information and Communication Engineers C

電子情報通信学会論文誌(C)


On Detecting Delay Faults Using Time-to-Digital Converter Embedded in Boundary Scan

This paper proposes a method for testing delay faults using a boundary scan circuit in which a time-to-digital converter (TDC) is embedded. The incoming transitions from the other cores or chips are captured at the boundary scan circuit. The TDC circuit is modified to set the initial value for a delay line through which the transition is propagated. The condition for measuring timing slacks of two or more paths is also investigated since the overlap of the signals may occur in the delay line of the TDC in our boundary scan circuit. An experimental IC with the TDC and boundary scan is fabricated and is measured to estimate the delay of some paths measured by the TDC embedded in boundary scan cells. The simulation results for a benchmark circuit with the boundary scan circuit are also shown for the case that timing slacks of multiple paths can be observed even if the signals overlap in the TDC.

本論文はタイムデジタイザを組込んだバウンダリスキャン回路を用いる遅延故障テスト手法を提案する．本テスト回路では他のコアまたはチップからの入力遷移がバウンダリスキャン回路でキャプチャされる．タイムデジタイザを修正し，遷移が伝搬する遅延線の初期値を設定可能とした．また，2つ以上の信号が遅延線で重複する可能性があるため，2つ以上の経路のタイミングスラックの測定条件を調査する．タイムデジタイザとバウンダリスキャンを含むICを試作し複数経路の遅延測定を行った．またタイムデジタイザ内で信号の重複が生じてもタイミングスラックの観測可能な場合のシミュレーション結果を示す．

IEICE Transactions on Information and Systems


Electrical Test Method for Interconnect Open Defects in 3D ICs

In this paper, an electrical test method is proposed to detect and locate open defects occurring at interconnects between two dies in 3D ICs. The test method utilizes a test architecture based on IEEE 1149.1 standards to provide a test vector to a targeted interconnect. Also, a testable design method for the IC is proposed for our testing. In this paper, testability of the electrical testing is evaluated using a SPICE simulation. The simulation results show that a resistive open defect of 100 Ω can be detected at a test speed of 1 GHz. Also, the test circuit is implemented inside a prototype IC. It is experimentally examined whether open defects between the IC and a printed circuit board can be detected by the test method. They are detected at a speed of 10 MHz by the test method in the experiments. It promises that interconnect open defects in a 3D IC can be detected by the test method per an interconnect at a test speed of at least 10 MHz.

本論文では3D IC 内の2つのダイ間配線で起こる断線故障の検出および位置指摘を行う電気的テスト手法を提案する．本テスト手法ではIEEE1149.1標準テスト機構を用いて対象配線にテストベクトルを供給する．また本テスト手法に適するテスト容易化設計を提案する．SPICEシミュレーションによる評価実験で，テスト速度1GHzのもとで100Ω以上の抵抗性断線が検出可能であることを確認した．また試作IC内にテスト回路を実装し，ICとプリント基板間に発生する断線が検出可能であることを確認した．実験結果より3D ICにおいても少なくとも10MHzのテスト速度でのIC間配線の断線欠陥検出が可能であることを確認した．

Transactions of The Japan Institute of Electronics Packaging


Electrical Testing of Open Defects between IEEE1149.1 Compliant ICs

バウンダリスキャンテスト機構を流用し,完全断線,半断線を確実に発見し,また不良発生箇所も容易に特定できるような電気検査法の開発を試みた．ここではその検査法とその検査を可能にする検査容易化設計法を提案するとともに,IC を試作しその IC を用いた実験で検査可能性を明らかにする．

エレクトロニクス実装学会誌


A Method for Locating Open Faults by Using a Fault Extraction Function

故障励起関数を利用したオープン故障の診断法

回路の微細化や銅配線の導入により,配線やビアの断線の発生頻度が高まっている.そのため,効率的なオープン故障の診断法の開発の重要性が増してきている.本論文では,完全に断線した信号線の論理値が,隣接信号線の論理値のしきい値関数として表される故障励起関数を提案する.次に,この故障励起関数を利用した単一オープン故障の診断法を提案する.この診断法では,故障励起関数を利用して故障信号線を絞り込み,更に故障信号線上の断線位置の推定を行う.計算機実験による性能評価の結果は,ほとんどの故障回路に対して高速に被疑故障信号線を1箇所に特定できること,及び故障信号線上の断線位置を故障信号線の長さの25%程度まで絞り込むことができることを示している.

The Transactions of the Institute of Electronics, Information and Communication Engineers D

電子情報通信学会論文誌(D)


Scan Chain Ordering to Reduce Test Data for BIST-Aided Scan Test Using Compatible Scan Flip-Flops

In this paper, the scan chain ordering method for BIST-aided scan test for reducing test data and test application time is proposed. In this work, we utilize the simple LFSR without a phase shifter as PRPG and configure scan chains using the compatible set of flip-flops with considering the correlations among flip-flops in an LFSR. The method can reduce the number of inverter codes required for inverting the bits in PRPG patterns that conflict with ATPG patterns. The experimental results for some benchmark circuits are shown to present the feasibility of our test method.

本論文ではBIST-aidedスキャンテストのテストデータおよびテスト実行時間を削減するためのスキャンチェイン構成法を提案する．本手法では，PRPGに位相シフト回路を用いない簡単なLFSRを使用し，LFSR内のフリップフロップの相関関係を考慮するフリップフロップの両立集合を用いたスキャンチェイン構成を行う．提案手法はATPGパターンと矛盾するPRPGパターン内のビットを反転するための反転コードの削減が可能である．ベンチマーク回路に対する実験結果よりテスト手法の有効性を評価する．


Open lead detection method by sensing the switching current of CMOS gate on sensing probe

CMOSゲート回路を断線センサとして用いた部品接合不良検出法

We propose a new test method for detecting open leads on ICs. The test method is based on using the supply current of a CMOS gate as an open lead detector; the current flows when an AC voltage signal is provided to a targeted lead with a probe as a stimulus. To evaluate the test method, we examined whether it could detect open leads in SSIs and LSIs. The experimental results confirm that open leads can be detected within 1μsec by providing an AC voltage signal with an amplitude that is 60% of the power supply voltage of the targeted IC.

本論文でははんだ付け時に発生するICのリードとプリント配線板のランド間の断線故障を検出する電気的検査法を提案している．その検査法はオープンセンサとしてCMOSゲートICを使用し,検査プローブを検査対象リードに接触させ交流電圧信号を印加したときのセンサの電源電流測定により,断線故障を検出するものである．本論文では,SSIおよびLSIのリードの断線故障検出がその検査法で行えることを実験で明らかにしている．また,その実験でその検出を可能にする交流電圧信号の振幅と周波数を調査し,電源電圧の0.6倍の振幅の交流電圧信号の印加により1μsecの時間でリードの断線検出が行えることも明らかにしている．

Journal of Japan Institute of Electronics Packaging

エレクトロニクス実装学会誌


Applied AC Voltage for Detecting Open Leads of CMOS LSI by Monitoring Supply Current under AC Electric Field

交流電界印加時の電流テストによるCMOS LSIのリード浮き検出のための印加交流電圧

We have proposed a supply current test method for detecting open leads in CMOS ICs. The method is based on the supply current of a circuit made of CMOS ICs, which flows when an AC electric field is supplied from outside the ICs. The electric field is generated by providing AC voltage between electrodes which are placed over the targeted leads and under a targeted PCB. In this paper, we experimentally examine how large an amplitude of AC voltage should be provided between the electrodes to detect open leads in the CPLD LSIs of PLCC, QFP and TQFP packages. The results reveal that the amplitude of the AC voltage needed to enable open leads detection depends on the shape of the package and the logic threshold voltage of the targeted ICs and printed circuit boards used. Also, they show that in some LSIs the required amplitude depends on the output logic level to an open lead.

プリント配線板上に実装されたCMOS論理ICのリード浮きを,検査対象リードの上部とプリント配線板の下に検査時にのみ設置した電極間に交流電圧を加え,発生する交流電界で現れる電源電流異常で検出する検査法が提案済みである．しかし,その電極に印加する交流電圧の大きさが何によって決まるのか明らかにされていない．そこで,われわれはCMOS LSIのリード浮き検出を可能にする交流電圧の大きさを実験により調査した．本論文ではその電圧の大きさは検査対象LSIのパッケージの形状,論理しきい値電圧,使用するプリント配線板に依存すること,ならびにリード浮き発生信号線への出力論理値に依存する場合があることを示す．

エレクトロニクス実装学会誌


Reducing Scan Shifts Using Configurations of Compatible and Folding Scan Trees

In this paper, a new method for reducing scan shifts is presented. Scan design is one of the most popular designs for test method for sequential circuits. However, for circuits with many flip-flops, it requires a long test application time and high test-data volume. Our new scan method utilizes two configurations of scan chains, a folding scan tree and a fully compatible scan tree to alleviate these problems. It is observed that uncompacted test patterns typically contain a large fraction of don't care values. This property is exploited in the fully compatible scan tree to reduce scan shifts without degrading fault coverage. Then, a folding scan tree is configured to further reduce the length of scan chain and scan shifts. Experimental results on benchmark circuits show that this scan method can significantly reduce scan shifts.

本論文ではスキャンシフト数の削減を行う新たな手法を提案する．提案するスキャン手法では折り畳み型スキャンツリーと完全両立型スキャンツリーの2種の構成を用いる．非圧縮のテストパターンには多くのドントケア値が存在することを利用し，故障検出率が低下しない完全両立スキャンツリー構成を求め，さらにスキャンチェーンを短くしスキャンシフト数を削減する折り畳み型スキャンツリーを構成する．ベンチマーク回路に対する実験よりスキャンシフト数が大幅に削減されることを示す．

Journal of Electronic Testing - Theory and Applications


ばらつきを有するICで構成したTTL回路の電源電流による統計的断線故障検出法

ばらつきを有するICで構成したTTL回路の電源電流による統計的断線故障検出法

In this paper, a supply-current test method is proposed for detecting open faults in logic circuits made of TTL ICs on printed circuit boards. This method is applicable even if there is any variation of the supply current among the ICs used. In this method, variation of the supply current in a logic circuit is modeled as a Gaussian distribution and a statistical analysis method with level of significance is used for fault detection. In this paper, the fault coverage of the test method is evaluated experimentally. In the experimental evaluation, test input vectors of the supply-current test method are generated for detecting single open faults of signal lines in ISCAS-85 benchmark circuits made of TTL SSIs. The results show that more open faults can be detected by this test method than by a functional test method if the deviation (ς/μ) of the supply current in each SSI used is smaller than 1.1%.

本論文では, TTL ICを用いてプリント回路板上に作製した論理回路の電源電流測定による断線故障検出法を提案する．この検出法は使用ICの電源電圧-電源電流特性にばらつきが存在する場合にでも適用可能で, 使用ICの電源電流特性のばらつきを正規分布でモデル化し, 有意差検定法で断線故障を統計的に検出するものである．その故障検出能力を評価するため, TTL SSIを用いて作製したISCAS-85ベンチマーク回路内の信号線の単一断線故障を検出する検査入力を生成し, その故障検出率を調べた．その結果, 有意水準0.1の場合, SSIの電源電流値のばらつきが1.1%以下なら, 現在一般的に使用されているファンクションテスト法よりも提案する検査法の方がより多くの断線故障を検出できる可能性があることがわかった．

エレクトロニクス実装学会誌


Genetic State Reduction Method of Incompletely Specified Machines

A new state reduction method of incompletely specified sequential machines is proposed in this paper. The method is based on a genetic algorithm implementing a dormant mechanism. MCNC benchmark machines are simplified by using this method to evaluate the method. The experimental results show that machines of almost the same number of states as the minimum ones can be derived by this method.

不完全指定順序機械の状態削減手法を提案する．提案手法は休眠機構を実装した遺伝的アルゴリズムを基にしている．本手法を用いてMCNCベンチマーク回路の簡単化を行った結果から，ほぼ最小解に近い数の状態が提案手法により得られた．

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences


Lead Open Detection Based on Supply Current of CMOS LSIs

In this paper, a test method is proposed to detect lead opens in CMOS LSIs. The test method is based on supply current which flows when test input vectors and AC electric field are provided from the outside of the ICs. Also, an application method of the test input vectors is proposed in this paper. It is shown experimentally that lead opens of SSIs and LSIs will be detected by providing each of the test input vectors per the period of AC electric field applied.

本論文ではCMOS LSIのリード浮きを検出する手法を提案する．提案するテスト手法はテスト入力ベクトルとIC外部からの交流電界印加時に流れる電源電流を用いて検査を行う．また，テスト入力ベクトルの印加方法も提案する．交流電界の周期に合わせてテスト入力ベクトルを印加することでSSIやLSIでのリード浮きを検出されることを実験的に示す．


Test Sequence Generation for Test Time Reduction of IDDQ Testing

In this paper, test time reduction for IDDQ testing is discussed. Although IDDQ testing is known to be effective to detect faults in CMOS circuit, test time of IDDQ testing is larger than that of logic testing since supply current is measured after a circuit is in its quiescent state. It is shown by simulation that test time of IDDQ test mostly depends on switching current. A procedure to modify test vectors and a procedure to arrange test vectors are presented for reducing the test time of IDDQ testing. A test sequence is modified such that switching current quickly disappears. The procedure utilizes a unit delay model to estimate the time of the last transition of logic value from L to H in a circuit. Experimental results for benchmark circuits show the effectiveness of the procedure.

本論文では，IDDQテストのテスト時間短縮について論じる．IDDQテストはCMOS回路の故障検出に有効であるが，回路が静的状態に安定した後に電流を測定するため論理値テストに比べて時間がかかる．IDDQテスト時間は主にスイッチング電流に依存することが知られている．提案手法では，スイッチング電流が早くおさまるようにテストベクトルを修正し，ベクトルの印加順を決定する．提案手法ではユニット遅延モデルを用いてLからHへの論理値遷移の完了時刻を推定する．ベンチマーク回路に対する実験結果より手法の有効性を示す．

IEICE Transactions on Information and Systems


Identification and Frequency Estimation of Feedback Bridging Faults Generating Logical Oscillation in CMOS Circuits

When a feedback bridging fault occurs in a combinational circuit and it is activated, logical oscillation may occur in the circuit. In this paper, some electrical conditions are proposed to identify whether a feedback bridging fault occurs logical oscillation. Also, it is proposed how to estimate the oscillation frequency. They are based on piece linearized models and do not require circuit simulation of large size of circuits. They are evaluated by some experiments. In the experiments, all of the feedback bridging faults occurring logical oscillation are identified. Also, oscillation frequencies larger than the ones obtained by SPICE simulation are derived by the proposed estimation method in the experiments. It promises us that the methods will be used for identifying such bridging faults and estimating the oscillation frequencies.

回路内にフイードバックブリッジ故障が発生し，活性化されると論理発振が起こる可能性がある．本論文では，フィードバックブリッジ故障発生時に論理発振が起こる電気的条件を考察する．また，論理発信の周波数の評価を行う手法を提案する．提案手法は区分線形モデルを用いることで大規模回路に対する回路シミュレーションを不要とする．実験により，論理発振を生じるすべてのフィードバックブリッジ故障が判定できた．また，実験ではSPICEシミュレーションにより得られるよりも高い周波数を提案手法が予測可能であることを示す．


Test Pattern Generation for CMOS Open Defect Detection by Supply Current Testing under AC Electric Field

In this paper, supply current testing for detecting open defects in CMOS circuits is discussed. It is known that open defects cause unpredictable faulty effects and are difficult to be detected. In our test method, an AC electric field is applied during testing. The voltage at a floating node caused by an open defect is varied by the applied electric field and then the defect can be detected. The test pattern generation procedure for open defects is proposed and is applied to benchmark circuits. The experimental results shows that the number of test vectors for opens are much smaller than that for stuck-at faults. The experimental evaluation for an LSI chip is also shown to present the feasibility of our test method.

本論文では，CMOS回路内の断線故障を検出する電源電流テストを提案する．断線故障は故障の影響が予測不能であるため検査が困難である．提案手法では，交流電界をテスト中に印加する．故障によるフローティングノードの電圧は印加電圧により変動するため，故障検査が可能となる．断線故障用テストパターン生成手法を提案し，ベンチマーク回路に対する実験を行った結果，縮退故障用テストパターンに比べてより少量のテストパターンで検査が可能であることを示す．また，LSIチップに対する実測実験により本テスト手法の有効性を示す．


CMOSマイクロコンピュータ回路の電源電流によるブリッジ故障検出法

CMOSマイクロコンピュータ回路の電源電流によるブリッジ故障検出法

A new supply current test method is proposed for bridging faults in CMOS microprocessor based circuits which are implemented circuit boards with discrete ICs. The method is based on supply current of a circuit under test, which flows when a test program is executed. A commercial microcomputer circuit is tested by the proposed method. In the tests, 98.7% of the bridging faults between two neighboring pins in the circuit are detected within 326 msec. It promises us that the method can be used in production tests of microprocessor based circuits. Also, it is sown that the test program can be developed by means of timing charts in data sheets of the microprocessor.

CMOSマイクロプロセッサを用いてプリント配線板上に実現したマイクロコンピュータに発生するブリッジ故障を検査プログラム実行時の電源電流測定により検出する検査法を，本論文では提案している．その検査法を商用のボイラ制御用マイクロコンピュータ回路の検査に適用し，使用ICの隣合う2本のピン間の単一ブリッジ故障の98.7%を検査時間326msecで検出できることを実験で明らかにしている．また，本検査法での検査時に実行させる検査プログラムの開発支援ツールがマイクロプロセッサのデータシート内で公開されているタイミングチャートを利用して開発できることも明らかにしている．

Journal of Japan Institute of Electronics Packaging

エレクトロニクス実装学会誌


A Test Circuit for Pin Shorts Generating Oscillation in CMOS Logic Circuits

CMOS論理回路の発振を生じるICピン短絡故障検出回路

CMOS論理ICをプリント配線板上にはんだ付けする際，ICピン短絡故障が発生する可能性がある．その故障励起時に，故障発生箇所に論理発振が生じる場合がある．その論理発振を生じる故障を論理回路に流れる電源電流によって検出するための検査法とその検査回路を本論文では提案している．実際にその検査回路を試作し，故障励起時に論理発振を生じる故障がその検査回路で検出できることを実験により明らかにしている．

The Transactions of the Institute of Electronics, Information and Communication Engineers D-I

電子情報通信学会論文誌(D-I)


Pin Open Detection for CMOS Logic ICs by Measuring Supply Current under AC Electric Field

CMOS論理ICの交流電界印加時の電源電流測定によるピン浮き検出法

A new test method is proposed in this paper for detecting pin opens in CMOS logic circuits fabricated on printed circuit boards, which are caused by missing solder and so on. In our test method, supply current of an IC is measured with AC electric filed applied outside of CMOS ICs. When any pin opens do not occur in the IC, only quiescent supply current will flow. If a pin open occurs, large supply current change will be generated. The proposed test method uses this property for detecting pin opens. In this paper, the feasibility of the test method is evaluated by some experiments. Also, the test input vectors are proposed for this test method.

本論文では,プリント配線板上に実装されたCM0S論理回路の,はんだ付け不良などにより発生するピン浮きを検出するための新しい検査法を提案する．本検査法では被検査回路の外部から交流電界を印加し,ICの電源電流を測定する．ピン浮きがない場合は,外部から交流電界を印加しても定常時にはそのICに静的電源電流しか流れない．しかしピン浮きがあると,そのICの電源電流に大きな変化が現れる．本論文ではこの性質を用いてピン浮きが検出可能であることを実験により示す．またこの検査法で必要となる検査入力パターンについても明らかにする．

エレクトロニクス実装学会誌


CMOS Open Defect Detection by Supply Current Measurement under Time-Variable Electric Field Supply

In this paper, a new test method is proposed for detecting open defects in CMOS logic ICs. The method is based on supply current of ICs generated by supplying time-variable supply voltage and electric field from the outside of the ICs. Also, test input vectors for the test method are proposed and it is shown that they can be generated more easily than functional test methods based on stuck-at fault models. The feasibility of the test is examined by some experiments. The empirical results promise us that by using the method, open defects in CMOS ICs can be detected.

本論文では，CMOS論理ICの断線故障を検出する新たなテスト手法を提案する．提案手法は，IC外部から時変電圧・時変電界を与えることで生じる電源電流を用いて検査を行う．また，提案手法で用いる検査入力は機能テストよりも容易に生成可能であることも示す．本テスト手法によりCMOS ICの断線故障検出に有効であることを，実験により示す．


IDDQ Test Time Reduction by High Speed Charging of Load Capacitors of CMOS Logic Gates

In this paper, a useful technique is proposed for realizing high speed IDDQ tests. By using the technique, load capacitors of the CMOS logic gates can be charged quickly, whose output logic values change from L to H by applying a test input vector to a circuit under test. The technique is applied to built-in I_<DDQ> sensor design and external I_<DDQ> sensor design. It is shown experimentally that high speed IDDQ tests can be realized by using the technique.

本論文では，高速IDDQテストを実現する有用な手法を提案する．提案手法により，出力電圧がLからHに遷移する論理ゲートの負荷容量の充電が高速に行われる．提案手法は，組込み型のIDDQセンサ，外部IDDQセンサのいずれの設計にも適用可能である．実験により高速IDDQテストが実現可能であることを示す．


Testable Static CMOS PLA for IDDQ Testing

A new IDDQ tastable design method is proposed for static CMOS PLA circuits. A testable PLA circuit of NOR-NOR type is designed using this method. It is shown that all bridging faults in NOR planes of the tastable designed PLA circuit can be detected by IDDQ testing with 4 sets of test input vectors. The test input vectors are independent of the logical functions to be realized in the PLA circuit. PLA circuits are designed using this method so that the quiescent supply current generated when they are tested will be zero. Thus, high resolution of IDDQ tests for the PLA circuits can be obtained by using the testable design method. Results of IDDQ tests of PLA circuits designed using this testable design method confirm not that the expected output can be generated from the circuits but that the circuits are fabricated without bridging faults in NOR planes. Since bridging faults often occur in state-of-the-art IC fabrication, the testable design is indispensable for realizing highly reliable logic systems.

静的CMOS PLA回路のIDDQテスト容易化設計手法を提案する．NOR平面上の全ての短絡故障が4つのテスト入力ベクトルにより検出可能であることを示す．テスト入力ベクトルはPLAの論理関数と独立であり，かつ検査容易化設計されたPLA回路はテスト時に静的電源電流が0となる．提案回路を用いるIDDQテストの適用により，回路から期待する出力が得られることだけでなく，NOR平面上に短絡故障が存在しないことも保証される．最先端のIC製造では短絡故障が発生するため，本テスト容易化設計が高信頼な論理回路を実現するのに不可欠である．

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences


Finding Unreachable States of Sequential Circuits

Some states in a sequential circuit can not be reached by any input sequence. A state is said to be unreachable if it has no transition from any other state. A test generator wastes a time if it tries to bring a state of a circuit to an unreachable state. Therefore the information about unreachable states in the circuit is useful for reducing test generation time. We have reported that obtaining strongly unreachable states, which is a part of unreachable states, is useful to simplify the sequential circuit. In this paper, we present a procedure to identify strongly unreachable states for the circuit which is described by the gate-level and whose state transition table is not given. The input functions of flip-flops are used to identify the invalid combination of state values. Since the procedure to identify unreachable states requires large memory for the circuits with many flip-flops, we also present a procedure to partition the set of flip-flops in order to restrict the number of flip-flops. Experimental results for benchmark sequential circuits show the effectiveness of the proposed procedure.

順序回路のいくつかの状態はいかなる入力系列によっても到達できない．それらの状態を到達不能状態とよび，テスト生成においては処理時間の無駄を生じる原因となる．本論文では，状態遷移表が与えられていないゲートレベル記述の順序回路に対して，到達不能状態の一部である強到達不能状態を同定する手法を提案する．フリップフロップの入力関数により到達不能な状態値の組合せを同定する．多くのフリップフロップを持つ回路ではメモリを多く必要とするため，フリップフロップ集合を分割するを行う手法も提案する．ベンチマーク回路への実験結果より提案手法の有効性を示す．

Technology Reports of the Osaka University


A Redundancy Removal Method for Sequential Circuits Based on Unreachable States

到達不能状態に基づく順序回路の冗長除去手法

縮退故障の存在する論理回路の出力系列が正常回路の出力系列と等しくなるとき, 故障に対応する信号線を除去することで回路を簡単化できる.故障に対応する信号線が除去できるとき, その故障は除去可能であると言う.本論文では除去可能な縮退故障の一部を容易に求める手法を提案する.提案手法ではいかなる状態からも遷移させることのできない到達不能状態に基づいて検出不能故障を求め, その状態が故障回路において到達不能であるか否かによりその故障の除去可能性を判定する.本手法では判定に用いる状態を到達不能状態に限るため, フリップフロップ数の多い回路に対しても適用可能である.ベンチマーク回路に対する実験結果より多くの冗長部分が除去されることを示す.また, テスト生成の結果から本手法の適用により回路のテスタビリティが向上することも示す.

電子情報通信学会論文誌(D-I)


Synthesis of Sequential Circuits by Redundancy Removal and Retiming

In this paper we propose a method for synthesizing sequential circuits to reduce the number of gates and flip-flops by removing both combinationally and sequentially redundant faults. In order to remove sequentially redundant faults these faults are converted into combinationally redundant faults by using retiming techniques and the combinationally redundant faults can be removed by using a test pattern generation method for combinational circuits. To simplify a given circuit retiming is utilized for two purposes in this method. One is to find sequentially redundant faults and another is to reduce the number of flip-flops and gates. Before and after each retiming the combinationally redundant faults are removed. Experimental results for ISCAS '89 benchmark circuits show that this method can remove many of sequentially redundant faults and can reduce a large number of gates and flip-flops.

本論文では，組合せ回路的冗長故障と順序回路的冗長故障をともに除去することで順序回路のゲート・フリップフロップの削減する順序回路の合成手法を提案する．順序回路的冗長故障をリタイミング手法を用いて組合せ回路的冗長故障に変換し，組合せ回路的冗長故障を組合せ回路用テスト生成手法により除去する．リタイミングは，順序回路的冗長故障の同定と，フリップフロップ数の削減に用いられる．ISCAS89ベンチマーク回路に対する実験結果より提案手法が多くの順序回路的冗長故障を削除でき，多くのゲートおよびフリップフロップを削減可能であることを示す．

Journal of Electronic Testing - Theory and Applications


Retiming for Sequential Circuits with a Specified Initial State and Its Application to Testability Enhancement

Retiming is a technique to resynthesize a synchronous sequential circuit by rearranging flip-flops. In view of logic optimization, retiming can potentially derive a circuit which is more simplified and testable because retiming can convert several sequential redundancies into combinational redundancies. Retiming methods proposed before have no guarantee to generate the same output sequences when the circuit start from a specified initial state such as the reset state. If the circuit with a specified initial state must have the same output sequences after retiming, rearrangement of flip-flops should be restricted. This paper presents a retiming method for circuits with a specified initial state so that retimed circuits give the same output sequences of the original circuits for any input sequences. In the proposed method, during the procedure of retiming each flip-flop keeps a value corresponding to the initial state and unification of flip-flops with different value is avoided. Our procedure uses 5-valued logic on gate level implementation to describe and calculate the values of flip-flops. Therefore after optimization using our method, the circuit has completely the same behavior as that of the original. Experimental results for ISCAS'89 benchmark circuits show the method can be used to optimize the circuits as well as a method without considering the initial state. And testability of the retimed circuit is more enhanced than that of the original circuit.

リタイミングはフリップフロップの再配置により同期式順序回路を再合成する手法である．論理最適化の観点からはリタイミングにより順序回路的冗長を組合せ回路的冗長に変換することで，回路がより簡単かつ検査容易になる可能性がある．従来のリタイミング手法は特定の初期状態からの出力系列の保持を保証していなかった．本論文では特定の初期状態を持つ回路がリタイミング適用後でも同一の出力系列が得られることを保証するリタイミング手法を提案する．本手法では初期状態に対応するフリップフロップの論理値を保持し，異なる値のフリップフロップを併合しないことで初期状態に対応する状態が必ず存在することを保証する．

IEICE Transactions on Information and Systems


On testing of open faults in multi-layered wiring LSIs

多層配線LSIの断線故障検査に関する研究

Open faults are difficult to test since the floating wire occurred by an open fault has unstable voltage. In this work, the effect of adjacent lines around an open fault in multi-layered wiring LSIs is discussed. To observe the relation between an open fault and the adjacent lines, a 0.35μm CMOS IC is designed and fabricated. The open fault macros with a transmission gate and with an intentional break are included in the IC. The adjacent lines in the same layer and the different layers are placed in the test chip. The simulation and experimental results show that the voltage at the floating wire is affected by the adjacent lines.

本研究では,IC 試作 により隣接信号線電位が断線故障発生箇所の電位に与える影響について観測を行った.IC 試作では,トランスミッションゲート(TG)を用いて擬似的に導通状態と断線状態の制御可能とする擬似断線故障と,信号線に完全断線を挿入した擬似断線故障を含む回路を CMOS 0.35μm プロセスにて設計した.電子回路シミュレーションにより隣接信号線とのカップリング容量が断線信号線電位に与える影響を確認し, 試作 IC の実測により同層および上下層間の隣接信号線が 断線信号線に与える影響について観測した.

Bulletin of Institute of Technology and Science, The University of Tokushima

徳島大学大学院ソシオテクノサイエンス研究部研究報告


Propagation Delay Analysis of a Soft Open Defect inside a TSV

The propagation delay of a logic signal through a through silicon via (TSV) in a 3D IC may depend on a soft open defect inside it. The propagation delay of a defective TSV which is connected only with barrier metal, in part owing to a soft open defect, is analyzed with an electromagnetic simulator and a circuit one in this paper. The results reveal that if such a soft open defect occurs inside a TSV, the delay depends on the defect size and the IC may work without any errors. A soft open defect will change into a hard open one in operation of a 3D IC and may generate a logical error. In order to realize high reliability of the IC, the defect should be detected before it changes into a hard open defect. In this paper, test input vectors are proposed with which a soft open defect can be detected by delay testing. However, the simulation results suggest that when the input and output capacitance of a TSV is small, the defect may not be detected even if the test vectors are provided to the defective IC, since the propagation delay of the defective TSV can be smaller than a defect-free one.

3D IC 内のシリコン貫通ビア(TSV)を通る論理信号の伝搬遅延はTSV内の半断線欠陥に依存する可能性がある．本論文では電磁界シミュレータと回路シミュレータを用いて半断線欠陥によりTSVがバリアメタルのみで導通している欠陥TSVの伝搬遅延の解析を行う．解析結果より，遅延が欠陥サイズに依存し，ICが障害なしで動作する場合があることを示す．半断線欠陥は3D ICの動作により完全断線に変化し論理故障を引き起こす可能性があるため，ICの高信頼化の実現には半断線が完全断線になる前に検出すべきである．本論文では遅延テストで半断線を検出するためのテスト入力ベクトルを提案する．シミュレーション結果からTSVの入出力容量が小さい場合には提案するテストベクトルを印加しても遅延が小さく検出されない場合もあることも示す

Transactions of The Japan Institute of Electronics Packaging


Sequential Redundancy Removal Using Test Generation and Multiple Strongly Unreachable States

A procedure to remove redundancies in sequential circuits is proposed using strongly unreachable states, which are the states with no incoming transitions. Test generation is used to find undetectable faults related to two or more strongly unreachable states. Experimental results show the new procedure can find more redundancies of sequential circuits.

入力遷移を持たない状態である強到達不能状態を用いる順序回路の上長除去手法を提案する．テスト生成手法を用いて2つ以上の強到達不能状態に関連する検出不能故障を同定する．実験により提案手法がより多くの冗長箇所を発見することを示す．