CU partitioning algorithm based on texture complexity in VVC

Proceedings of the 2024 6th International Conference on Video, Signal and Image Processing, VSIP 2024


Semantic Segmentation of River Video for Smart River Monitoring System

Proceedings of 13th Global Conference on Consumer Electronics (GCCE2024)


Color Correction Method using Monocular Depth Estimation Model for Underwater Images


Bitrate Control for VVC based on RD-Cost Estimation with YOLOv8


Semantic Segmentation for Intersection Images with Domain Adaptation


Intra Prediction Mode using Conditional-UNet by Stochastic Differential Equations for Next Generation Video Coding

Proceedings of International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC2024)


Partial Image Generation with VQGAN for River Surveillance Video Coding


Low Bit Rate Video Coding using VVC and DCVC-DC for River Surveillance


Efficient Deraining model using Transformer and Kernel Basis Attention for UAVs


Underwater Object Detection Through Analysis and Data Augmentation of Underwater Datasets


A Novel GAN-Based Intra Prediction Mode for HEVC

The International Symposium on Communications and Information Technologies (ISCIT) 2023


Refined Datasets and Saliency Map Analysis for Underwater Object Detection


High Efficiency Image Correction for Object Detection Improvement in Low-Power Underwater Drones


An Efficient Merge Mode with Motion Vector Difference Approach for Versatile Video Coding

Proceedings of the 2023 11th International Conference on Communications and Broadband Networking(ICCBN)


A High Precision Counting Framework for Cerithidea moerchii towards Low Power Implementation

Proceedings of International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC2023)


Semantic Segmentation of River Video for Efficient River Surveillance System


Video Semantic Segmentation for Intersection by Domain Adaptation


YOLO-based Bitrate Control Algorithm for VVC


A Novel Intra Prediction Mode using Transformer-based GAN for VVenC

Advances in Signal Processing and Artificial Intelligence (ASPAI) 2023


Context Similarity-enabled CU Partitioning Algorithm in VVC

2023 5th International Conference on Communications, Information System and Computer Engineering (CISCE)


VVC Coding Unit Partitioning Decision based on Naive Bayes Theory

Proceedings of the 2023 5th International Conference on Image Processing and Machine Vision


A Fast CU Partitioning Algorithm Based on Texture Characteristics for VVC


Dataset Generation and De-raining Algorithms for Video System of Drone

The 9th International Forum on Advanced Technologies 2023 (IFAT2023)


An Adaptive Selection Algorithm of Screen Content Coding Tools for Educational Video System

Proceedings of IEEE International Conference on Consumer Electronics(ICCE)


Semi-Supervised Learning Based De-Raining Method for UAV


Coordinate Attention-enabled Ship Object Detection with Electro-optical Image

Proceedings of International Conference on Computing and Pattern Recognition


Depth Estimation with Sonar-based Correction for Low-cost Underwater Drone


Object Recognition based Self-Position Estimation for Underwater Robots


YOLOX based Underwater Object Detection for Inshore Aquaculture


Investigation of Sensors Related 3D-Mapping Algorithm for Monocular Video based Underwater Vehicles

Proceedings of International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC2022)


High-Accuracy Object Detection Using Multi-view Video at Road Intersections


High Efficiency Dataset Generation for Semantic Video Segmentation on Road Intersection


A Novel Video Coding Framework with GAN-based Face Generation for Videoconferencing


Object Detection in Curved Mirror with Multi-Cameras from Single Viewpoint Video


Deep Learning-Based Quality Enhancement Algorithms for Background of Video


High Efficiency Image Correction for Low Power Underwater Drone


Detection of Plant Leaf Disease using Deep Learning

The 8th International Forum on Advanced Technologies 2022 (IFAT2022)


Adaptive Cross Component Linear Model for Chroma Intra-Prediction in VVC

10th International Conference on Communications and Broadband Networking (ICCBN 2022)

Cross-Component Linear Model (CCLM) for chroma intra-prediction is a promising coding tool in Joint Exploration Model (JEM) developed by the Joint Video Exploration Team (JVET). CCLM assumes a linear correlation between the luma and chroma components in a coding block. With this assumption, the chroma components can be predicted by the Linear Model (LM) mode, which utilizes the reconstructed neighbouring samples to derive parameters of a linear model by linear regression. This paper presents three new methods to further improve the coding efficiency of CCLM. First, we introduce a multi-model CCLM (MM-CCLM) approach, which applies more than one linear models to a coding block. With MM-CCLM, reconstructed neighbouring luma and chroma samples of the current block are classified into several groups, and a particular set of linear model parameters is derived for each group. The reconstructed luma samples of the current block are also classified to predict the associated chroma samples with the corresponding linear model. Second, we propose a multi-filter CCLM (MF-CCLM) technique, which allows the encoder to select the optimal down-sampling filter for the luma component with the 4:2:0 colour format. Third, we present a LM-angular prediction (LAP) method, which synthesizes the angular intra-prediction and the MM-CCLM intra-prediction into a new chroma intra coding mode. Simulation results show that 0.55%, 4.66% and 5.08% BD rate savings in average on Y, Cb and Cr components respectively, are achieved for All Intra (AI) configurations with the proposed three methods. MM-CCLM and MF-CCLM have been adopted into the JEM by JVET.


Domain Adaptive Semantic Segmentation Through Photorealistic Enhancement of Video Game

Proceedings of IEEE International Conference on Consumer Electronics(ICCE)


Optimal Stopping Theory-Enabled VVC Intra Prediction with Texture

Proceedings 2022 7th International Conference on Communication, Image and Signal Processing, CCISP 2022


The 7th International Forum on Advanced Technologies 2021 (IFAT2021)


Reference Frame Generation Algorithm using Dynamical Learning PredNet for VVC

Proceedings of IEEE International Conference on Consumer Electronics (ICCE)


Edge Computing for Video Analytics in the Internet of Vehicles with Blockchain

the 10th ACM International Symposium on Design and Analysis of Intelligent Vehicular Networks and Applications (DIVANet20)


An Adaptive Selection Method of Screen Content Coding Tools for Educational Video System

The 6th International Forum on Advanced Technologies 2020 (IFAT2020)


Low Bitrate VVC-based Drone Video Coding System


Input Bit Reduction for a Low Cost Neural ODE


Machine Learning based Underwater Depth Estimation


Bitrate Fluctuation Control Method for VVC-based Drone Video Coding System

Proceedings of RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing(NCSP'20)


CenterNet based Object Detection System for 360-degree Panorama Video System


GAN-based Color Correction for Underwater Object Detection


Proposal-Aware Visual Saliency Detection with Semantic Attention

International Conference on Intelligence Science and Big Data Engineering (IScIDE 2019)


Improvement of Cross Component Prediction by Multiple Liner Prediction for HEVC

Proceedings of International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC2019)


Fast Object Detection Algorithm using Encoded Video Information

IEEE CASS Shanghai and Shikoku Chapters Joint Workshop on Circuits and Systems (SSJW'18)

本論文は，低消費電力オブジェクト認識システムにおける消費電力削減を目的とした符号化済み情報を用いたオブジェクト検出アルゴリズムを提案した．認識フレームレートを半分にし，動き情報と差分情報を用いて連続のフレームにある冗長な認識処理を割出し，計算量を大幅に削減した．提案手法を実装しシミュレーションした結果，従来手法に比べ50%∼78%の演算量削減を実現した．


QP Adaptation Algorithm for Low Complexity HEVC based on a CNN-Generated Header Bits Map

Proceedings of IEEE 8th International Conference of Consumer Electronics in Berlin (ICCE-Berlin)

本論文は，HEVCにおけるヘッダビットマップを用いた低演算量QP調整アルゴリズムを提案した．検証結果からフレームの領域により生成ビットの偏りがあることが判明したため，CNNによる生成ビットマップを作成し，これを用いた高速モード選択アルゴリズムを提案した．提案手法を参照ソフトウェアHM16.7に実装しシミュレーションした結果，従来手法に比べ画質の劣化がほとんどなく，平均26%の演算量削減を実現した．


Multi-line Intra Prediction for Inter-Layer Reference in SHVC

Proceedings of Taiwan and Japan Conference on Circuits and Systems (TJCAS2018)

本論文は，SHVCのインターレイヤ符号化における複数ライン画素を用いた画面内符号化アルゴリズムを提案した．従来法で使用される参照画素を1ラインから2ラインに拡張し，予測用データを増やし，2ラインの画素データを活用する予測アルゴリズムを提案した．提案手法を実装しシミュレーションした結果，平均1.2%の符号化効率向上を実現した．


Fast PU Size Decision Algorithm Using RD-Cost and Depth Dispersion for Depth Intra Coding of 3D-HEVC

本論文は，3D-HEVCの画面内符号化におけるRD-COSTと深度分散を用いたPUサイズ決定アルゴリズムを提案した．最も可能性の高いモードを高速探索し，ある程度候補を限定した後に，詳細な検索を行うアルゴリズムを提案した．提案手法を実装しシミュレーションした結果，最大41%の演算量削減を実現した．


Efficient Object Detection Algorithm using Encoded Video Information

本論文は，小型カメラに使用される低消費電力オブジェクト認識システムにおける消費電力削減を目的とした符号化済み情報を用いたオブジェクト検出アルゴリズムを提案した．認識フレームレートを半分にし，更に連続のフレームに冗長な認識処理を割出し，計算量を大幅に削減した．提案手法を実装しシミュレーションした結果，従来手法に比べ50%∼78%の演算量削減を実現した．


Learning Library Extension for Sea Cucumber Recognition using GANs

Proceedings of International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC2018)

本論文は，ナマコ養殖における水中自動認識を実現するために学習用ライブラリを構築する手法を提案した．CNNの学習処理に用いる学習データが不足しているため，水中ロボットによるデータ採集を行い，既存のデータを用いてGANsによるデータ生成を行い，大規模な学習用ライブラリを構築した．提案手法を実装しシミュレーションした結果，82%の認識率を実現した．


Fast Object Detection System Based On The Embedded Information In The Bitstream

本論文は，将来の小型監視カメラに使用される低消費電力オブジェクト認識システムにおける消費電力削減を目的としたビットストリーム情報を用いた高速オブジェクト認識システムを提案した．提案手法は，連続のフレームに冗長な認識処理を割出し，無駄な計算量を大幅に削減する．提案手法を実装しシミュレーションした結果，従来手法に比べ50%∼78%の演算量削減を実現した．


Low-Complexity Intra Coding Algorithm Based on Convolutional Neural Network for HEVC

Proceedings of 2018 International Conference on Information and Computer Technologies (ICICT2018)

本論文は，HEVCにおけるCNNを用いた低演算量画面内符号化アルゴリズムを提案した．従来，画面内符号化モード決定手法において周辺の画素をCNNに入力する方法があったが，本論文は4つ並列に入力する構造を提案した．提案手法を実装しシミュレーションした結果，従来手法に比べ画質の劣化がほとんどなく，平均67%の高速処理を実現した．


Multi-Input CNN-based Low-Complexity Intra Coding Algorithm for HEVC

Proceedings of 4th International Forum on Advanced Technologies (IFAT2018)

本論文は，HEVCにおける複数入力CNNを用いた低演算量画面内符号化アルゴリズムを提案した．従来の画面内符号化モード決定手法では周辺画素を使用するが，CNNに入力される単一画素データを4つ並列に入力する構造を提案した．提案手法を実装しシミュレーションした結果，従来手法に比べ画質の劣化がほとんどなく，平均73%の高速処理を実現した．


Efficient Intra Prediction Based on Adaptive Downsampling Signal for Parallel HEVC Encoding

Proceedings of IEEE International Conference on Consumer Electronics(ICCE2018)

本論文は，並列処理HEVCにおける適応的ダウンサンプリングを用いた高効率画面内符号化アルゴリズムを提案した．符号化対象CUの画素に対しダウンサイジング処理を施し，新規の符号化順序と符号化方式を提案した．提案手法を参照ソフトウェアHM16.1に実装しシミュレーションした結果，従来手法に比べ27%の演算量削減を実現した．


Hardware-oriented Low Complexity Motion Estimation for HEVC

本論文は，HEVCのハードウェア実装における低演算量動き探索アルゴリズムを提案する．空間領域と時間領域の動きベクトルの相関性を評価し，新規の探索中心予測アルゴリズムを提案し，それを用いた探索範囲選択アルゴリズムを提案した．提案手法を参照ソフトウェアHM16.7に実装しシミュレーションした結果，従来手法に比べ80%の高速符号化性能を実現した．


Early Mode Selection of High Resolution for HEVC Base on Bits-Mapping

本論文は，HEVCにおけるビットマップを用いた高解像度用高速モード選択アルゴリズムを提案した．検証結果からフレームの領域により生成ビットの偏りがあるため，この特徴を利用しフレームを8領域に分割し，生成するビットマップを予測し，これを用いた高速モード選択アルゴリズムを提案した．提案手法を参照ソフトウェアHM15.0に実装しシミュレーションした結果，従来手法に比べ画質の劣化がほとんどなく，平均50%の演算量削減を実現した．


Pixel-based Fast CU Depth Decision Algorithm with Edge Strength for HEVC

本論文は，HEVCにおけるエッジ強度による高速CU決定アルゴリズムを提案した．ソベルフィルタを用いてエッジ強度を評価し，エッジの強さによりCUの深度を決定するアルゴリズムを提案した．提案手法を参照ソフトウェアHM10.0に実装しシミュレーションした結果，従来手法に比べ画質の劣化がほとんどなく，わずかなビットレートの上昇で高速なCU決定を実現した．


A Coding Efficiency Improvement Algorithm for Future Video Coding

IFIP International Federation for Information Processing 2017

本論文は，現在の符号化標準HEVCをベースとし，画面間予測に対して探索中心と探索範囲を改良した次世代動画像符号化のための高効率符号化アルゴリズムを提案した．まず，符号化中のCUの周辺動きベクトル情報を用いて高精度の動き探索中心決定アルゴリズムを提案し，更にその動きベクトル情報を用いて探索範囲を削減するアルゴリズムを提案した．提案アルゴリズムを実装し，シミュレーションした結果により，平均5.49%の符号化効率向上を実現した．


Coding Efficiency Improvement Algorithm for Inter-Layer Reference Prediction in SHVC

Proceedings of International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC2017)

本論文は，SHVCのインター符号化における高効率符号化アルゴリズムを提案した．SHVCのインターレイヤ符号化においてベースレイヤ情報をアップサンプリングする際のフィルタ処理を改良し，検証結果が優れたフィルタ2種を追加した．提案手法を参照ソフトウェアSHM11.0に実装しシミュレーションした結果，従来手法に比べ平均2%の符号化効率向上を実現した．


Fast CU Depth Decision Algorithm Using Depth-Map for 3D-HEVC

本論文は，3D-HEVCにおける深度マップを用いた高速CU決定アルゴリズムを提案する．深度マップに画像領域を3つに分割し，近いリージョンと遠いリージョンには，異なるCUで符号化する．遠いリージョンには小さい深度，近いリージョンには大きい深度が適応的に割当てるアルゴリズムを提案した．提案手法を実装しシミュレーションした結果，15%の演算量削減を実現した．


Training Library Generation for Automatic Sea Cucumber Recognition

本論文は，水産業界の自動化を目的としたナマコ養殖における自動認識を実現するために学習用ライブラリを構築した．ナマコを自動認識するためにCNNの学習処理に用いる学習データが不足しているため，水中ロボットによるデータ採集を行い，データ加工し，学習ライブラリを構築した．提案手法を実装しシミュレーションした結果，76%の認識率を実現した．


Early Depth Determination Algorithm for Enhancement Layer Intra Coding of SHVC

Proceedings of IEEE International Technical Conference TENCON 2016

本論文は，SHVCのエンハンスメントレイヤにおける画面内符号化の早期深度決定アルゴリズムを提案した．SHVCのインターレイヤ符号化のレイヤ間のRDコストの相関性を検証し，冗長演算を削除する深度決定アルゴリズムを提案した．提案手法を参照ソフトウェアSHM6.0に実装しシミュレーションした結果，従来手法に比べ画質の劣化がほとんどなく，平均48%の高速処理を実現した．


Adaptive Mode Selection for Low Complexity Enhancement Layer Encoding of SHVC

Proceedings of International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC2016)

本論文は，SHVCのエンハンスメントレイヤにおける低演算量符号化アルゴリズムを提案した．SHVCのインターレイヤ符号化の各モード使用率と特徴を検証し，冗長演算を削除するアルゴリズムを提案した．提案手法を参照ソフトウェアSHM6.0に実装しシミュレーションした結果，従来手法に比べ画質の劣化がほとんどなく，平均20%の高速処理を実現した．


Hardware Oriented Early CU Splitting Algorithm by Coding Unit Feature Analysis for HEVC

本論文は，HEVCにおける符号化ユニットの特徴に基づいた高速CU分割アルゴリズムを提案する．CU内のエッジ成分量を評価し，エッジ強度を計算し，エッジ強度によるCU分割アルゴリズムを提案した．提案手法を用いた場合，全てのモード決定処理が提案手法のみで完成し，ハードウェア実装において劇的に高速処理が可能となる．


An Adaptive Search Range Selection Algorithm for HEVC

本論文は，HEVCにおける適応的動き探索範囲の選択アルゴリズムを提案する．空間領域と時間領域の動きベクトルの相関性を評価し，高精度の探索中心予測アルゴリズムを提案し，探索中心決定法を用いた探索範囲選択アルゴリズムを提案した．提案手法を参照ソフトウェアHM16.7に実装しシミュレーションした結果，従来手法に比べ76%の高速符号化性能を実現した．


Energy Efficient Streaming for Smartphones by Video Adaptation and Backlight Control

The Proceedings of the 2nd International Conference on Intelligent Green Building and Smart Grid (IGBSG)

本論文は，携帯端末のビデオ配信における消費電力増大の問題に対し，従来のCPUの負荷削減手法と異なり，ネットワークの通信状況によるスケーラブルビデオの配信手法を提案した．また，有効なバックライトの調整手法を用いることにより，さらに消費電力を削減できる．提案手法のシステムを構築し，検証した結果およそ20%∼30%の消費電力の削減を実現できた．


Reference Frame Selection Algorithm of HEVC Encoder for Low Power Video Device

Proceedings of 2nd International Conference on Intelligent Green Building and Smart Grid (IGBSG 2016)

本論文は，携帯端末の復号器において低消費電力を目的としたHEVC符号化器の参照フレーム選択アルゴリズムを提案した．本提案は，符号器側で複合器側の消費電力の高いフレームメモリのアクセス部分の消費電力を削減するために，フレーム選択アルゴリズムを改良することにより消費電力削減を図った．提案手法を実装しシミュレーションした結果，従来手法に比べ平均40%の削減を実現した．


Fast CU Size Decision for Intra Coding Algorithm in SHVC

Proceedings of 2nd International Forum on Advanced Technologies (IFAT2016)

本論文は，SHVCのエンハンスメントレイヤにおける低演算量画面内符号化アルゴリズムを提案した．SHVCのインターレイヤ符号化の各モード使用率と特徴を検証し，RDコストによる冗長演算を削除するアルゴリズムを提案した．提案手法を参照ソフトウェアSHM6.0に実装しシミュレーションした結果，従来手法に比べ画質の劣化がほとんどなく，平均60%の高速処理を実現した．


Downsampled Information Based Low Complexity Intra Coding for HEVC

本論文は，HEVCの画面内符号化において画素間の空間相関性を利用した新規符号化方式を提案した．符号化対象CUの画素に対しダウンサイジング処理を施し，新規の符号化順序と符号化方式を提案し，様々な情報を用いて演算量の削減を図った．提案手法を参照ソフトウェアJM12.1に実装しシミュレーションした結果，従来手法に比べ平均18.43%の符号化効率向上を実現した．


Low-Complexity Intra Coding Algorithm in Enhancement Layer for SHVC

Proceedings of 2016 IEEE International Conference on Consumer Electronics (ICCE)

本論文は，SHVCのエンハンスメントレイヤにおける低演算量画面内符号化アルゴリズムを提案した．SHVCのインターレイヤ符号化の各モード使用率と特徴を検証し，冗長演算を削除するアルゴリズムを提案した．提案手法を参照ソフトウェアSHM6.0に実装しシミュレーションした結果，従来手法に比べ画質の劣化がほとんどなく，平均60%の高速処理を実現した．


High efficiency CU depth decision algorithm for high resolution application of HEVC

Proceedings of IEEE International Technical Conference TENCON 2015

本論文は，高解像度の応用を目的にしたHEVCのCU深度決定アルゴリズムを提案した．符号化対象CUの周辺動きベクトルの分布を調査し，符号化コストと共にCU動きベクトルを予測し，それを用いた高速符号化手法を提案した．提案手法を参照ソフトウェアJM12.1に実装しシミュレーションした結果，従来手法に比べ42%の高速符号化を実現した．


High Efficiency Intra Coding Extension for HEVC/H.265

IEEE CASS Shikoku and Malaysia Chapters Joint Seminar

本論文は，HEVCの画面内符号化における新規符号化モードを提案した．符号化対象CUの画素に対しダウンサイジング処理を施し，新規の符号化順序と符号化方式を提案し，様々な情報を用いて演算量の削減を図った．提案手法を参照ソフトウェアJM12.1に実装しシミュレーションした結果，従来手法に比べ大幅の符号化効率向上を実現した．


Small Area VLSI Architecture for Deblocking Filter of HEVC

Proceedings of IEEE International Conference on Consumer Electronics Berlin(ICCE-Berlin 2015)

本論文は，HEVCのディブロッキングフィルタ処理の効率的ハードウェア処理順序を提案し，小面積かつ高効率なハードウェアアーキテクチャを提案した．HEVCのディブロッキング処理順序を分析し，ハードウェア処理に不向きであることを指摘し，効率的な符号化順序とパイプライン処理手順を提案したアーキテクチャを示した．提案手法をハードウェアに実装しシミュレーションした結果，従来手法に比べ小面積で実装可能であることを示した．


Segmental Downsampling Intra Coding Based on Spatial Locality for HEVC

本論文は，HEVCの画面内符号化において画素間の空間相関性を利用した新規符号化方式を提案した．符号化対象CUの画素に対しダウンサイジング処理を施し，新規の符号化順序と符号化方式を提案し，様々な情報を用いて演算量の削減も図った．提案手法を参照ソフトウェアJM12.1に実装しシミュレーションした結果，従来手法に比べ平均18.43%の符号化効率向上を実現した．


Spatial Locality Based Parallel Scheme for Intra Coding of HEVC

Tenth International Conference on Innovative Computing, Information and Control (ICICIC2015)

本論文は，HEVCの画面内符号化において画素間の空間相関性を利用した新規符号化方式を提案した．符号化対象CUの画素に対し隣接4画素を4ブロックに分け，符号化済ブロックの情報を用いて残りのブロックを符号化する手法を提案し，符号化する際の参照ブロックの選択法と効率的なフィルタを提案した．提案手法を参照ソフトウェアJM12.1に実装しシミュレーションした結果，従来手法に比べ平均10.8%の符号化効率向上を実現した．


Design and Implementation of Various File Deduplication Schemes on Storage Devices

11th EAI International Conference on Heterogeneous Networking for Quality, Reliability, Security and Robustness (QShine 2015)


Efficient Prediction Motion Vector Candidate Selection Algorithm for HEVC

The 30th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2015)

本論文は，HEVCの動き探索中心を決定する際に効率的に行うアルゴリズムを提案している．符号化CUの周辺CUの符号化済動きベクトルを用いて分散を評価し，符号化CUの動きベクトルを精確に予測し，探索中心を効率的に決定するアルゴリズムを提案した．提案手法を参照ソフトウェアJM9に実装しシミュレーションした結果，従来手法に比べ平均3.5%のビットレート削減を実現した．


Original Pixel Based Parallel Algorithm for Intra Prediction of HEVC

本論文は，HEVCの画面内符号化において従来の符号化済画素を用いたモード決定法の代わりに，原画素を用いた新規の符号化モード選択方式を提案した．原画素を用いた場合のCUサイズへの影響，シーケンス毎の差異，量子化係数QPによる差異を検証し，最適なモード選択手法を提案した．提案手法を参照ソフトウェアJM12.1に実装しシミュレーションした結果，画質劣化はほとんどなく並列処理が可能となった．


Spatial Locality Based Supplemental Modes for Intra Prediction of HEVC

Proceedings of IEEE International Conference on Consumer Electronics(ICCE-Taiwan 2015)

本論文は，HEVCの画面内符号化において画素間の空間相関性を利用した新規符号化方式を提案した．符号化対象CUの画素に対し隣接4画素を4ブロックに分け，符号化済ブロックの情報を用いて残りのブロックを符号化する手法を提案し，使用する効率的なフィルタを提案した．提案手法を参照ソフトウェアJM12.1に実装しシミュレーションした結果，従来手法に比べ平均8.4%の符号化効率向上を実現した．


Merge Prediction Algorithm for Adaptive Parallel Improvement of High Efficiency Video Coding

本論文は，GPUなど並列処理性能が高く要求される環境においてHEVCを実装する場合に，マージモードのアルゴリズムを改良することにより，並列処理性能を高めるアルゴリズムを提案した．処理単位CTUに対し，PUの動きベクトルをCTU周辺の動きベクトルより予測し，PU間の相関性を無くし，符号化効率への影響を最小限にする手法を提案した．提案手法を参照ソフトウェアHM12.0に実装しシミュレーションした結果，従来手法に比べわずか0.1%未満の符号化効率低下まで抑え，並列処理を可能にした．


Efficient Intra Coding for HEVC Based on Spatial Locality

Proceedings of International Forum on Advanced Technologies (IFAT2015)

本論文は，HEVCの画面内符号化における画素間の空間相関性を利用した新規符号化方式を提案した．符号化対象CUの画素に対し隣接4画素を4ブロックに分け，左上ブロックのみを符号化し，符号化済ブロックの情報を用いて残りのブロックを符号化した．提案手法を参照ソフトウェアJM12.1に実装しシミュレーションした結果，従来手法に比べ平均6%の符号化効率向上を実現した．


High Efficiency Inter CU Size Prediction Algorithm for HEVC

本論文は，HEVCの画面間符号化において高効率CUサイズ決定アルゴリズムを提案した．符号化対象CUの周辺の動きベクトルを利用し，現在のCUに利用可能とする信頼度を評価し，その信頼度とMADを用いて総合的にCUサイズを決定するアルゴリズムを提案した．提案手法を参照ソフトウェアJM8に実装しシミュレーションした結果，従来手法に比べ平均42%の演算量の削減を実現した．


Received Signal Strength Indication(RSSI) Prediction-based Adaptive H.264/SVC Video Service on Smartphone

Proceedings of International Forum on Advanced Technologies

本論文は，携帯端末における受信信号強度によるH.264/SVC適応的ビデオ配信手法を提案した．携帯端末におけるビデオ通信の消費電力増大の問題に対し，通信状況を計測することにより低帯域の場合に適応的にビデオ配信量を抑えるアルゴリズムを提案した．提案手法を実装しシミュレーションを行った結果，提案手法は従来の手法に比べ平均10%の消費電力削減を実現できる．


Edge Information Based Fast Selection Algorithm for Intra Prediction of HEVC

Proceedings of IEEE Asia Pacific Conference on Circuits & Systems(APCCAS2014)

New features of intra prediction in HEVC improves coding ef ciency, meanwhile, brings high computational complexity. This paper presents a fast algorithm for intra prediction of HEVC. An edge information based fast image preprocessing stage is designed. Based on the result of edge detection, reasonable PU size is decided ef ciently. Intra prediction mode selection optimization based on edge information also helps to achieve the goal of computational complexity reduction. Compared to the original HEVC, the result of the complexity reduction is over 27%, in the meantime, the increased BD-Rate and declining BD-PSNR is almost negligible.


AMVP Prediction Algorithm for Adaptive Parallel Improvement of HEVC

HEVC has been improved greatly including some parallel processing tools to achieve fast implementation on multi-core or many-core platforms. However, CU level parallel processing is still a challenging issue. In this paper, the relation among spatial motion candidates is analyzed firstly. Then, a parallelism spatial candidate list generation algorithm is proposed on the basis of the strong correlations among current prediction unit (PU), surrounding PUs and temporal correlated PUs. By evaluating the reliability of the motion vectors, the parallel granularity can be controlled adaptively. Experimental results show that the presented algorithm can achieve friendly parallel processing with only 0.26% BD-rate loss, based on the test model HM12.0.


Temporal Prediction Improvement for Parallel Processing of HEVC

HEVC is based on a block-based hybrid coding architecture. Parallel processing is important tool to accelerate both on the encoder and decoder side. Advanced motion vector prediction (AMVP) is an efficient inter prediction tool in HEVC. However, neighbor block dependence in AMVP coding is major barrier for parallel processing. In this work, focusing on the parallel processing ability in HEVC, a parallel temporal prediction algorithm is proposed that make the encoder decide the temporal candidate once in a larger coding unit for all the sub-units. Experimental results demonstrate that the proposed algorithm realize parallel temporal prediction candidate with only 0.11% BD-rate loss, compared with the reference software model.


Hardware Architecture of the Fast Mode Decision Algorithm for H.265/HEVC

Proceedings of International Conference of Image Processing (ICIP2014)

In this paper, a course of low complexity Fast Mode Decision (FMD) algorithms as well as the corresponding hardware architecture is presented. Firstly, the depth information of co-located block from previous frame is used to predict the size of current block. Then, for a certain sized block, the inter prediction residual is analyzed to determine whether to terminate current check or to skip some unnecessary modes and split to smaller size. Finally, the corresponding hardware architecture is proposed based on state machine mechanism. Simulation results show that these proposed algorithms reduce the encoding time by 40.8~ 70.3%, without incurring any noticeable performance degradation. Hardware synthesis results demonstrate that the proposed architecture achieves a max frequency of about 193 MHz.


Complexity Reduction Algorithm for Intra Prediction of HEVC

The 29th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2014)

The novel HEVC achieved higher coding efficiency than traditional video coding standards at the expense of increased encoding complexity. Compared with traditional intra prediction tools, high coding complexity comes from both of the increased block size and enhanced coding modes. In the proposed algorithm, a novel pixel gradient detection algorithm is proposed to reduce the candidate modes to be calculated with SATD. The proposed algorithm determines the mode with high probability in intra prediction using the difference of the adjacent pixels. As a result the proposed algorithm achieved a reduction of approximately 35% of the SATD calculation with almost no quality loss.


High Efficiency Video Coding (HEVC) Motion Estimation Parallel Algorithms on GPU

Proceedings of IEEE International Conference on Consumer Electronics - Taiwan (2014 ICCE-Taiwan)

Exhausted motion estimation in HEVC with variable block sizes is the bottleneck for real time encoding. Previous works show that CTU-based parallel processing will induce much coding efficiency loss. In this paper, focusing on the parallel processing in one CTU, efficient parallel algorithms are presented to accelerate integer motion estimation (IME) and fractional motion estimation (FME) on GPU, including multistep composite method for IME and eliminating redundancies for FME. Experimental results show that the highest time reduction can reach up to about 52.38% compared with the non-parallel baseline implementation.


Edge Detector Based Fast Level Decision Algorithm for Intra Prediction of HEVC

Proceedings of International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP'14)

The Research Institute of Signal Processing Japan

HEVC achieves significant coding efficiency than previous video coding standards. In intra prediction of HEVC, prediction unit sizes from 4x4 to 64x64 are employed, defined as level 1 ∼ level 5, to achieve higher coding efficiency. Nevertheless, it is at the expense of high computation complexity. This paper proposed a fast algorithm for intra prediction of HEVC that can efficiently select the level on the base of roberts-cross edge detector. It is composed mainly of a bottom-up level decision method and an efficient decision flow on the grounds of authentic image feature. The results of the proposed algorithm will achieve enormously computation complexity reduction comparing to the original HEVC.


Hardware architecture of the fast mode decision algorithm for H.265/HEVC

2014 IEEE International Conference on Image Processing, ICIP 2014


Hardware-oriented Fast Mode Decision Algorithm for Intra Prediction in HEVC

Proceedings of Picture Coding Symposium (PCS2013)

In this paper, a hardware-oriented low complexity fast intra prediction algorithm is presented. The proposed algorithm adopts a fast Discrete Cross Differences (DCD) to detect the dominant direction of the coding unit. Based on DCD information, only a subset of the 35 candidate modes are selected for the rough mode decision process. Moreover, four simple but efficient early termination strategies are proposed to terminate the RDO process properly. Complexity analysis results demonstrate that the proposed algorithm can be easily implemented on hardware platform with fewer resources consumed. Simulation results show that the proposed algorithm reduce the encoding time by 66% on average, requiring bit-rate increase about 3.9% and PSNR decrease about 0.18dB, respectively.


Low Complexity Algorithm for Sub-Pixel Motion Estimation of HEVC

Proceedings of IEEE International Conference on Signal Processing, Communications and Computing (ICSPCC 2013)

The next generation video coding standard HEVC introduced many efficient algorithms to enhance the coding efficiency. However, the computational complexity of motion estimation is still the bottleneck for its implementation. In this paper, we propose a complexity reduction algorithm for fractional-pixel motion estimation (FPME). Firstly, a fast termination algorithm is proposed to fast terminate FPME using a threshold. Next, the proposed algorithm designs several original search orders and search patterns for 1/2 pixel and 1/4 pixel motion estimation, respectively. These proposed patterns are on the basis of the probability of each search point and its surrounding integer search points. Simulation results show that the proposed algorithm succeed in reduction of search point for up to 38% with almost no coding efficiency loss.


High-Performance Multiplierless Transform Architecture for HEVC

Proceeding of IEEE International Symposium on Circuits and Systems(ISCAS')

In this paper, a high-performance multiplierless VLSI architecture for the transform applied in the emerging HEVC is presented. The proposed architecture can support a variety of transform sizes from 4x4 to 32x32, and some simplification strategies are adopted during the implementation, such as reusing part of a larger sized transform structure reused by smaller ones, and turning multiplications by constant into shift and sum operations. Synthesis results on the FPGA platform indicate that the proposed design can double the throughput compared with previous work, with almost the same hardware cost. Moreover, synthesis results under 45nm technology show that it can support real-time processing of 4Kx2K (4096x2048, 30fps) video sequences.


Fast Motion Estimation for Spatial Scalability of H.264/SVC

Proceedings of International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP'13)

In this paper, we propose a fast algorithm for spatial scalability of H.264/SVC. First, verification is performed to confirm the redundancy of the previous motion estimation process of H.264/SVC. Then, based on the evaluation results we propose an improved algorithm that only focuses on the complexity reduction of enhancement layer. The proposed algorithm can decrease the computation complexity of the enhancement layer using the inter layer motion prediction. The proposed algorithm is evaluated using reference software JSVM. The simulation results show that the proposed algorithm can achieve over 66% computation complexity reduction comparing to the original JSVM algorithm.


Hardware-oriented fast mode decision algorithm for intra prediction in HEVC

2013 Picture Coding Symposium, PCS 2013 Proceedings


Computational Complexity Reduction Algorithm of Sub-Pixel Motion Estimation for HEVC

The 27th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2012)

The emerging standard of HEVC (High Efficiency Video Coding) is on the last stage for recommendation. However, the computational complexity of motion estimation is still the bottleneck for the implementation of HEVC. In this paper, we propose a complexity reduction algorithm for the fractional-pixel motion estimation. The proposed algorithm designs several original search patterns for 1/2 pixel and 1/4 pixel motion estimation. These proposed patterns are on the basis of the probability of each search point and its surrounding integer search points. Simulation results show that the proposed algorithm succeed in reduction of search point for up to 35% with almost no coding efficiency loss.


Motion Vector Management Architecture for 4K Resolution H.264/AVC Decoder

Proceedings of International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP'12)

The Research Institute of Signal Processing Japan

The computation complexity of H.264/AVC especially for 4K resolution applications is still the bottleneck for real-time processing. In this work, a motion vector management architecture that is in charge of the total motion vectors management and calculation is proposed. The proposed architecture can calculate the predicted motion vector, select the reference motion vectors for direct mode, and calculate the motion vectors for interlace decoding. The simulation result shows that the proposed architecture can be implemented by about 99k gates working at 200MHz.


Quadtree-based Adaptive Filter for Inter-layer Intra Prediction in H.264/SVC

Proceeding of International Conference on Embedded Systems and Intelligent Technology

In this paper, an adaptive wiener filtering method based on the quadtree structure is proposed in addition to the inter-layer intra prediction within H.264/SVC codec. The proposed method adaptively applies the filter to individual blocks of different sizes that can be represented by the quadtree structure. Moreover, based on analysis, the proposed filter is redesigned for several times to find out the optimized filter suiting for the block region where filtering operation is actually needed. Experimental results show that the average reduction of the bitrate and PSNR improvement for 8 video sequences are 7.14% and 1.218 dB without considering the bit cost of filter operation.


Fast Inter-layer Motion Estimation for Spatial Scalability of H.264/SVC

International Conference on Innovative Computing, Information and Control (ICICIC2011)

In this paper, we propose an improved low complexity algorithm for spatial scalability of H.264/SVC on the basis of the motions in the sequences. First, verification is performed to confirm the redundancy of the previous motion estimation process of H.264/SVC. Then, based on the evaluation results we propose an improved algorithm for our previous work that only focuses on the complexity reduction of enhancement layer. The proposed algorithm can decrease the computation complexity of the enhancement layer using the inter layer motion prediction. The simulation results show that the proposed algorithm can achieve over 95% computation complexity reduction comparing to the original JSVM algorithm.


Novel INTRA modes with Temporal-Spatial Prediction for H.264/AVC

2011 IEEE International Conference on Consumer Electronics - Berlin (ICCE-Berlin 2011)

This work proposes a novel INTRA coding algorithm that can achieve high coding efficiency using temporal-spatial prediction for H.264/AVC. The proposed prediction algorithm can compensate the weak point of individual usage of spatial or temporal prediction. Firstly, a new prediction block is selected in the temporal previous frame. Next, the selected block in the previous frame is used as the reference data to perform spatial prediction with the same reference direction as traditional INTRA modes. The simulation results show that the proposed new INTRA modes can achieve about 1dB improvement than the original H.264/AVC.


New prediction modes for parallel processing of H.264/AVC

Proceedings 2011 International Conference on Multimedia and Signal Processing, CMSP 2011


High performance binarizer for H.264/AVC CABAC

2011 International Conference on Electric Information and Control Engineering, ICEICE 2011 Proceedings


Keyframe Selection Method Based on the Motion Features of H.264

The 26th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2011)

In this paper, we propose a novel key-frame selection algorithm for video retrieval. Firstly, the video sequences are segmented into shots with the pixel features between consecutive frames. Then, based on the MV and MVD features of H.264, we notice that MV can reflect the displacement of objects in the frames and MVD can reflect the regularity of motion. Thus, the intensity of the motion can be reflected through MV and MVD features, and key-frames are selected with the greatest intensity of motion in each shot. The experimental results show that our proposed algorithm can weaken the influence of camera motion and select key-frames from video sequences effectively.


Fast Parallel Algorithm of H.264/AVC Deblocking Filter for GPU Implementation

Due to the improvement of the processing capability of graphics processing unit (GPU), it is considered as a powerful processing tool to realize fast implementation of H.264/AVC. In this work, we propose a fast parallel algorithm for deblocking filter (DF) in H.264/AVC on a computer unified device architecture (CUDA) platform that is proposed by NVIDIA GPUs. The proposed algorithm modifies the filtering process to realize parallel processing of all macroblocks in one frame. Simulation results show that this modification will not induce PSNR loss and it realized over 10 times fast processing of DF than that of using CPU only.


New Prediction Modes for Parallel Processing of H.264/AVC

Proceedings of International Conference on Multimedia and Signal Processing (CMSP'11)

This work proposes a novel parallel processing algorithm for H.264/AVC that is dedicated to GPU implementation. Firstly, the original pixel data is used in the rate-distortion optimization (RDO) process instead of the reconstructed pixel data to realize the complete MB-level parallel processing of INTRA coding. It can help to parallel encode all the MB in one frame in the same time on GPU. Next, a new temporal prediction concept is introduced in the traditional spatial prediction to compensate the weak point of individual usage of spatial or temporal prediction. The simulation results show that when using the original pixel in the RDO process it will induce slight PSNR loss. However, when the proposed new modes are introduced the RD-curve shows about 1dB improvement than the original H.264/AVC.


Motion Estimation Algorithm for Spatial Scalability in H.264/SVC

Proceedings of International Workshop on Nonlinear Circuits, Communication and Signal Processing (NCSP'11)

The Research Institute of Signal Processing Japan

In this paper, we propose an improved low complexity algorithm for spatial scalability of H.264/SVC on the basis of the motions in the sequences. First, verification is performed to confirm the redundancy of the previous motion estimation process of H.264/SVC. Then, based on the evaluation results we propose an improved algorithm for our previous work in which only focuses on the complexity reduction of enhancement layer. The proposed algorithm can decrease the computation complexity of the enhancement layer using the inter layer motion prediction. The simulation results show that the proposed algorithm can achieve over 95% complexity reduction comparing to the original JSVM. When it is compared with our previous works, 12% complexity reduction has been achieved.


Improved Inter-layer Intra Prediction for Scalable Video Coding

In this paper, a method based on the two dimensional Wiener filter is proposed in addition to inter-layer intra prediction in H.264/SVC. The performance of inter-layer intra prediction is limited due to the up-sampling operation and the coding noise of base layer. The Wiener filter can be used as an optimizing filter to enhance the prediction of enhancement. However, prediction errors of some pixels are increased by this filter operation. The proposed method applies the filter for each block of different size adaptively. Experimental results show that the reduction of bit rate and PSNR improvement for QCIF-CIF Akiyo sequences are 3.74% and 1.15dB without considering the bit cost of filter operation.


Novel Variable Search Range Selection Algorithm for H.264/SVC

In this paper, a novel variable search range selection algorithm is proposed for the H.264/SVC. The scalable extension of H.264/AVC achieves high scalability as well as high coding efficiency. However, the exhausted computation complexity becomes the implementation difficulty. In variable block size motion estimation, we find that motion estimation process has much redundancy. On the basis of this feature, we propose a novel variable search range algorithm that can significantly reduce the redundant search range. Simulation results show that the proposed method can achieve high computation complexity reduction with very slight PSNR loss.


Fast Parallel Algorithm of Motion Estimation for GPU Implementation

Due to the rapid growth of the processing capability of graphics processing unit (GPU), using GPU as a coprocessor to assist the CPU in computing massive data becomes essential. In this work, we propose a fast parallel algorithm for motion estimation (ME) process in H.264/AVC on a computer unified device architecture (CUDA) platform. The proposed algorithm performs the parallel calculation of the residuals and SAD. Simulation results show that with the assistance of GPU the processing time is about 2 times faster than that of using CPU only.


Fast Spiral Motion Estimation Algorithm for H.264/AVC

Variable block size and multiple reference frames are introduced in H.264/AVC. However, these new features induce significant implementation complexity increases. In this paper, fast spiral motion estimation (FSME) is proposed based on our previous spiral motion estimation (SME) algorithm and its architecture. When the sum of absolute differences (SAD) closes to the best search position, a convergent value of SAD is available. The proposed FSME reduces the search point candidates with the characteristic of SAD. Simulation results show that about 63% search points in motion estimation is realized by negligible video quality degradation.


Coding Efficient Improvement by Adaptive Search Center Definition

Proceedings of 28th Picture Coding Symposium (PCS2010)

In this paper, an efficient search center definition algorithm is proposed for H.264/AVC. H.264/AVC achieved high coding efficiency but the definition of the search center is not efficient in the case of significant motions. This work proposes some new search center candidates using spatial and temporal correlations of motion vectors to improve the coding efficiency. Simulation results show that the proposed search centers can achieve very much bit saving but induced high computation complexity. Additional complexity reduction algorithm is also introduced to improve the tradeoff between bit saving and implementation performance. This work realized a maximum bit saving of 19%.


Coding efficient improvement by adaptive search center definition


Low complexity inter-layer motion estimation algorithm for H.264/SVC

2010 World Automation Congress, WAC 2010


Real-time architecture for inter-layer prediction of H.264/SVC

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)


Motion Based Low Complexity Algorithm for Spatial Scalability of H.264/SVC

Proceedings of 2010 IEEE 17th International Conference on Image Processing (ICIP2010)

In this paper, we propose an improved low complexity algorithm for spatial scalability of H.264/SVC on the basis of the motions in the sequences. First, verification is performed to confirm the redundancy of the previous motion estimation process of H.264/SVC. Then, based on the evaluation results we propose an improved algorithm for our previous work that only focuses on the complexity reduction of enhancement layer. The simulation results show that the proposed algorithm can achieve over 90% computation complexity reduction comparing to the original JSVM algorithm. When it is compared with previous works, 10% complexity reduction and over 27% time saving have been achieved.


Real-Time Architecture for Inter-layer Prediction of H.264/SVC

Proceedings of Pacific-Rim Conference on Multimedia (PCM2010)

In this paper, an efficient architecture for Inter-layer prediction of H.264/SVC is proposed. In the proposed architecture, the motion vector prediction mode is not concerned due to its limited coding efficiency. Using an efficient mode selection algorithm that is proposed by our previous work, the complexity of residual prediction is significantly reduced. Therefore, to realize real-time processing with low cost hardware, the proposed architecture makes use of a single-core coding engine. Using this coding core, the macroblock encoding is performed for base layer and enhancement layer alternatively. The proposed up-sampling module is described by Verilog-HDL and synthesis results show that the gate counts are 16,121 and the maximum working frequency is 141MHz.


Low Complexity Inter-Layer Motion Estimation Algorithm for H.264/SVC

Proceedings of World Automation Congress (WAC2010)

In this paper, we propose an improved low complexity algorithm on the basis of motions in the sequences for H.264/SVC. First, verification is performed to confirm the redundancy of the previous motion estimation process of H.264/SVC. Then, based on the evaluation results we propose an improved algorithm for our previous work that focuses on the complexity reduction of enhancement layer only. Furthermore, the proposed algorithm can decrease the computation complexity of the base layer using the feature of the hierarchical structure. The simulation results show that the proposed algorithm can achieve over 90% computation complexity reduction comparing to the original JSVM algorithm.


Complexity Reduction Algorithm for Enhancement Layer of H.264/SVC

The Third International Symposium on Intelligent Informatics (ISII2010)

The inter-layer prediction of H.264/SVC can help to improve the coding efficiency as well as the computation complexity. This paper presents a low complexity algorithm for inter-layer prediction. Proposed algorithm focuses on the reduction of the candidate modes by making use of the correlations of the encoding cost between the base layer and enhancement layers. For macroblock with collocated macroblock coded by INTRA or INTER type, two algorithm are proposed, respectively. Both algorithm efficiently decrease the redundant candidate modes by estimating from the base layer coding information. The experiment results show that proposed algorithm can significantly reduce redundant computation complexity with almost no coding efficiency loss.


Efficient Deblocking Filter Architecture for High-Resolution Applications of H.264/AVC

This paper presents an efficient deblocking-filter architecture for high-resolution applications of H.264/AVC. In this work, we try to reduce the redundant filtering process in the case of high-resolution applications with low quantization parameter (QP). We early terminate filtering process to cut down power consumption by detecting the case when all the boundary strength (BS) of 4×4 blocks for one macroblock are zero. An efficient architecture that can realize these two proposals is also proposed. Simulation results show that there is a maximum 90% reduction in the filtering calculations and 87% of BS calculation. Low power implementation can be realized with the proposed architecture.


Four-bins Paralleled Architecture for CABAC in H.264/AVC

Proceedings of International Workshop on Nonlinear Circuits and Signal Processing (NCSP'10)

The Research Institute of Signal Processing Japan

In H.264/AVC, the entropy encode tool used in main and high profiles is context-based adaptive binary arithmetic coding (CABAC) which can achieve high coding efficiency. In this work, a high encoding throughput is achieved, but it only benefits from running at the much higher frequency that is not typical implementation for current applications. Another work proposed some acceleration architectures to encode 3 or 4 in one cycle. However in this architecture, only the bypass encoded which account for about 15% of the total are accelerated. This paper proposes an efficient pipelined architecture with the encoding ability of 4 per cycle supporting both the bypass mode and the context-adaptive mode in CABAC.


Low Complexity Algorithm for Inter-layer Residual Prediction of H.264/SVC

IEEE International Conference on Image Processing (ICIP2009)

In this paper, we propose an improved low complexity algorithm for spatial scalability of H.264/SVC on the basis of the motions in the sequences. First, verification is performed to confirm the redundancy of the previous motion estimation process of H.264/SVC. Then, based on the evaluation results we propose an improved algorithm for our previous work that only focuses on the complexity reduction of enhancement layer. The simulation results show that the proposed algorithm can achieve over 90% computation complexity reduction comparing to the original JSVM algorithm. When it is compared with some other previous works, 10% complexity reduction and over 27% time saving have been achieved.


Mode Selection Method for Hierarchical B-picture of H.264/SVC

The Second International Symposium on Intelligent Informatics (ISII2009)

In this paper, a novel mode selection method for hierarchical B-picture of H.264/SVC is proposed. However, the exhausted computation complexity becomes the implementation difficulty. Observing the correlation in multi-layer structures, we find that the mode selection process has much redundancy. In particular, the redundant modes have essential relation with the encoding layers. On the basis of this feature, we propose a novel mode selection method that can significantly reduce the redundant candidate modes. Simulation results show that the proposed method can achieve high computation complexity with very slight PSNR loss.


Improvement of Motion Estimation with Modified Search Center and Search Range for H.264/SVC

The 24th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2009)

In this paper, we propose a novel optimized motion estimation algorithm with a modified search center for spatial scalability when using inter-layer motion prediction of H.264/SVC. Firstly, up-sampled motion vector of base layer is evaluated to find the relation with the enhancement layer. Based on the results, we use the motion vector of the base layer to estimate the optimal search center for enhancement layer. Then, based on the modified search center we adaptively control the search range to reduce the redundant motion estimation. The simulation results show that the proposed algorithm can achieve over 80% computation complexity reduction of total motion estimation.


An Efficient Architecture for Spiral-Type Motion Estimation for H.264/AVC

In this paper, an efficient architecture for spiral-type ME is proposed. First, we propose a hardware friendly spiral search order. Then, an improved PE architecture for ME is proposed to achieve the proposed search order. The improved PE enables the shift of the reference pixel data to top, bottom, right, and left by 4 input and output ports. Moreover, the parallel calculation architecture to calculate all block size with the SAD of 4x4 is introduced in the proposed architecture. As a result of hardware implementation, the hardware cost is about 145K gates. Maximum clock frequency is 134MHz in the case of FPGA (Xilinx Vertex5) implementation.


Spatial-Temporal Correlation Based Mode Decision Algorithm for H.264/AVC

The 13th IEEE International Symposium on Consumer Electronics (ISCE2009)

In this work, a fast mode decision algorithm for H.264/AVC is proposed. In order to reduce the computation complexity of the encoder of H.264/AVC, the proposed algorithm efficiently reduces the candidate modes. The proposed algorithm includes an early skip mode decision method and an adaptive rate distortion cost threshold for early INTER mode decision. A complexity reduction algorithm for INTRA modes which uses the information during INTER mode selection is also proposed. The experimental results show that compared with full-search algorithm the proposed algorithm can achieve up to 70-89% speed up with very slight PSNR loss.


Efficient Mode Selection Algorithm for Inter-Layer Residual Prediction of H.264/SVC

The 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2009)

Institute of Electronics, Information and Communication Engineers

This paper presents an efficient mode selection algorithm to reduce the computational complexity when using inter-layer residual prediction of H.264/SVC. Proposed two steps algorithm focuses on the complexity reduction of the inter-layer residual prediction. In the first step, the ordinary routine of rate-distortion optimization (RDO) for H.264/AVC is performed and a temporary best mode (TBM) is selected. Then, in the second step the TBM is used to determine the redundant coding modes from all the candidate modes. The experiment results show that the proposed algorithm can considerably reduce redundant computation complexity with almost no coding efficiency loss.


Motion Based Frame Memory Access Reduction Method for H.264/AVC

Proceedings of International Workshop on Nonlinear Circuits and Signal Processing (NCSP'09)

The Research Institute of Signal Processing Japan

In this paper, considering the features of frame memory access patterns in RDO process, we introduce a novel memory access reduction method by estimating the motion information. The traditional necessary pixels data for the encoding of one macroblock in reference frame is 49 macroblocks. In this work, the search center is estimated by adjacent motion vectors. In the proposed method pixels data of only 9 or 25 macroblocks are adaptively used as reference data for motion estimation. Simulation results show that proposed method can realize about 50∼75% memory access reduction with almost no PSNR degradation.


Coding Mode Decision Method for MPEG-2/H.264 Transcoder

International Workshop on Vision, Communications and Circuits (IWVCC2008)

In this paper, a novel coding mode decision method for MPEG-2/H.264 is proposed. Some previous works showed that the selected INTRA or INTER mode for MPEG-2 is not suitable for H.264/AVC directly. Observing the features of the modes decided by MPEG-2 we find the optimal mode for H.264/AVC can be estimated by reusing existing information in MPEG-2 bitstream. Proposed method can not only select INTRA/INTER mode for H.264/AVC but also reduce the mode candidates of INTER mode by reusing existing encoded information of MPEG-2 bitstream. Simulation results show that the proposed transcoder can achieve high computation complexity reduction rate with very slight PSNR loss.


Motion Vector Predicted Variable Search Range Motion Estimation Algorithm for H.264/AVC

In this paper, a novel variable search range algorithm for H.264/AVC is proposed. In this work we try to find an adaptive search range selection algorithm to reduce the computation complexity without decreasing encoding efficiency. A novel definition of MVave that is derived from the mean of motion vector in the previous frame is firstly defined to describe the feature of motions in the sequences. Then another parameter of THp is defined to evaluate the distribution of the surrounding motion vectors. Simulation results show that proposed algorithm can reduce 10% of the computation complexity at sequences with less motion and 35% for sequences with more motions.


Coding Efficiency Improvement with Adaptive GOP Size Selection for H.264/SVC

International Conference on Innovative Computing, Information and Control (ICICIC2008)

In this paper, we present a novel adaptive GOP structure (AGS) for H.264/SVC. Proposed method adaptively defines the GOP structure by analyzing the input sequence characters. The accumulated difference of luminance pixel components is utilized to set a threshold for adaptive GOP size definition. Another scene change detection method is also proposed to reorganize the GOP structure. Different from previous AGS methods, the proposed method concentrates on the coding efficiency improvement on the basis of the Hierarchical B-picture structure. The simulation results show that proposed AGS method can improve up to 0.2dB of PSNR compared with fixed size GOP methods.


Fast Deblocking Filter Implementation Method and It's Architecture for H.264/AVC

International Conference in Electrical Engineering/Electronics, Computer, Telecommunications, and Information Technoly (ECTI-CON2008)

In this work, a fast implementation method for deblocking filter of H.264/AVC and its architecture are proposed. Proposed method makes use of the correlation of the adjacent pixels to decrease the redundant processing cycles. Simulation results show that using proposed method, the average coding cycles for one macroblock is reduced to 170. It is fast than that of the previous works that considered that the least filtering cycle number for one macroblock is 192. Implementation results show that the proposed architecture can be realized using 30.14K gates.


Switched CABAC/CAVLC Architecture for Real-Time High Profile Applications of H.264/AVC

Proceedings of International Workshop on Nonlinear Circuits and Signal Processing (NCSP'08)

In this paper, novel entropy coding implementation method and its efficient architecture of H.264/AVC for high bitrate real time HDTV are proposed. The proposed method makes use of this switching bit to adaptively switch the CABAC to CAVLC at the coding peak of CABAC. We also proposed an efficient architecture to realize the proposed switching method. The experimental results show that the proposed method can realize fast coding at the bit generation peak and cut down the buffer consumption with slight bit rate increase.


Fast Transform and Quantization Architecture with All-Zero Detection and Bit Estimation for H.264/AVC

2007 IEEE International Workshop on Signal Design and Its Applications in Communications(IWSDA'07)

In this paper a fast processing architecture for the transform and quantization of the H.264/AVC, named DQ Engine, is proposed. The proposed DQ engine architecture could achieve 2 times fast processing of transform and quantization together with the inverse transform and inverse quantization when the rate-distortion optimization is performed. Moreover, proposed architecture introduced an all-zero block detection architecture that could cut down the redundant processing of the all-zero coefficient blocks. A bit estimation architecture is also introduced into the DQ Engine to fulfill fast estimation of the generated bits. Implementation results show that the proposed architecture could be fulfilled with only 126,728 transistors.


Efficient Motion Compensation Architecture with Rate-Distortion Optimization for H.264/AVC

International Conference on Signal Processing and Multimedia Applications(SIGMAP2007)

In this paper, novel motion compensation architecture is proposed to support the Rate-Distortion Optimization (RDO) in H.264/AVC. First, the scope of the motion compensation in this work is defined not only including the half and quarter pixel motion compensation but also the deblocking filter and rate-distortion optimization. Then, based on the new concept of motion compensation an efficient architecture for H.264/AVC codec is constructed. Pipelined processing structure is designed for sub-block mode selection to achieve real-time processing for up to HDTV resolution inputs. Implementation result shows that proposed architecture could be realized with only 42,280 gates and 48,320 bits SRAM.


Adaptive Search Range Motion Estimation Algorithm for H.264/AVC

2007 IEEE International Symposium on Circuits and Systems(ISCAS'07)

In this paper, a novel variable search range algorithm is proposed for the H.264/AVC. From simulation results we find that how much the search range could be reduced to achieve an optimum search range have strong relation with the average of the frame motion vectors. Based on these simulation results an adaptive search range algorithm which estimate the most efficient search range from the previous frames with a adaptively search range adjustment method is proposed. Simulation results show that proposed algorithm could achieve the motion estimation by average 45% computation complexity compare with the reference software with equivalent PSNR and the bitrate results.


Efficient Variable Search Range Motion Estimation Architecture for Real-time RDO of H.264/AVC

Proceedings of RISP International Workshop on Nonlinear Circuits and Signal Processing (NCSP'07)

The Research Institute of Signal Processing Japan

In this paper, novel motion estimation architecture of H.264/AVC is proposed. To reduce the computation complexity of RDO calculation, we propose a TAD+Top-down method with hardware-friendly structure that could efficiently reduce the number of candidate coding modes. The proposed architecture could support the variable search range motion estimation from the range 0 to ±16, which is possible to cooperate with any kind of variable search range methods proposed so far. The experimental results show that the proposed method could reduce computation complexity of motion estimation 80% average without PSNR and bitrate loss compared with the reference software JM8.2.


Multi-State Estimated Architecture of CABAC for H.264/AVC

In this paper, a novel fast context-adaptive binary arithmetic coder (CABAC) implementation method and an efficient architecture are proposed. Proposed method achieve multi-bits arithmetic coding in one cycle by introducing a Multi-State Estimation(MSE) scheme which accomplish multiple update of state, range and low in one cycle. Discussing the tradeoff between the coding speed and the hardware resource, we give an example solution of two-state estimation implementation with which could cut down half of the coding cycles. We also proposed an efficient architecture with a selectable memory solution for different target applications. Implementation result shows that proposed method could be realized with about 20,000 gates.


Frame Memory Compression Method for H.264/AVC

The 2006 International Technical Conference on Circuits/Systems, Computers and Communications

In this paper, a novel frame memory compression method for the H.264/AVC is proposed. Proposed method introduce DAP (Differential of Adjacent Pixel) and Huffman coding to the original image data between the frame memory interface and the image coding process. Simulation results shows that this method can achieve not only a stable compression rate but also realize a lossless compression which cause no additional information loss to the coding process. Furthermore, proposed method is hardware-friendly and cause no further delay during the memory access period. Proposed method can be realized by only about 7,000 gates.


Evolutional Algorithms of A Steiner Tree Problem in 3-D VLSI

Proceedings of RISP International Workshop on Nonlinear Circuits and Signal Processing (NCSP'06)

In this paper, we propose an efficient routing algorithm for 3-D VLSI. In our method, first, we construct a Euclidian minimum spanning tree and then obtain individual 3-D rectilinear Steiner tree by replacing each pair of terminals in the tree with segments that are parallel to X, Y, or Z-axis using genetic algorithms. Secondly, we shuffling the order of wiring net, replacing each wiring pair and applying to Breadth First Search (BFS) algorithms to those under optimized nets. Several simulation results demonstrate that our method can achieve an optimized total wire length and radius with a higher routing ratio.


Complexity Reduced Variable Block Size Motion Estimation Algorithm for H.264

The 2005 International Technical Conference on Circuits/Systems, Computers and Communications

In this paper, a Block Size-Estimated Variable Block Size Motion Estimation (BSE-VBSME) algorithm is proposed. First, we discussed two proposed methods to estimate the motion estimation block size utilizing temporal block size information of previous frame and the spatial information of the current block. Then, a novel algorithm is proposed to decrease the computation complexity of VBSME by integrating traditional top-down and bottom-up methods into proposed block size estimation methods. Compared with the traditional VBSME algorithm recommended by JM8, the proposed method shows about 50% average computation reduction with almost no quality and bitrate loss.


Low Complexity Triplet Search Motion Estimation for H.264

International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)

In this paper, we propose a fast motion estimation method for H.264, named Triplet Search Motion Estimation(TS-ME). In the same manner as typical traditional fast motion estimation methods such as Three Steps Search(TSS) and Diamond Search(DS), TS-ME is based on the hierarchic motion search, while introducing some new features, 1) high accuracy first step search using triplet patterns, 2) computational cost reduction by referring surrounding motion vectors, and 3) computational cost reduction for sub pixel motion search in accordance with the motion vector appearance probability. From the simulation results, estimation speed is improved by a factor of up to 38 comparing to the JM7.3 reference code of H.264, with very slight loss in picture quality.


Low Power Architecture for H.263 Version2 Codec

In this paper, an efficient algorithm and its VLSI architecture are proposed for H.263 version2. In the H.263 version2, there are 3 main extension are recommended. To these 3 extensions, 3 different algorithms are proposed to realize small area and low power VLSI implementation, respectively. Because these algorithms are hardware oriented improvement for H.263 version2, a very small hardware cost are needed in addition to original H.263 codec.


近海養殖支援に向けた水中物体検出に関する調査

近海養殖支援に向けた水中物体検出に関する調査

Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers

電気関係学会四国支部連合大会講演論文集


交差点映像における高効率セグメンテーションデータセット生成

交差点映像における高効率セグメンテーションデータセット生成

電気関係学会四国支部連合大会講演論文集


交差点映像における Few-shot 物体検出手法に関する研究

交差点映像における Few-shot 物体検出手法に関する研究

電気関係学会四国支部連合大会講演論文集


河川監視システムにおける雨滴分類手法

河川監視システムにおける雨滴分類手法

電気関係学会四国支部連合大会講演論文集


ソナー画像を用いた水中 SLAM におけるループ検出技術の精度評価

ソナー画像を用いた水中 SLAM におけるループ検出技術の精度評価

電気関係学会四国支部連合大会講演論文集


二つのコウモリ群を用いたフロアプラン最適化アルゴリズムに関する研究

二つのコウモリ群を用いたフロアプラン最適化アルゴリズムに関する研究

電気関係学会四国支部連合大会講演論文集


SA アルゴリズムを用いた b*-tree 表現フロアプランの最適化に関する研究

電気関係学会四国支部連合大会講演論文集


方向性を考慮した条件付きグリッド拡張を用いた TSV 割り当てに関する研究

方向性を考慮した条件付きグリッド拡張を用いた TSV 割り当てに関する研究

電気関係学会四国支部連合大会講演論文集


遺伝的アルゴリズムによる LSI の配置最適化に関する研究

遺伝的アルゴリズムによる LSI の配置最適化に関する研究

電気関係学会四国支部連合大会講演論文集


水中音響画像変換における CycleGAN を用いた高精度 3D マッピング

水中音響画像変換における CycleGAN を用いた高精度 3D マッピング

電気関係学会四国支部連合大会講演論文集


顕著性マップに基づく再学習用データセット厳選アルゴリズム

顕著性マップに基づく再学習用データセット厳選アルゴリズム

電気関係学会四国支部連合大会講演論文集


ドローン映像における高精度小数画素精度動き補償フィルタ

ドローン映像における高精度小数画素精度動き補償フィルタ

電気関係学会四国支部連合大会講演論文集


動画像における機械学習による長期参照画像生成に関する研究

動画像における機械学習による長期参照画像生成に関する研究

電気関係学会四国支部連合大会講演論文集


水中画像の色補正方法に関する研究

水中画像の色補正方法に関する研究

電気関係学会四国支部連合大会講演論文集


機械学習を用いた次世代画面内符号化技術に関する研究

機械学習を用いた次世代画面内符号化技術に関する研究

電気関係学会四国支部連合大会講演論文集


フロアプラン設計のための遺伝的アルゴリズムによる配置最適化に関する研究

フロアプラン設計のための遺伝的アルゴリズムによる配置最適化に関する研究

電気関係学会四国支部連合大会講演論文集


Removal of rain in panorama images using GAN

パノラマ映像における GANを用いた雨除去に関する研究

人工知能学会全国大会(JSAI2021)

人工知能学会全国大会(JSAI2021)

オンライン開催 X会場 (ポスター会場1)

オンライン開催 X会場 (ポスター会場1)


An Adaptive Selection Method of Screen Content Coding Tools for Educational Video System

教育用配信システムにおけるスクリーンコンテンツ符号化ツール選択手法に関する研究

人工知能学会全国大会(JSAI2021)

人工知能学会全国大会(JSAI2021)

オンライン開催 X会場 (ポスター会場1)

オンライン開催 X会場 (ポスター会場1)


Research on underwater depth estimation using machine learning

機械学習を用いた水中深度推定に関する研究

人工知能学会全国大会(JSAI2021)

人工知能学会全国大会(JSAI2021)

オンライン開催 X会場 (ポスター会場1)

オンライン開催 X会場 (ポスター会場1)


Underwater Image Enhancement with JetsonXavier

JetsonXavierを用いた水中画像補正に関する研究

人工知能学会全国大会(JSAI2021)

人工知能学会全国大会(JSAI2021)

オンライン開催 X会場 (ポスター会場1)

オンライン開催 X会場 (ポスター会場1)


VVCにおける特徴マップを応用した色差成分予測手法に関する研究

VVCにおける特徴マップを応用した色差成分予測手法に関する研究

画像符号化シンポジウム(PCSJ2020)

画像符号化シンポジウム(PCSJ2020)


InstaGANを用いた学習ライブラリ構築に関する研究

InstaGANを用いた学習ライブラリ構築に関する研究

画像符号化シンポジウム(PCSJ2020)

画像符号化シンポジウム(PCSJ2020)


昼夜変換画像による夜間物体検出精度向上に関する研究

昼夜変換画像による夜間物体検出精度向上に関する研究

画像符号化シンポジウム(PCSJ2020)

画像符号化シンポジウム(PCSJ2020)


InstaGANを用いた学習ライブラリ構築に関する研究

InstaGANを用いた学習ライブラリ構築に関する研究

電気関係学会四国支部連合大会講演論文集


遺伝的アルゴリズムを用いたLSIにおける面積と電力密度のトレードオフ最適化に関する研究

電気関係学会四国支部連合大会講演論文集


固定アウトラインでの再帰的分割法を用いたモジュールの配置に関する研究

固定アウトラインでの再帰的分割法を用いたモジュールの配置に関する研究

電気関係学会四国支部連合大会講演論文集


VVCイントラ予測残差における変換係数予測手法に関する研究

VVCイントラ予測残差における変換係数予測手法に関する研究

電気関係学会四国支部連合大会講演論文集


オブジェクト検出の高速化アルゴリズムに関する研究

オブジェクト検出の高速化アルゴリズムに関する研究

電気関係学会四国支部連合大会講演論文集


CNNを用いたHEVCのイントラ符号化効率向上に関する研究

CNNを用いたHEVCのイントラ符号化効率向上に関する研究

電気関係学会四国支部連合大会講演論文集


VVCの画面間符号化におけるベイジアンネットワークを用いた高速モード決定手法に関する研究

電気関係学会四国支部連合大会講演論文集


3D-ICにおけるTSV割り当てのための効率的なアルゴリズム

3D-ICにおけるTSV割り当てのための効率的なアルゴリズム

電気関係学会四国支部連合大会講演論文集


MDS問題における最適アルゴリズムとそのPCB配線への応用

MDS問題における最適アルゴリズムとそのPCB配線への応用

電気関係学会四国支部連合大会講演論文集


ブラインドビア・差動ペアを使用したPCBにおけるエスケープ配線の最適化に関する研究

電気関係学会四国支部連合大会講演論文集


画面間予測におけるクラウドベース参照画像選択手法

画面間予測におけるクラウドベース参照画像選択手法

電子情報通信学会総合大会講演論文集

電子情報通信学会総合大会講演論文集

Institute of Electronics, Information and Communication Engineers


HEVCイントラ予測における原画素を用いた高速処理アルゴリズム

HEVCイントラ予測における原画素を用いた高速処理アルゴリズム

電子情報通信学会総合大会講演論文集

電子情報通信学会総合大会講演論文集


JEMのイントラ予測符号化における情報隠蔽技術に関する研究

JEMのイントラ予測符号化における情報隠蔽技術に関する研究

画像符号化シンポジウム(PCSJ2018)

画像符号化シンポジウム(PCSJ2018)


look-ahead合法化を用いたフロアプランに関する研究

look-ahead合法化を用いたフロアプランに関する研究

電気関係学会四国支部連合大会講演論文集


SPAにおける単一信号及び差動ペアを共に考慮できるエスケープ配線に関する研究

SPAにおける単一信号及び差動ペアを共に考慮できるエスケープ配線に関する研究

電気関係学会四国支部連合大会講演論文集


機械学習を用いた海鼠の認識システムの開発に関する研究

機械学習を用いた海鼠の認識システムの開発に関する研究

電子情報通信学会総合大会講演論文集

電子情報通信学会総合大会講演論文集


顕著性検出を用いた動画像符号化アルゴリズムに関する研究

顕著性検出を用いた動画像符号化アルゴリズムに関する研究

電気関係学会四国支部連合大会講演論文集


複数ネットにおける長さ整合のための配線アルゴリズムに関する研究

複数ネットにおける長さ整合のための配線アルゴリズムに関する研究

電気関係学会四国支部連合大会講演論文集


3次元グローバル配置におけるTSV カップリング削減に関する研究

3次元グローバル配置におけるTSV カップリング削減に関する研究

電気関係学会四国支部連合大会講演論文集


H.265/HEVCにおけるウォーターマーキング技術に関する研究

H.265/HEVCにおけるウォーターマーキング技術に関する研究

電子情報通信学会総合大会講演論文集

電子情報通信学会総合大会講演論文集


深層学習を用いた海鼠認識に関する研究

深層学習を用いた海鼠認識に関する研究

電子情報通信学会総合大会講演論文集

電子情報通信学会総合大会講演論文集


携帯端末向け参照フレーム削減によるHEVCの低消費電力実現に関する研究

携帯端末向け参照フレーム削減によるHEVCの低消費電力実現に関する研究

電気関係学会四国支部連合大会講演論文集


HEVCのハードウェア実装におけるTUサイズ選択手法の性能評価

HEVCのハードウェア実装におけるTUサイズ選択手法の性能評価

電気関係学会四国支部連合大会講演論文集


HEVCにおけるDCT係数の差分符号化による符号化効率向上の性能評価

HEVCにおけるDCT係数の差分符号化による符号化効率向上の性能評価

電気関係学会四国支部連合大会講演論文集


積層信号TSV活用のための熱源探索に関する研究

積層信号TSV活用のための熱源探索に関する研究

電気関係学会四国支部連合大会講演論文集


アンテナ効果を削減する多層配線に関する研究

アンテナ効果を削減する多層配線に関する研究

電気関係学会四国支部連合大会講演論文集


HEVCにおける双方向予測の演算量削減に関する研究

HEVCにおける双方向予測の演算量削減に関する研究

電気関係学会四国支部連合大会講演論文集


HEVCにおける低演算量CUサイズ決定手法に関する研究

HEVCにおける低演算量CUサイズ決定手法に関する研究

電気関係学会四国支部連合大会講演論文集


力学的手法による2Dフロアプランニング

力学的手法による2Dフロアプランニング

電気関係学会四国支部連合大会講演論文集


並列処理を取り入れた障害物回避直線スタイナー木構築手法

並列処理を取り入れた障害物回避直線スタイナー木構築手法

電気関係学会四国支部連合大会講演論文集


HEVCにおける高精度動き探索手法に関する研究

HEVCにおける高精度動き探索手法に関する研究

電気関係学会四国支部連合大会講演論文集


H.264/AVCにおける予測コストを用いたモード決定手法

H.264/AVCにおける予測コストを用いたモード決定手法

電気関係学会四国支部連合大会講演論文集


ズーム対応動き探索アルゴリズムに関する研究

ズーム対応動き探索アルゴリズムに関する研究

電気関係学会四国支部連合大会講演論文集


TSVの位置と面積を考慮した3D-ICフロアプラン

TSVの位置と面積を考慮した3D-ICフロアプラン

電気関係学会四国支部連合大会講演論文集


ブロックの分割を用いたTSV-共同配置方式によるフロアプランニング

ブロックの分割を用いたTSV-共同配置方式によるフロアプランニング

電気関係学会四国支部連合大会講演論文集


障害物回避直線スタイナー木の効率的多層探索に関する研究

障害物回避直線スタイナー木の効率的多層探索に関する研究

電気関係学会四国支部連合大会講演論文集


GPUによるHEVC動き探索の高速化に関する研究

GPUによるHEVC動き探索の高速化に関する研究

電気関係学会四国支部連合大会講演論文集


H.264/SVCにおける双方向予測の高速化

H.264/SVCにおける双方向予測の高速化

電気関係学会四国支部連合大会講演論文集


H.264/AVC における高精度イントラ予測手法に関する研究

H.264/AVC における高精度イントラ予測手法に関する研究

電気関係学会四国支部連合大会講演論文集


スタイナー点による障害物回避配線とその3次元化

スタイナー点による障害物回避配線とその3次元化

電気関係学会四国支部連合大会講演論文集


障害物回避スタイナー木の効率的な構築手法

障害物回避スタイナー木の効率的な構築手法

電気関係学会四国支部連合大会講演論文集


DP曲線を用いた電圧割当て

DP曲線を用いた電圧割当て

電気関係学会四国支部連合大会講演論文集


B*木を用いたフロアプランにおける遅延制約を考慮した電圧割当てに関する研究

B*木を用いたフロアプランにおける遅延制約を考慮した電圧割当てに関する研究

電気関係学会四国支部連合大会講演論文集


論理的境界にとらわれない電圧島生成

論理的境界にとらわれない電圧島生成

電気関係学会四国支部連合大会講演論文集


画面間予測を用いたイントラ符号化アルゴリズム

画面間予測を用いたイントラ符号化アルゴリズム

第14回DSPS教育会議

第14回DSPS教育会議


低消費電力LSI設計のためのセル電源電圧割当て

低消費電力LSI設計のためのセル電源電圧割当て

電気関係学会四国支部連合大会講演論文集


多層配線における最小スタイナー木の構築法

多層配線における最小スタイナー木の構築法

電気関係学会四国支部連合大会講演論文集


Optimization Methodology for Floorplan with Voltage Assignment

Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers


走査線探索を用いた効率的な多層配線手法

走査線探索を用いた効率的な多層配線手法

電気関係学会四国支部連合大会講演論文集


概略配線における密集制限を用いた層割り当てに関する研究

概略配線における密集制限を用いた層割り当てに関する研究

電気関係学会四国支部連合大会講演論文集


Fast Key-Frame Selection Method for Target Number Limited Environment


H.264/AVCにおける高効率モード選択手法

H.264/AVCにおける高効率モード選択手法

電子情報通信学会総合大会講演論文集

電子情報通信学会総合大会講演論文集


H.264/SVCにおけるイントラモード選択手法

H.264/SVCにおけるイントラモード選択手法

電子情報通信学会ソサイエティ大会講演論文集


MPEG-2/H.264トランスコーダにおける符号化モード選択手法

MPEG-2/H.264トランスコーダにおける符号化モード選択手法

電子情報通信学会総合大会講演論文集

電子情報通信学会総合大会講演論文集


H.264/AVCにおける動きベクトルを用いたビットレート制御

H.264/AVCにおける動きベクトルを用いたビットレート制御

電子情報通信学会総合大会講演論文集

電子情報通信学会総合大会講演論文集


高解像度用H.264/AVCにおけるエントロピー符号化手法

高解像度用H.264/AVCにおけるエントロピー符号化手法

電子情報通信学会総合大会講演論文集

電子情報通信学会総合大会講演論文集


樹木型直線スタイナー配線の近似解法

樹木型直線スタイナー配線の近似解法

電気関係学会四国支部連合大会講演論文集


H.264/AVCにおける動き探索範囲に関する研究

H.264/AVCにおける動き探索範囲に関する研究

電子情報通信学会ソサイエティ大会講演論文集


H.264/AVCにおけるCABAC高速処理アーキテクチャ

H.264/AVCにおけるCABAC高速処理アーキテクチャ

電子情報通信学会総合大会講演論文集

電子情報通信学会総合大会講演論文集


Fast 4-step Intra-Prediction Mode Selection Method for H.264/AVC

電子情報通信学会総合大会講演論文集

電子情報通信学会総合大会講演論文集

Institute of Electronics, Information and Communication Engineers


スパニンググラフを用いたスタイナー木の効率的な構築方法

スパニンググラフを用いたスタイナー木の効率的な構築方法

電気関係学会四国支部連合大会講演論文集


直方体パッキング問題のSA法による解法

直方体パッキング問題のSA法による解法

電気関係学会四国支部連合大会講演論文集


HEVCイントラ予測残差におけるDC係数推定アルゴリズムに関する研究

HEVCイントラ予測残差におけるDC係数推定アルゴリズムに関する研究

電子情報通信学会技術研究報告


SHVCのエンハンスメントレイヤ符号化時における低演算アルゴリズムに関する研究

SHVCのエンハンスメントレイヤ符号化時における低演算アルゴリズムに関する研究

The Technical Report on the Institute of Image Information and Television Engineers

映像情報メディア学会技術報告

The Institute of Image Information and Television Engineers


Introductory Laboratory on Electrical and Electronic Engineering for an Introductory Education in the First Year

初年度導入教育のための電気電子工学入門実験

The Papers of Technical Meeting, IEE JAPAN

The Institute of Electrical Engineers of Japan


H.264/AVCにおけるAll-Zeroブロック検出および生成ビット数を予測可能なDCT・量子化アーキテクチャ

電子情報通信学会技術研究報告


H.264/AVCにおけるデブロッキングフィルタの低消費電力化実装手法

H.264/AVCにおけるデブロッキングフィルタの低消費電力化実装手法

電子情報通信学会技術研究報告


H.264/AVCデコーダにおける低演算量デブロッキングフィルタ実装手法

H.264/AVCデコーダにおける低演算量デブロッキングフィルタ実装手法

電子情報通信学会技術研究報告


H.264/AVCにおけるフレームメモリアクセス手法

H.264/AVCにおけるフレームメモリアクセス手法

電子情報通信学会技術研究報告