=== Generating (published_papers) ===
=== Generating (research_interests) ===
=== Generating (teaching_experience) ===
=== Generating (education) ===
=== Generating (research_experience) ===
=== Generating (research_projects) ===
=== Generating (books_etc) ===
=== Generating (industrial_property_rights) ===
=== Generating (committee_memberships) ===
=== Generating (awards) ===
=== Generating (association_memberships) ===
=== Generating (presentations) ===
==== begin registerFile(/WWW/pub2/data/ERD/person/79439/researchmap/published_papers.jsonl) ====
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line:27, {"insert":{"user_id":"5000080634","type":"published_papers","id":"28296389"},"force":{"see_also":[{"@id":"https://www.scopus.com/record/display.url?eid=2-s2.0-84947928867&origin=inward","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=303989","label":"url"}],"paper_title":{"en":"Spatio-Temporal Prediction Based Algorithm for Parallel Improvement of HEVC","ja":"Spatio-Temporal Prediction Based Algorithm for Parallel Improvement of HEVC"},"authors":{"en":[{"name":"Jiang Xiantao"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"},{"name":"Shi Wen"},{"name":"Wang Lisheng"}],"ja":[{"name":"蒋 先涛"},{"name":"宋 天"},{"name":"島本 隆"},{"name":"石 文"},{"name":"王 力生"}]},"description":{"en":"本論文は，GPUによる高速並列処理を目的とした空間と時間領域の予測手法を用いた高効率アルゴリズムを提案した．空間領域の相関性を利用した動きベクトルの予測手法と時間領域の予測による動きベクトルの予測手法を提案し，両手法を総合的に利用した高速並列処理アルゴリズムを提案した．提案手法を参照ソフトウェアJM12.0に実装しシミュレーションした結果，従来手法に比べ画質の劣化がほとんどなく，高速な並列処理を実現した．","ja":"本論文は，GPUによる高速並列処理を目的とした空間と時間領域の予測手法を用いた高効率アルゴリズムを提案した．空間領域の相関性を利用した動きベクトルの予測手法と時間領域の予測による動きベクトルの予測手法を提案し，両手法を総合的に利用した高速並列処理アルゴリズムを提案した．提案手法を参照ソフトウェアJM12.0に実装しシミュレーションした結果，従来手法に比べ画質の劣化がほとんどなく，高速な並列処理を実現した．"},"publication_date":"2015-11","publication_name":{"en":"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences","ja":"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences"},"volume":"Vol.E98-A","number":"No.11","starting_page":"2229","ending_page":"2237","languages":["eng"],"referee":true,"identifiers":{"doi":["10.1587/transfun.E98.A.2229"],"issn":["0916-8508"]},"published_paper_type":"scientific_journal"},"priority":"input_data"}
line:28, {"insert":{"user_id":"5000080634","type":"published_papers","id":"13729363"},"force":{"see_also":[{"@id":"http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7027201","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=303987","label":"url"}],"paper_title":{"en":"Hierarchical structure based fast mode decision for H.265/HEVC","ja":"Hierarchical structure based fast mode decision for H.265/HEVC"},"authors":{"en":[{"name":"Wenjun Zhao"},{"name":"Takao Onoye"},{"name":"Song Tian"}],"ja":[{"name":"趙 文軍"},{"name":"尾上 孝雄"},{"name":"宋 天"}]},"description":{"en":"本論文は，H.265/HEVCにいて階層構造に基づいた高速モード決定手法を提案した．まず，前フレームの深度情報を用いて現在のCUのモードを予測する．また，残差情報を用いてモード候補を絞る．さらに，画面内符号化に対してもハードウェア実装を考慮した低演算量かつ小面積のアーキテクチャを提案した．提案手法を実装しシミュレーションを行った結果，提案手法は54%~68%の演算量削減を実現した．","ja":"本論文は，H.265/HEVCにいて階層構造に基づいた高速モード決定手法を提案した．まず，前フレームの深度情報を用いて現在のCUのモードを予測する．また，残差情報を用いてモード候補を絞る．さらに，画面内符号化に対してもハードウェア実装を考慮した低演算量かつ小面積のアーキテクチャを提案した．提案手法を実装しシミュレーションを行った結果，提案手法は54%~68%の演算量削減を実現した．"},"publication_date":"2015-10","publication_name":{"en":"IEEE Transactions on Circuits and Systems for Video Technology","ja":"IEEE Transactions on Circuits and Systems for Video Technology"},"volume":"Vol.25","number":"No.10","starting_page":"1651","ending_page":"1664","languages":["eng"],"referee":true,"identifiers":{"doi":["10.1109/TCSVT.2015.2395751"],"issn":["1051-8215"]},"published_paper_type":"scientific_journal"},"priority":"input_data"}
line:29, {"insert":{"user_id":"5000080634","type":"published_papers","id":"28340328"},"force":{"see_also":[{"@id":"http://ci.nii.ac.jp/naid/130005089906/","label":"url"},{"@id":"https://cir.nii.ac.jp/crid/1390282681286803840/","label":"url"},{"@id":"https://www.scopus.com/record/display.url?eid=2-s2.0-84938920529&origin=inward","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=303986","label":"url"}],"paper_title":{"en":"Hardware Architecture of the Fast Mode Decision Algorithm for H.265/HEVC","ja":"Hardware Architecture of the Fast Mode Decision Algorithm for H.265/HEVC"},"authors":{"en":[{"name":"Zhao Wenjun"},{"name":"Onoye Takao"},{"name":"Song Tian"}],"ja":[{"name":"趙 文軍"},{"name":"尾上 孝雄"},{"name":"宋 天"}]},"description":{"en":"In this paper, a specified hardware architecture of the Fast Mode Decision (FMD) algorithms presented by our previous work is proposed. This architecture is designed as an embedded mode dispatch module. On the basis of this module, some unnecessary modes can be skipped or the mode decision process can be terminated in advanced. In order to maintain a higher compatibility, the FMD algorithms are unitedly designed as an unique module that can be easily embedded into a common video codec for H.265/HEVC. The input and output interfaces between the proposed module and other parts of the codec are designed based on simple but effective protocol. Hardware synthesis results on FPGA demonstrate that the proposed architecture achieves a maximum frequency of about 193 MHz with less than 1% of the total resources consumed. Moreover, the proposed module can improve the overall throughput.","ja":"本論文は，H.265/HEVCにいて高速モード決定手法を提案した．提案手法は，前フレームの深度情報を用いて現在のCUのモードを予測し，残差情報を用いてモード候補を絞る手法を提案する．さらに，これらの提案を実現する小面積のアーキテクチャを提案し，FPGAに実装した．提案アーキテクチャは，わずか1%のFPGAリソースを使用し，193MHzで動作可能である．"},"publication_date":"2015-08","publication_name":{"en":"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences","ja":"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences"},"volume":"Vol.E98.A","number":"No.8","starting_page":"1787","ending_page":"1795","languages":["eng"],"referee":true,"identifiers":{"doi":["10.1587/transfun.E98.A.1787"],"issn":["0916-8508"]},"published_paper_type":"scientific_journal"},"priority":"input_data"}
line:30, {"insert":{"user_id":"5000080634","type":"published_papers","id":"13729365"},"force":{"see_also":[{"@id":"https://www.scopus.com/record/display.url?eid=2-s2.0-84948712294&origin=inward","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=296852","label":"url"}],"paper_title":{"en":"Enhancing the Presence Service Efficiency of Internet Protocol Multimedia Subsystem-Based Web Services","ja":"Enhancing the Presence Service Efficiency of Internet Protocol Multimedia Subsystem-Based Web Services"},"authors":{"en":[{"name":"Jenq-Shiou Leu"},{"name":"Kun-Che Hsu"},{"name":"Song Tian"}],"ja":[{"name":"Jenq-Shiou Leu"},{"name":"Kun-Che Hsu"},{"name":"宋 天"}]},"description":{"en":"本論文は，インターネット上のマルチメディア通信品質の改善を目的に，品質改善システムを提案した．まず，ユーザとネットワーク間に新たなインターネット・サブシステムをゲートウェイとして追加する．このサブシステムがユーザの大量な状態情報を高速に扱うことができるため，ネット遅延を大幅に削減できる．提案システムを実装し，シミュレーションした結果により，平均40%∼54%の遅延の削減を実現した．","ja":"本論文は，インターネット上のマルチメディア通信品質の改善を目的に，品質改善システムを提案した．まず，ユーザとネットワーク間に新たなインターネット・サブシステムをゲートウェイとして追加する．このサブシステムがユーザの大量な状態情報を高速に扱うことができるため，ネット遅延を大幅に削減できる．提案システムを実装し，シミュレーションした結果により，平均40%∼54%の遅延の削減を実現した．"},"publication_date":"2015-07-19","publication_name":{"en":"Wireless Personal Communications","ja":"Wireless Personal Communications"},"volume":"Vol.85","number":"No.4","starting_page":"2319","ending_page":"2331","languages":["eng"],"referee":true,"identifiers":{"doi":["10.1007/s11277-015-2907-z"],"issn":["0929-6212"]},"published_paper_type":"scientific_journal"},"priority":"input_data"}
line:31, {"insert":{"user_id":"5000080634","type":"published_papers","id":"28284318"},"force":{"see_also":[{"@id":"https://www.scopus.com/record/display.url?eid=2-s2.0-84930439344&origin=inward","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=295149","label":"url"}],"paper_title":{"en":"Compressed Sensing Signal Recovery via Creditability-Estimation Based Matching Pursuit","ja":"Compressed Sensing Signal Recovery via Creditability-Estimation Based Matching Pursuit"},"authors":{"en":[{"name":"Liu Yizhong"},{"name":"Song Tian"},{"name":"Zhuang Yiqi"},{"name":"Shimamoto Takashi"},{"name":"Li Xiang"}],"ja":[{"name":"Liu Yizhong"},{"name":"宋 天"},{"name":"Zhuang Yiqi"},{"name":"島本 隆"},{"name":"Li Xiang"}]},"description":{"en":"本論文は，圧縮感知信号の回復を目的に信頼性予測手法を用いたマッチング追跡手法を提案した．従来の信頼性予測手法のサポートポイントセット選択手法を分析し，固定の閾値による選択が非効率であることが判明したため，確率の高いサポートポイントを優先に選択し，他のポイントを追加していく手法を採用した．提案手法を実装しシミュレーションした結果，従来手法に比べ優れた信号回復能力を示した．","ja":"本論文は，圧縮感知信号の回復を目的に信頼性予測手法を用いたマッチング追跡手法を提案した．従来の信頼性予測手法のサポートポイントセット選択手法を分析し，固定の閾値による選択が非効率であることが判明したため，確率の高いサポートポイントを優先に選択し，他のポイントを追加していく手法を採用した．提案手法を実装しシミュレーションした結果，従来手法に比べ優れた信号回復能力を示した．"},"publication_date":"2015-06","publication_name":{"en":"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences","ja":"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences"},"volume":"Vol.E98-A","number":"No.6","starting_page":"1234","ending_page":"1243","languages":["eng"],"referee":true,"identifiers":{"doi":["10.1587/transfun.E98.A.1234"],"issn":["0916-8508"]},"published_paper_type":"scientific_journal"},"priority":"input_data"}
line:32, {"insert":{"user_id":"5000080634","type":"published_papers","id":"13729367"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=293743","label":"url"}],"paper_title":{"en":"Edge Detector Based Fast Level Decision Algorithm for Intra Prediction of HEVC","ja":"Edge Detector Based Fast Level Decision Algorithm for Intra Prediction of HEVC"},"authors":{"en":[{"name":"Shi Wen"},{"name":"Jiang Xiantao"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"石 文"},{"name":"蒋 先涛"},{"name":"宋 天"},{"name":"島本 隆"}]},"description":{"en":"本論文は，HEVCの画面内符号化においてエッジ情報を用いた符号化レベルの高速決定手法を提案した．符号化対象のCUの画素に対しエッジ情報を用いてエッジ強度を評価し，エッジ強度による符号化レベルを適応的に決定するアルゴリズムを提案した．提案手法を参照ソフトウェアJM12.1に実装しシミュレーションした結果，従来手法に比べ平均37%の高速化を実現した．","ja":"本論文は，HEVCの画面内符号化においてエッジ情報を用いた符号化レベルの高速決定手法を提案した．符号化対象のCUの画素に対しエッジ情報を用いてエッジ強度を評価し，エッジ強度による符号化レベルを適応的に決定するアルゴリズムを提案した．提案手法を参照ソフトウェアJM12.1に実装しシミュレーションした結果，従来手法に比べ平均37%の高速化を実現した．"},"publication_date":"2015-03","publication_name":{"en":"Journal of Signal Processing","ja":"Journal of Signal Processing"},"volume":"Vol.19","number":"No.2","starting_page":"67","ending_page":"73","languages":["eng"],"referee":true,"identifiers":{"doi":["10.2299/jsp.19.67"],"issn":["1342-6230"]},"published_paper_type":"scientific_journal"},"priority":"input_data"}
line:33, {"insert":{"user_id":"5000080634","type":"published_papers","id":"13729368"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=258820","label":"url"}],"paper_title":{"en":"Efficient Architecture for Motion Vector Management of H.264/AVC Decoder for 4K Resolution","ja":"Efficient Architecture for Motion Vector Management of H.264/AVC Decoder for 4K Resolution"},"authors":{"en":[{"name":"Song Tian"},{"name":"Ishikura Naoyuki"},{"name":"Watanabe Kenji"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"宋 天"},{"name":"石倉 直幸"},{"name":"Watanabe Kenji"},{"name":"島本 隆"}]},"description":{"en":"UHDTV is highly required for video streaming and broadcasting. However, the computational complexity for 4K-resolution applications is still the bottleneck preventing the realization of real-time decoders. In this work, a motion vector management architecture that is designed for total motion vector management and calculation is proposed. The proposed architecture can calculate predicted motion vectors, select reference motion vectors for the direct mode, and calculate the motion vectors for interlace decoding. The proposed architecture can perform 176 cycles/MB decoding in the worst case. The simulation result shows that when working at 200 MHz, the proposed architecture can be implemented by about 99k gates.","ja":"訳: 本論文は，4Kまでの解像度をデコード可能なH.264/AVC動きベクトル管理アーキテクチャを提案している．提案アーキテクチャは，予測動きベクトルの管理と計算，ダイレクトモードの動きベクトル選択，インターレース復号のための動きベクトル計算を行う．提案アーキテクチャを実装し，合成した結果，わずか99Kのゲート実現でき，FPGAで実装した場合最大動作周波数は200MHzとなった．"},"publication_date":"2012-11","publication_name":{"en":"Journal of Signal Processing","ja":"Journal of Signal Processing"},"volume":"Vol.16","number":"No.6","starting_page":"611","ending_page":"616","languages":["eng"],"referee":true,"identifiers":{"doi":["10.2299/jsp.16.611"],"issn":["1342-6230"]},"published_paper_type":"scientific_journal"},"priority":"input_data"}
line:34, {"insert":{"user_id":"5000080634","type":"published_papers","id":"13729369"},"force":{"see_also":[{"@id":"https://www.scopus.com/record/display.url?eid=2-s2.0-84860808556&origin=inward","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=249835","label":"url"}],"paper_title":{"en":"Low Complexity Algorithm for Inter-layer Prediction of H.264/SVC","ja":"Low Complexity Algorithm for Inter-layer Prediction of H.264/SVC"},"authors":{"en":[{"name":"Song Tian"},{"name":"Takei Kentaro"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"宋 天"},{"name":"武井 健太郎"},{"name":"島本 隆"}]},"description":{"en":"Inter-layer prediction of H.264/SVC can help to improve the coding efficiency with increased computation complexity. This paper presents a low complexity algorithm for inter-layer prediction. The proposed algorithm focuses on the reduction of the candidate modes by making use of the correlations of the encoding cost between the base layer and enhancement layers. For macroblocks with the collocated macroblock coded by INTRA or INTER type two algorithms are proposed, respectively. Both algorithms efficiently decrease the redundant candidate modes by estimating from the base layer coding information. The experiment results show that the proposed algorithm can significantly reduce redundant computation complexity with almost no coding efficiency loss.","ja":"訳: H.264/SVCはスケラビリティを実現できるものの，高演算量より実用困難となっている．本研究は，H.264/SVCインターレイヤ予測の低演算量アルゴリズムを提案した．階層間の符号化コストの相関性を利用し，インターレイヤイントラ予測とインターレイヤインター予測の低演算量アルゴリズムを提案した．参照ソフトウェアJSVMに実装しシミュレーションした結果，符号化効率に影響なく，大幅な演算量削減が実現できた．"},"publication_date":"2012-05","publication_name":{"en":"International Journal of Innovative Computing, Information and Control","ja":"International Journal of Innovative Computing, Information and Control"},"volume":"Vol.8","number":"No.5(A)","starting_page":"3103","ending_page":"3113","languages":["eng"],"referee":true,"identifiers":{"issn":["1349-4198"]},"published_paper_type":"scientific_journal"},"priority":"input_data"}
line:35, {"insert":{"user_id":"5000080634","type":"published_papers","id":"13729370"},"force":{"see_also":[{"@id":"http://ci.nii.ac.jp/naid/40019081712/","label":"url"},{"@id":"https://cir.nii.ac.jp/crid/1520291853539001984/","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=242674","label":"url"}],"paper_title":{"en":"Key Frame Extraction Method Based on Motion Features of H.264/AVC","ja":"Key Frame Extraction Method Based on Motion Features of H.264/AVC"},"authors":{"en":[{"name":"Li Yi"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"李 毅"},{"name":"宋 天"},{"name":"島本 隆"}]},"description":{"en":"In this paper, we propose a novel key-frame selection algorithm for video retrieval. Firstly, the video sequences are segmented into shots with the pixel features between consecutive frames. Then, based on the MV and MVD features of H.264, we notice that MV can reflect the displacement of objects in the frames and MVD can reflect the regularity of motion. Thus, the intensity of the motion can be reflected through MV and MVD features, and key-frames are selected with the greatest intensity of motion in each shot. The experimental results show that our proposed algorithm can weaken the influence of camera motion and select key-frames from video sequences effectively.","ja":"訳: 本論文は，H.264/AVCのコンテンツからキーフレームを効率的に抽出するアルゴリズムを提案している．提案アルゴリズムは，動きベクトルの差分(MVD)を定義し，MVDとMVの特徴を調査し，動きの大きさと動き一致率を示した．この特性を利用し，動画像コンテンツの内容を正確に反映するキーフレーム抽出アルゴリズムを提案した．提案手法を実装し評価した結果，真の特徴フレームが抽出されたことが確認できた．"},"publication_date":"2011-11","publication_name":{"en":"Journal of Signal Processing","ja":"Journal of Signal Processing"},"volume":"Vol.15","number":"No.6","starting_page":"443","ending_page":"450","languages":["eng"],"referee":true,"identifiers":{"issn":["1342-6230"]},"published_paper_type":"scientific_journal"},"priority":"input_data"}
line:36, {"insert":{"user_id":"5000080634","type":"published_papers","id":"13729371"},"force":{"see_also":[{"@id":"http://ci.nii.ac.jp/naid/40018946833/","label":"url"},{"@id":"https://cir.nii.ac.jp/crid/1520291854804518784/","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=231950","label":"url"}],"paper_title":{"en":"Improved Interlayer Intraprediction for Scalable Video Coding","ja":"Improved Interlayer Intraprediction for Scalable Video Coding"},"authors":{"en":[{"name":"Zhao Wenjun"},{"name":"Song Tian"},{"name":"Wang Jinxiang"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"Zhao Wenjun"},{"name":"宋 天"},{"name":"Wang Jinxiang"},{"name":"島本 隆"}]},"description":{"en":"In this paper, a method based on the two dimensional Wiener filter is proposed in addition to inter-layer intra prediction in H.264/SVC. The performance of inter-layer intra prediction is limited due to the up-sampling operation and the coding noise of base layer. The Wiener filter can be used as an optimizing filter to enhance the prediction of enhancement. However, prediction errors of some pixels are increased by this filter operation. The proposed method applies the filter for each block of different size adaptively. Experimental results show that the reduction of bit rate and PSNR improvement for QCIF-CIF Akiyo sequences are 3.74% and 1.15dB without considering the bit cost of filter operation.","ja":"訳: 本論文は，H.264/SVCインターレイヤイントラ予測にウィナーフィルタを用いた高予測精度アルゴリズムを提案する．インターレイヤイントラ予測は，アップサンプリングの精度不足より高圧縮率を実現できなかった．提案手法は，各種ブロックサイズに適応的にフィルタ処理を施し，高予測精度を実現した．シミュレーションより，QCIF-CIFサイズAkiyoシーケンスに対し3.74%のビット削減と1.15dBのPSNR向上が実現できた．"},"publication_date":"2011-07","publication_name":{"en":"Journal of Signal Processing","ja":"Journal of Signal Processing"},"volume":"Vol.15","number":"No.4","starting_page":"299","ending_page":"302","languages":["eng"],"referee":true,"identifiers":{"issn":["1342-6230"]},"published_paper_type":"scientific_journal"},"priority":"input_data"}
line:37, {"insert":{"user_id":"5000080634","type":"published_papers","id":"13729372"},"force":{"see_also":[{"@id":"https://www.scopus.com/record/display.url?eid=2-s2.0-78650914782&origin=inward","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=220454","label":"url"}],"paper_title":{"en":"Complexity Reduction Algorithm for Hierarchical B-Picture of H.264/SVC","ja":"Complexity Reduction Algorithm for Hierarchical B-Picture of H.264/SVC"},"authors":{"en":[{"name":"Hamamoto Takaaki"},{"name":"Song Tian"},{"name":"Katayama Takafumi"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"濱本 高彰"},{"name":"宋 天"},{"name":"片山 貴文"},{"name":"島本 隆"}]},"description":{"en":"In this paper, a novel complexity reduction algorithm for hierarchical B- picture of H.264/SVC is proposed. Observing some evaluations results, we find that due to the correlation among multi-layers, the search range selection and the mode selection process have much redundancy. In particular, the redundant search range and candidate modes have essential relations with the encoding layers. Using this feature, we propose a novel search range selection and mode selection algorithm that can significantly reduce the redundant search range and candidate modes. Simulation results show that the proposed method can achieve high computation complexity reduction rate with very slight PSNR loss.","ja":"訳: 本論文は，H.264/SVC階層Bピクチャの探索範囲を制御することにより，演算量を削減するアルゴリズムを提案する．検証結果より，階層間の高い相関性によりその探索範囲を適応的に変更し，大幅な演算量削減を実現した．参照ソフトウェアに実装しシミュレーションした結果，符号化効率にほとんど影響なく，大幅な演算量を削減できた．"},"publication_date":"2011-01","publication_name":{"en":"International Journal of Innovative Computing, Information and Control","ja":"International Journal of Innovative Computing, Information and Control"},"volume":"Vol.7","number":"No.1","starting_page":"445","ending_page":"457","languages":["eng"],"referee":true,"identifiers":{"issn":["1349-4198"]},"published_paper_type":"scientific_journal"},"priority":"input_data"}
line:38, {"insert":{"user_id":"5000080634","type":"published_papers","id":"13729373"},"force":{"see_also":[{"@id":"http://ci.nii.ac.jp/naid/40017404160/","label":"url"},{"@id":"https://cir.nii.ac.jp/crid/1521980703450448640/","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=218266","label":"url"}],"paper_title":{"en":"Hardware-Oriented Fast Estimation of Generated Bits for Rate-Distortion Optimization in H.264/AVC","ja":"Hardware-Oriented Fast Estimation of Generated Bits for Rate-Distortion Optimization in H.264/AVC"},"authors":{"en":[{"name":"Liu Yizhong"},{"name":"Song Tian"},{"name":"Kuniyasu Hiroki"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"劉 翊中"},{"name":"宋 天"},{"name":"國安 大樹"},{"name":"島本 隆"}]},"description":{"en":"In order to accelerate the RDO calculation, this paper proposes a new bits estimation algorithm Fast Estimation of Generated Bits (FEGB) and the corresponding architecture to fast estimate the generated bits instead of implementing the real entropy coding in the RDO process. The proposal is based on the entropy encode tool of context-adaptive variable length coding (CAVLC). By breaking the table lookup dependency for continuous syntax elements of a coefficients block and performing the paralleled processing, the rate estimation throughput of a 4x4 block per clock cycle is achieved. The proposed architecture can work on the frequency of 250MHz with 50K standard cells consumed.","ja":"訳: 本論文は，H.264/AVCの高速なRDO処理のアーキテクチャを提案する．提案アーキテクチャは，新たなFEGBモジュールにより，生成するビット数をCAVLCを用いて高速に予測した．提案手法を実装し，シミュレーションした結果，FEGBアーキテクチャは高速な予測性能を示した．提案アーキテクチャをVerilog HDLを用いて記述し合成した結果，最大動作周波数は250MHz となり，50Kの標準セルで実装可能であった．"},"publication_date":"2010-11","publication_name":{"en":"Journal of Signal Processing","ja":"Journal of Signal Processing"},"volume":"Vol.14","number":"No.6","starting_page":"443","ending_page":"450","languages":["eng"],"referee":true,"identifiers":{"issn":["1342-6230"]},"published_paper_type":"scientific_journal"},"priority":"input_data"}
line:39, {"insert":{"user_id":"5000080634","type":"published_papers","id":"13729374"},"force":{"see_also":[{"@id":"http://ci.nii.ac.jp/naid/10027637809/","label":"url"},{"@id":"https://cir.nii.ac.jp/crid/1390001206309716096/","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=214075","label":"url"}],"paper_title":{"en":"A High-Throughput Binary Arithmetic Coding Architecture for H.264/AVC CABAC","ja":"A High-Throughput Binary Arithmetic Coding Architecture for H.264/AVC CABAC"},"authors":{"en":[{"name":"Liu Yizhong"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"劉 翊中"},{"name":"宋 天"},{"name":"島本 隆"}]},"description":{"en":"In this paper, we propose a high-throughput binary arithmetic coding architecture for CABAC (Context Adaptive Binary Arithmetic Coding) that is one of the entropy coding tools used in the H.264/AVC main and high profiles. The binarization and context model selection are implemented in a proposed binarizer, in which a FIFO is used to pack the binarization results and output 4 bins in one clock. In order to improve the processing speed, the context variables access and update for 4 bins are paralleled and the pipeline path is balanced. This proposal can work at the clock frequency of 250MHz and takes up about 58K standard cells, 3.2Kbits register files and 27.6K bits ROM.","ja":"訳: 本論文は，H.264/AVCの算術符号化手法CABACに高いスループットを実現するアーキテクチャを提案している．提案アーキテクチャは，1サイクルに4ビンを処理できる高い処理性能を実現し，符号化速度とハードウェア面積のトレードオフを考慮し，最小限のハードウェア負荷で高い符号化性能を実現した．提案アーキテクチャをHDLを用いて実装し，58K標準セル，3.2Kレジスタと27.6KビットROMで実現できた．"},"publication_date":"2010-09-01","publication_name":{"en":"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences","ja":"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences"},"volume":"Vol.E93-A","number":"No.9","starting_page":"1594","ending_page":"1604","languages":["eng"],"referee":true,"identifiers":{"doi":["10.1587/transfun.E93.A.1594"],"issn":["0916-8508"]},"published_paper_type":"scientific_journal"},"priority":"input_data"}
line:40, {"insert":{"user_id":"5000080634","type":"published_papers","id":"13729375"},"force":{"see_also":[{"@id":"http://www.jsts.org/html/journal/journal_files/2010/03/Year2010Volume10_01_05.pdf","label":"url"},{"@id":"https://www.scopus.com/record/display.url?eid=2-s2.0-77952667456&origin=inward","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=208653","label":"url"}],"paper_title":{"en":"A Novel Spiral-Type Motion Estimation Architecture for H.264/AVC","ja":"A Novel Spiral-Type Motion Estimation Architecture for H.264/AVC"},"authors":{"en":[{"name":"Hirai Naoyuki"},{"name":"Song Tian"},{"name":"Liu Yizhong"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"Hirai Naoyuki"},{"name":"宋 天"},{"name":"Liu Yizhong"},{"name":"島本 隆"}]},"description":{"en":"New features of motion compensation, such as variable block size and multiple reference frames are introduced in H.264/AVC. In this paper, an efficient architecture for spiral-type motion estimation is proposed. First, we propose a hardware-friendly spiral search order. Then, an efficient PE architecture for ME is proposed to achieve the proposed search order. The improved PE enables one-pixel-move of the reference pixel data to top, bottom, right, and left by four ports for input and output. As the result of hardware implementation, the hardware cost is about 145k gates. Maximum clock frequency is 134 MHz in the case of FPGA (Xilinx Vertex5) implementation.","ja":"訳: 本論文は，H.264/AVCの動き探索処理に注目し，高速かつ小面積なハードウェアアーキテクチャを提案している．ハードウェアの面積増加が少ないスパイラル探索を提案し，スパイラル探索に適する上下左右シフトが可能な処理モジュールを提案し，小面積アーキテクチャを実現した．提案手法をFPGA (Xilinx Vertex5)に実装しシミュレーションした結果，145Kゲートで実現でき，最大動作周波数は134MHzとなった．"},"publication_date":"2010-03","publication_name":{"en":"Journal of Semiconductor Technology and Science","ja":"Journal of Semiconductor Technology and Science"},"volume":"Vol.10","number":"No.1","starting_page":"37","ending_page":"44","languages":["eng"],"referee":true,"identifiers":{"doi":["10.5573/JSTS.2010.10.1.037"],"issn":["1598-1657"]},"published_paper_type":"scientific_journal"},"priority":"input_data"}
line:41, {"insert":{"user_id":"5000080634","type":"published_papers","id":"13729376"},"force":{"see_also":[{"@id":"https://ci.nii.ac.jp/naid/40016925758/","label":"url"},{"@id":"https://cir.nii.ac.jp/crid/1521980705360610304/","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=201481","label":"url"}],"paper_title":{"en":"Frame Memory Access Method for High Resolution H.264/AVC Applications","ja":"Frame Memory Access Method for High Resolution H.264/AVC Applications"},"authors":{"en":[{"name":"Song Tian"},{"name":"Kishida Tomoyuki"},{"name":"Liu Yizhong"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"宋 天"},{"name":"Kishida Tomoyuki"},{"name":"Liu Yizhong"},{"name":"島本 隆"}]},"description":{"en":"In this paper, considering the features of frame memory access patterns in Rate-Distortion Optimization (RDO) process we introduce a novel memory access reduction method by estimating the motion information. In this work, the search center is estimated by adjacent motion vectors to decrease the redundancy of these reference data. In the proposed method, pixel data of only 9, 12, or 25 macroblocks are adaptively used as reference data for motion estimation. Simulation results show that the proposed method can realize up to 60% memory access reduction with almost no PSNR degradation.","ja":"訳: 本論文は，H.264/AVC 符号器の外部メモリへの帯域幅を削減する効率的なメモリインターフェイスアーキテクチャを提案している．従来，1マクロブロックの動き探索に49個のマクロブロック参照データのアクセスが必要となる．本研究では，参照データの削減により，メモリ帯域幅の削減を実現した．シミュレーション結果より，9∼25個の参照データのみをアクセスし，全体で60%のメモリアクセス量を削減できた．"},"publication_date":"2009-11","publication_name":{"en":"Journal of Signal Processing","ja":"Journal of Signal Processing"},"volume":"Vol.13","number":"No.6","starting_page":"469","ending_page":"475","languages":["eng"],"referee":true,"identifiers":{"issn":["1342-6230"]},"published_paper_type":"scientific_journal"},"priority":"input_data"}
line:42, {"insert":{"user_id":"5000080634","type":"published_papers","id":"13729377"},"force":{"see_also":[{"@id":"https://www.scopus.com/record/display.url?eid=2-s2.0-71149095841&origin=inward","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=200910","label":"url"}],"paper_title":{"en":"Coding Efficiency Improvement with Adaptive GOP Selection for H.264/SVC","ja":"Coding Efficiency Improvement with Adaptive GOP Selection for H.264/SVC"},"authors":{"en":[{"name":"Song Tian"},{"name":"Matsuoka Shinpei"},{"name":"Morigami Yoshitaka"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"宋 天"},{"name":"Matsuoka Shinpei"},{"name":"Morigami Yoshitaka"},{"name":"島本 隆"}]},"description":{"en":"In this paper, we present a novel group-of-picture (GOP) structure selection method for H.264/SVC. Proposed method adaptively defines the GOP structure by analyzing the input sequence characters. The accumulated difference of luminance pixel components is utilized to set a threshold for adaptive GOP size selection. Another scene change detection method is also proposed to reorganize the GOP structure. Different from previous adaptive GOP structure methods, the proposed method concentrates on the coding efficiency improvement on the basis of the Hierarchical B-picture structure. The simulation results show that the proposed method can improve up to 0.2dB for PSNR compared with fixed size GOP methods.","ja":"訳: 本論文は，H.264/SVCのGOP選択アルゴリズムを提案している．提案アルゴリズムは，入力画像シーケンスの特性を分析し，フレーム間の輝度値の差分値を利用してフレーム間の相関性を予測した．提案手法は，従来手法と異なり，階層的Bピクチャの符号化効率の向上を重視した手法である．本手法を実装し，シミュレーションした結果，従来手法より0.2dBのPSNRの増加を実現できた．"},"publication_date":"2009-11","publication_name":{"en":"International Journal of Innovative Computing, Information and Control","ja":"International Journal of Innovative Computing, Information and Control"},"volume":"Vol.5","number":"No.11(B)","starting_page":"4155","ending_page":"4165","languages":["eng"],"referee":true,"identifiers":{"issn":["1349-4198"]},"published_paper_type":"scientific_journal"},"priority":"input_data"}
line:43, {"insert":{"user_id":"5000080634","type":"published_papers","id":"13729378"},"force":{"see_also":[{"@id":"https://www.scopus.com/record/display.url?eid=2-s2.0-71149095016&origin=inward","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=200909","label":"url"}],"paper_title":{"en":"Fast Deblocking Filter Implementation Method for H.264/AVC","ja":"Fast Deblocking Filter Implementation Method for H.264/AVC"},"authors":{"en":[{"name":"Song Tian"},{"name":"Hayashi Yoshinori"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"宋 天"},{"name":"Hayashi Yoshinori"},{"name":"島本 隆"}]},"description":{"en":"In this work, a fast implementation method for deblocking filter of H.264/AVC and its architecture are proposed. The proposed method makes use of the correlation of the adjacent pixels to decrease the redundant processing cycles. Simulation results show that the average coding cycles for one macroblock is reduced to 170. It is fast than previous works that considered the least number of filtering cycles for one macroblock is 192. This work also provides an efficient architecture for the proposed method in which a parallel memory access solution and a novel comparison module are proposed. Implementation results show that the proposed architecture can be realized by about 30K gates.","ja":"訳: 本論文は，H.264/AVCのデブロッキングフィルタの高速アーキテクチャを提案している．提案手法は，隣接ピクセルの相関性を利用して演算サイクル数を削減した．提案手法を実装しシミュレーションした結果，従来手法で限界とされていた192サイクルから，平均170サイクルまで削減できた．提案アーキテクチャは，並列メモリアクセス手法と新たな比較用モジュールの提案により，わずか30Kゲートで実現できた．"},"publication_date":"2009-11","publication_name":{"en":"International Journal of Innovative Computing, Information and Control","ja":"International Journal of Innovative Computing, Information and Control"},"volume":"Vol.5","number":"No.11(A)","starting_page":"3983","ending_page":"3993","languages":["eng"],"referee":true,"identifiers":{"issn":["1349-4198"]},"published_paper_type":"scientific_journal"},"priority":"input_data"}
line:44, {"insert":{"user_id":"5000080634","type":"published_papers","id":"13729379"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=185182","label":"url"}],"paper_title":{"en":"Switching Entropy Coding Architecture for High Bitrate H.264/AVC Applications","ja":"Switching Entropy Coding Architecture for High Bitrate H.264/AVC Applications"},"authors":{"en":[{"name":"Song Tian"},{"name":"Liu Yizhong"},{"name":"Hayashi Yoshinori"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"宋 天"},{"name":"Liu Yizhong"},{"name":"Hayashi Yoshinori"},{"name":"島本 隆"}]},"description":{"en":"In this paper, novel entropy coding implementation method and its efficient architecture of H.264/AVC for high bitrate real time HDTV are proposed. The proposed method makes use of this switching bit to adaptively switch the CABAC to CAVLC at the coding peak of CABAC. We also proposed an efficient architecture to realize the proposed switching method. The experimental results show that the proposed method could realize fast coding at the bit generation peak and cut down the buffer consumption with very small bit rate increase.","ja":"訳: 本論文は，H.264/AVCの算術符号化手法においてCAVLCとCABAC両手法を適応的に選択する新たなアルゴリズムを提案する．提案アーキテクチャは，両手法を切り替えるビットを用いてCAVLCの高速性能とCABACの高い符号化効率を有効に利用し，最小限のハードウェア負荷で高い符号化性能を実現した．提案アーキテクチャは，符号の生成ピーク時にバッファへの圧迫がなく，算術符号化を高速に処理できた．"},"publication_date":"2008-11","publication_name":{"en":"Journal of Signal Processing","ja":"Journal of Signal Processing"},"volume":"Vol.12","number":"No.6","starting_page":"483","ending_page":"488","languages":["eng"],"referee":true,"identifiers":{"issn":["1342-6230"]},"published_paper_type":"scientific_journal"},"priority":"input_data"}
line:45, {"insert":{"user_id":"5000080634","type":"published_papers","id":"13729380"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=172460","label":"url"}],"paper_title":{"en":"Efficient Multistate Estimated Architecture of CABAC for H.264/AVC Encoder","ja":"Efficient Multistate Estimated Architecture of CABAC for H.264/AVC Encoder"},"authors":{"en":[{"name":"Song Tian"},{"name":"Yamada Atsushi"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"宋 天"},{"name":"Yamada Atsushi"},{"name":"島本 隆"}]},"description":{"en":"In this paper, a novel fast Context-Adaptive Binary Arithmetic Coder (CABAC) architecture and its efficient implementation method are proposed. The proposed architecture could achieve multi-bit arithmetic encoding in one cycle by introducing the multistate estimation (MSE) scheme, which enables multiple updates of the State, Range and Low in one cycle. Discussing the trade-off between coding speed and hardware consumption, we give an example solution to the two-state estimation architecture by which we could cut down half the number of coding cycles. The implementation results show that the proposed method could be implemented using about 20,000 gates.","ja":"訳: 本論文は，H.264/AVCの算術符号化手法CABACに高いスルーピットを実現するアーキテクチャを提案している．提案アーキテクチャは，符号化速度とハードウェア面積のトレードオフを考察し，最小限のハードウェア負荷で高い符号化性能を実現した．また，柔軟に本アーキテクチャを使用できるように複数の可能性について検討した．提案手法のハードウェアアーキテクチャはわずか20,000ゲートで実現できた．"},"publication_date":"2008-01","publication_name":{"en":"Journal of Signal Processing","ja":"Journal of Signal Processing"},"volume":"Vol.12","number":"No.1","starting_page":"65","ending_page":"71","languages":["eng"],"referee":true,"identifiers":{"issn":["1342-6230"]},"published_paper_type":"scientific_journal"},"priority":"input_data"}
line:46, {"insert":{"user_id":"5000080634","type":"published_papers","id":"13729381"},"force":{"see_also":[{"@id":"http://ci.nii.ac.jp/naid/40015763241/","label":"url"},{"@id":"https://cir.nii.ac.jp/crid/1523669554820813952/","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=165686","label":"url"}],"paper_title":{"en":"Efficient Variable Block Size Motion Estimation Architecture for Real-Time Rate Distortion Optimization of H.264/AVC Encoder","ja":"Efficient Variable Block Size Motion Estimation Architecture for Real-Time Rate Distortion Optimization of H.264/AVC Encoder"},"authors":{"en":[{"name":"Song Tian"},{"name":"Saito Kosuke"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"宋 天"},{"name":"Saito Kosuke"},{"name":"島本 隆"}]},"description":{"en":"In this paper, novel motion estimation architecture for H.264/AVC is proposed. To reduce the computational complexity of RDO calculation, we propose a TAD+top-down method that can efficiently reduce the number of candidate coding modes. The TAD+top-down method is a hardware-friendly method that can easily be implemented on the basis of traditional motion estimation architectures. The proposed architecture can support variable search- range motion estimation in the range of 0 to ±16. The experimental results show that the proposed method can reduce the computation complexity by about 80% without PSNR and bit rate loss compared with the reference software JM8.2.","ja":"訳: 本論文は，H.264/AVCの可変ブロックサイズの動き探索アルゴリズムを提案している．まず，空間方向のフレームのブロックサイズを用いて現在の符号化ブロックのサイズを予測する方法を提案した．次にトップダウン手法に基づいたブロックサイズ選択アルゴリズムを提案した．参照ソフトウェアJM8に実装しシミュレーションした結果，従来手法に比べ平均80%の演算量の削減を実現できた．"},"publication_date":"2007-11","publication_name":{"en":"Journal of Signal Processing","ja":"Journal of Signal Processing"},"volume":"Vol.11","number":"No.6","starting_page":"453","ending_page":"459","languages":["eng"],"referee":true,"identifiers":{"issn":["1342-6230"]},"published_paper_type":"scientific_journal"},"priority":"input_data"}
line:47, {"insert":{"user_id":"5000080634","type":"published_papers","id":"13729382"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=155459","label":"url"}],"paper_title":{"en":"Motion Area Estimated Motion Estimation with Triplet Search Patterns for H.264/AVC","ja":"Motion Area Estimated Motion Estimation with Triplet Search Patterns for H.264/AVC"},"authors":{"en":[{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"宋 天"},{"name":"島本 隆"}]},"description":{"en":"In this paper a fast motion estimation method for H.264/AVC named Triplet Search Motion Estimation (TS-ME) is proposed. The proposed algorithm separates the motion search process to several steps but with some new features. First, the proposed algorithm try to search the real motion area using proposed triplet patterns instead of some selected search points to avoid dropping into the local minimum. Then, in the localized motion area a novel 3-step motion search algorithm is performed. From the simulation results, motion estimation speed improved by a factor of up to 38 when using proposed algorithm than that of the reference software of H.264/AVC with ignorable picture quality loss.","ja":"訳: 本論文は，H.264/AVCの動き探索に新たな三角領域を基にした探索アルゴリズムを提案している．提案手法は従来手法と異なり，可能性の高い探索点を絞るのではなく，三角パターンを用いてベスト探索領域を決める．次に，決められた探索領域に新たな3ステップの探索手法を提案した．参照ソフトウェアに実装しシミュレーションした結果，高い符号化効率を実現するとともに演算量も大幅に削減できた．"},"publication_date":"2007-03","publication_name":{"en":"International Journal of Signal Processing(IJSP)","ja":"International Journal of Signal Processing(IJSP)"},"volume":"Vol.4","number":"No.1","starting_page":"67","ending_page":"76","languages":["eng"],"referee":true,"published_paper_type":"scientific_journal"},"priority":"input_data"}
line:48, {"insert":{"user_id":"5000080634","type":"published_papers","id":"13729383"},"force":{"see_also":[{"@id":"https://cir.nii.ac.jp/crid/1050845762814115456/","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=288409","label":"url"}],"paper_title":{"en":"携帯端末用低消費電力H.263 Version2コーデックコアのVLSI化設計","ja":"携帯端末用低消費電力H.263 Version2コーデックコアのVLSI化設計"},"authors":{"en":[{"name":"Song Tian"}],"ja":[{"name":"宋 天"}]},"description":{"en":"H.263 Version2 コーデックのVLSIアーキテクチャを提案した．携帯端末利用のため，レベル1オプションの小面積アーキテクチャを提案し，拡張Intra符号化モードとデブロッキングフィルタモードの必要機能を可能な限り1モジュールに集約することを考えた．これより，オプションモードの追加が該当モジュールの追加により実現できるため，アプリケーションに応じてハードウェアが容易にカスタム化できる構成となった．","ja":"H.263 Version2 コーデックのVLSIアーキテクチャを提案した．携帯端末利用のため，レベル1オプションの小面積アーキテクチャを提案し，拡張Intra符号化モードとデブロッキングフィルタモードの必要機能を可能な限り1モジュールに集約することを考えた．これより，オプションモードの追加が該当モジュールの追加により実現できるため，アプリケーションに応じてハードウェアが容易にカスタム化できる構成となった．"},"publication_date":"2002-05","publication_name":{"en":"情報処理学会誌","ja":"情報処理学会誌"},"volume":"Vol.43","number":"No.5","starting_page":"1161","ending_page":"1170","languages":["jpn"],"referee":true,"published_paper_type":"scientific_journal"},"priority":"input_data"}
line:49, {"insert":{"user_id":"5000080634","type":"published_papers","id":"13729384"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=189690","label":"url"}],"paper_title":{"en":"H.264/SVCにおけるEnhancementレイヤー符号化時の動き探索範囲の最適化に関する研究","ja":"H.264/SVCにおけるEnhancementレイヤー符号化時の動き探索範囲の最適化に関する研究"},"authors":{"en":[{"name":"Katayama Takafumi"},{"name":"森上 義崇"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"片山 貴文"},{"name":"森上 義崇"},{"name":"宋 天"},{"name":"島本 隆"}]},"description":{"en":"H.264/SVCは時間・空間・品質のスケーラビリティを1つのビットストリームで提供できる．本稿では，その中の空間スケーラビリティに着目し，Enhancementレイヤー符号化時に符号化済Baseレイヤーの動きベクトルを用いた探索中心の改良を提案した．そしてそれに基づく探索範囲の適応的制御手法を提案した．シミュレーション結果より，演算量を65∼75%削減できることを示した．","ja":"H.264/SVCは時間・空間・品質のスケーラビリティを1つのビットストリームで提供できる．本稿では，その中の空間スケーラビリティに着目し，Enhancementレイヤー符号化時に符号化済Baseレイヤーの動きベクトルを用いた探索中心の改良を提案した．そしてそれに基づく探索範囲の適応的制御手法を提案した．シミュレーション結果より，演算量を65∼75%削減できることを示した．"},"publication_date":"2009-04-20","publication_name":{"en":"電子情報通信学会 回路とシステム軽井沢ワークショップ","ja":"電子情報通信学会 回路とシステム軽井沢ワークショップ"},"number":"No.22","starting_page":"136","ending_page":"141","languages":["jpn"],"published_paper_type":"research_institution"},"priority":"input_data"}
line:50, {"insert":{"user_id":"5000080634","type":"published_papers","id":"13729385"},"force":{"see_also":[{"@id":"http://ci.nii.ac.jp/naid/40016083578/","label":"url"},{"@id":"https://cir.nii.ac.jp/crid/1520572359800730880/","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=175036","label":"url"}],"paper_title":{"en":"H.264/SVCにおける適応的GOPサイズを用いた符号化効率改善手法の検討","ja":"H.264/SVCにおける適応的GOPサイズを用いた符号化効率改善手法の検討"},"authors":{"en":[{"name":"松岡 真平"},{"name":"森上 義崇"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"松岡 真平"},{"name":"森上 義崇"},{"name":"宋 天"},{"name":"島本 隆"}]},"description":{"en":"H.264/SVCは時間・空間・品質のスケーラビリティを1つのビットストリームで提供できる．本稿では，時間スケーラビリティを実現する階層Bピクチャに着目し，動きの激しさによって符号化効率の良いGOPサイズが異なることを示し，適応的なGOPサイズ選択手法を提案した．また，シーンチェンジにおける符号化効率損失の対応策も提案した．シミュレーションより，本手法が符号化効率改善に有効であることを示した．","ja":"H.264/SVCは時間・空間・品質のスケーラビリティを1つのビットストリームで提供できる．本稿では，時間スケーラビリティを実現する階層Bピクチャに着目し，動きの激しさによって符号化効率の良いGOPサイズが異なることを示し，適応的なGOPサイズ選択手法を提案した．また，シーンチェンジにおける符号化効率損失の対応策も提案した．シミュレーションより，本手法が符号化効率改善に有効であることを示した．"},"publication_date":"2008-04-21","publication_name":{"en":"電子情報通信学会 回路とシステム軽井沢ワークショップ","ja":"電子情報通信学会 回路とシステム軽井沢ワークショップ"},"number":"No.21","starting_page":"131","ending_page":"136","languages":["jpn"],"published_paper_type":"research_institution"},"priority":"input_data"}
line:51, {"insert":{"user_id":"5000080634","type":"published_papers","id":"13729386"},"force":{"see_also":[{"@id":"http://ci.nii.ac.jp/naid/40015884358/","label":"url"},{"@id":"https://cir.nii.ac.jp/crid/1520853834767316480/","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=157285","label":"url"}],"paper_title":{"en":"MPEG-2/H.264トランスコーダにおける低演算量動き探索手法","ja":"MPEG-2/H.264トランスコーダにおける低演算量動き探索手法"},"authors":{"en":[{"name":"橋本 慶宏"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"橋本 慶宏"},{"name":"宋 天"},{"name":"島本 隆"}]},"description":{"en":"本稿では，MPEG-2/H.264トランスコーダの動き探索の演算量削減手法を提案する．まず，ビットストリームを復号する際に得られるSAD値を用い，適応的にH.264/AVCにおける符号化ブロックサイズを決定する手法を提案した．さらに，ビットストリームより得られる動きベクトルを用い，探索範囲の適応的縮小手法を提案した．シミュレーション結果より，約70∼90%の動き探索の演算量削減が達成できた．","ja":"本稿では，MPEG-2/H.264トランスコーダの動き探索の演算量削減手法を提案する．まず，ビットストリームを復号する際に得られるSAD値を用い，適応的にH.264/AVCにおける符号化ブロックサイズを決定する手法を提案した．さらに，ビットストリームより得られる動きベクトルを用い，探索範囲の適応的縮小手法を提案した．シミュレーション結果より，約70∼90%の動き探索の演算量削減が達成できた．"},"publication_date":"2007-04-24","publication_name":{"en":"電子情報通信学会 回路とシステム軽井沢ワークショップ","ja":"電子情報通信学会 回路とシステム軽井沢ワークショップ"},"number":"No.20","starting_page":"603","ending_page":"608","languages":["jpn"],"published_paper_type":"research_institution"},"priority":"input_data"}
line:52, {"insert":{"user_id":"5000080634","type":"published_papers","id":"13729387"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=193005","label":"url"}],"paper_title":{"en":"H.263 Version2コ―デックコアのVLSI化設計","ja":"H.263 Version2コ―デックコアのVLSI化設計"},"authors":{"en":[{"name":"Song Tian"},{"name":"宋 学燮"},{"name":"藤田 玄"},{"name":"尾上 孝雄"},{"name":"白川 功"}],"ja":[{"name":"宋 天"},{"name":"宋 学燮"},{"name":"藤田 玄"},{"name":"尾上 孝雄"},{"name":"白川 功"}]},"description":{"en":"H.263 Version2 コーデックのVLSIアーキテクチャを提案した．携帯端末利用のため，レベル1オプションの小面積アーキテクチャを提案し，拡張Intra符号化モードとデブロッキングフィルタモードの必要機能を可能な限り1モジュールに集約することを考えた．これより，オプションモードの追加が該当モジュールの追加により実現できるため，アプリケーションに応じてハードウェアが容易にカスタム化できる構成となった．","ja":"H.263 Version2 コーデックのVLSIアーキテクチャを提案した．携帯端末利用のため，レベル1オプションの小面積アーキテクチャを提案し，拡張Intra符号化モードとデブロッキングフィルタモードの必要機能を可能な限り1モジュールに集約することを考えた．これより，オプションモードの追加が該当モジュールの追加により実現できるため，アプリケーションに応じてハードウェアが容易にカスタム化できる構成となった．"},"publication_date":"2001-04-23","publication_name":{"en":"電子情報通信学会 回路とシステム軽井沢ワークショップ","ja":"電子情報通信学会 回路とシステム軽井沢ワークショップ"},"number":"No.14","starting_page":"561","ending_page":"566","languages":["jpn"],"published_paper_type":"research_institution"},"priority":"input_data"}
line:53, {"insert":{"user_id":"5000080634","type":"published_papers","id":"13729388"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=346521","label":"url"}],"paper_title":{"en":"Saliency-Detection-Based Quantization Parameter Setting Method for HEVC","ja":"注目領域検出を用いた符号化アルゴリズムに関する研究"},"authors":{"en":[{"name":"Katayama Takafumi"},{"name":"Tanaka Hiroki"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"片山 貴文"},{"name":"田中 宏樹"},{"name":"宋 天"},{"name":"島本 隆"}]},"description":{"en":"H.265/HEVCは前動画像符号化規格のH.264/AVCと比較して，約2倍の圧縮性能を有する．しかし，今後は4K/8Kのような超高精細映像が普及することから，さらなる符号化効率の改善が期待される．本研究では，HEVCのさらなる符号化効率向上のために，注目領域検出手法を組み合わせることで，主観評価に影響を与えない映像品質を実現し，符号化量(Bit-rate)を平均11%削減した．","ja":"H.265/HEVCは前動画像符号化規格のH.264/AVCと比較して，約2倍の圧縮性能を有する．しかし，今後は4K/8Kのような超高精細映像が普及することから，さらなる符号化効率の改善が期待される．本研究では，HEVCのさらなる符号化効率向上のために，注目領域検出手法を組み合わせることで，主観評価に影響を与えない映像品質を実現し，符号化量(Bit-rate)を平均11%削減した．"},"publication_date":"2018-10-12","publication_name":{"en":"IEEJ Transactions on Electronics, Information and Systems","ja":"電気学会論文誌C (電子，情報，システム部門誌)"},"volume":"Vol.138","number":"No.10","starting_page":"1185","ending_page":"1186","languages":["jpn"],"identifiers":{"doi":["10.1541/ieejeiss.138.1185"],"issn":["1348-8155"]},"published_paper_type":"scientific_journal"},"priority":"input_data"}
line:54, {"insert":{"user_id":"5000080634","type":"published_papers","id":"13729389"},"force":{"see_also":[{"@id":"http://ci.nii.ac.jp/naid/130005268124/","label":"url"},{"@id":"https://repo.lib.tokushima-u.ac.jp/ja/110596","label":"url"},{"@id":"https://cir.nii.ac.jp/crid/1390282679355792512/","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=321502","label":"url"}],"paper_title":{"en":"Fast Coding Unit Size Decision Based on Probabilistic Graphical Model in High Efficiency Video Coding Inter Prediction","ja":"Fast Coding Unit Size Decision Based on Probabilistic Graphical Model in High Efficiency Video Coding Inter Prediction"},"authors":{"en":[{"name":"Jiang Xiantao"},{"name":"Song Tian"},{"name":"Shi Wen"},{"name":"Katayama Takafumi"},{"name":"Shimamoto Takashi"},{"name":"Wang Lisheng"}],"ja":[{"name":"蒋 先涛"},{"name":"宋 天"},{"name":"石 文"},{"name":"片山 貴文"},{"name":"島本 隆"},{"name":"王 力生"}]},"description":{"en":"本論文は，HEVCの画面内符号化における確率モデルを用いた高速CUサイズ決定アルゴリズムを提案した．提案手法は，Markov Random Fields(MRF)モデルを用いてCBF情報を用いた分割/統合決定アルゴリズムであり，参照ソフトウェアHM12.0に実装しシミュレーションした結果，従来手法に比べ画質の劣化がほとんどなく，平均53%以上の高速処理を実現した．","ja":"本論文は，HEVCの画面内符号化における確率モデルを用いた高速CUサイズ決定アルゴリズムを提案した．提案手法は，Markov Random Fields(MRF)モデルを用いてCBF情報を用いた分割/統合決定アルゴリズムであり，参照ソフトウェアHM12.0に実装しシミュレーションした結果，従来手法に比べ画質の劣化がほとんどなく，平均53%以上の高速処理を実現した．"},"publication_date":"2016-11","publication_name":{"en":"IEICE Transactions on Information and Systems","ja":"IEICE Transactions on Information and Systems"},"volume":"Vol.E99-D","number":"No.11","starting_page":"2836","ending_page":"2839","languages":["eng"],"identifiers":{"doi":["10.1587/transinf.2015EDL8237"],"issn":["0916-8532"]},"published_paper_type":"scientific_journal"},"priority":"input_data"}
line:55, {"insert":{"user_id":"5000080634","type":"published_papers","id":"13729390"},"force":{"see_also":[{"@id":"https://www.scopus.com/record/display.url?eid=2-s2.0-84856949031&origin=inward","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=243735","label":"url"}],"paper_title":{"en":"Fast Inter-layer Motion Estimation for Spatial Scalability of H.264/SVC","ja":"Fast Inter-layer Motion Estimation for Spatial Scalability of H.264/SVC"},"authors":{"en":[{"name":"Ishikura Naoyuki"},{"name":"Takei Kentaro"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"石倉 直幸"},{"name":"武井 健太郎"},{"name":"宋 天"},{"name":"島本 隆"}]},"description":{"en":"In this paper, we propose an improved low complexity algorithm for spatial scalability of H.264/SVC on the basis of the motions in the sequences. First, verification is performed to confirm the redundancy of the previous motion estimation process of H.264/SVC. Then, based on the evaluation results we propose an improved algorithm for our previous work that only focuses on the complexity reduction of enhancement layer. The proposed algorithm can decrease the computation complexity of the enhancement layer using the inter layer motion prediction. The simulation results show that the proposed algorithm can achieve over 95% computation complexity reduction comparing to the original JSVM algorithm.","ja":"訳: 本論文は，H.264/SVCインターレイヤ予測に演算量削減アルゴリズムを提案している．様々な検証結果よりエンハンスメントレイヤ演算量削減の効果が大きいため，先行研究の演算量削減手法を改良し，さらにベースレイヤの演算量削減手法も提案した．参照ソフトウェアJSVMに実装しシミュレーションした結果，従来手法に比べ，符号化効率にほとんど影響なく，演算量を95%削減できた．"},"publication_date":"2012-02","publication_name":{"en":"ICIC Express Letters","ja":"ICIC Express Letters"},"volume":"Vol.6","number":"No.2","starting_page":"335","ending_page":"340","languages":["eng"],"identifiers":{"issn":["1881-803X"]},"published_paper_type":"scientific_journal"},"priority":"input_data"}
line:56, {"insert":{"user_id":"5000080634","type":"published_papers","id":"13729391"},"force":{"see_also":[{"@id":"https://www.scopus.com/record/display.url?eid=2-s2.0-77956933270&origin=inward","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=214186","label":"url"}],"paper_title":{"en":"Complexity Reduction Algorithm for Enhancement Layer of H.264/SVC","ja":"Complexity Reduction Algorithm for Enhancement Layer of H.264/SVC"},"authors":{"en":[{"name":"Takei Kentaro"},{"name":"Katayama Takafumi"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"武井 健太郎"},{"name":"片山 貴文"},{"name":"宋 天"},{"name":"島本 隆"}]},"description":{"en":"The inter-layer prediction of H.264/SVC can help to improve the coding efficiency as well as the computation complexity. Proposed algorithm focuses on the reduction of the candidate modes by making use of the correlations of the encoding cost between the base layer and enhancement layers. For macroblock with collocated macroblock coded by INTRA or INTER type, two algorithms are proposed, respectively. Both algorithms efficiently decrease the redundant candidate modes by estimating from the base layer coding information. The experiment results show that proposed algorithm can significantly reduce redundant computation complexity with almost no coding efficiency loss.","ja":"訳: 本論文は，H.264/SVCインターレイヤ予測のモード選択手法を提案している．提案手法は，符号化コストの相関性を利用して予測用候補モードを削減し，演算量削減を図った．イントラモードとインターモードの候補モードに対し，新たなアルゴリズムを提案し，その組み合わせで演算量削減を実現した．参照ソフトウェアに実装しシミュレーションした結果，符号化効率にほとんど影響なく，大幅な演算量が削減できた．"},"publication_date":"2010-10","publication_name":{"en":"ICIC Express Letters","ja":"ICIC Express Letters"},"volume":"Vol.4","number":"No.5(B)","starting_page":"1965","ending_page":"1972","languages":["eng"],"identifiers":{"issn":["1881-803X"]},"published_paper_type":"scientific_journal"},"priority":"input_data"}
line:57, {"insert":{"user_id":"5000080634","type":"published_papers","id":"13729392"},"force":{"see_also":[{"@id":"https://www.scopus.com/record/display.url?eid=2-s2.0-77956698519&origin=inward","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=214185","label":"url"}],"paper_title":{"en":"Efficient Deblocking Filter Architecture for High-Resolution Applications of H.264/AVC","ja":"Efficient Deblocking Filter Architecture for High-Resolution Applications of H.264/AVC"},"authors":{"en":[{"name":"Akita Tomohiro"},{"name":"Hirai Naoyuki"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"秋田 朋洋"},{"name":"平井 直行"},{"name":"宋 天"},{"name":"島本 隆"}]},"description":{"en":"This paper presents an efficient deblocking-filter architecture for high-resolution applications of H.264/AVC. In this work, we try to reduce the redundant filtering process in the case of high-resolution applications with low quantization parameter (QP). We early terminate filtering process to cut down power consumption by detecting the case when all the boundary strength (BS) of 4×4 blocks for one macroblock are zero. An efficient architecture that can realize these two proposals is also proposed. Simulation results show that there is a maximum 90% reduction in the filtering calculations and 87% of BS calculation. Low power implementation can be realized with the proposed architecture.","ja":"訳: 本論文は，高解像度H.264/AVCのデブロッキングフィルタの高速アーキテクチャを提案している．提案手法は，フィルタリング処理のサイクル数を削減し，全体の消費電力の削減を目標とした．BS処理に冗長があるため，BS処理の必要性をあらかじめ計算し，BS処理のサイクル数を削減した．提案手法を実装しシミュレーションした結果，最大90%のフィルタ処理削減と87%のBS処理サイクル数削減を実現した．"},"publication_date":"2010-10","publication_name":{"en":"ICIC Express Letters","ja":"ICIC Express Letters"},"volume":"Vol.4","number":"No.5(A)","starting_page":"1709","ending_page":"1715","languages":["eng"],"identifiers":{"issn":["1881-803X"]},"published_paper_type":"scientific_journal"},"priority":"input_data"}
line:58, {"insert":{"user_id":"5000080634","type":"published_papers","id":"13729393"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=194701","label":"url"}],"paper_title":{"en":"Low Complexity Mode Selection Method for Hierarchical B-picture of H.264/SVC","ja":"Low Complexity Mode Selection Method for Hierarchical B-picture of H.264/SVC"},"authors":{"en":[{"name":"Hamamoto Takaaki"},{"name":"Katayama Takafumi"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"Hamamoto Takaaki"},{"name":"片山 貴文"},{"name":"宋 天"},{"name":"島本 隆"}]},"description":{"en":"In this paper, a novel mode selection method for hierarchical B-picture of H.264/SVC is proposed. Observing the correlation in multi-layer structures, we find that the mode selection process has much redundancy. In particular, the redundant modes have essential relation with the encoding layers. On the basis of this feature, we propose a novel mode selection method that can significantly reduce the redundant candidate modes. Simulation results show that the proposed method can achieve high computation complexity with very slight PSNR loss.","ja":"訳: 本論文は，H.264/SVCの階層的Bピクチャのモード選択手法を提案している．提案手法は，各階層間のモードの相関関係を利用し，符号化モードの削減を実現した．特に，各階層において冗長な符号化モードを分析し，冗長性を削減した．これらの特徴を利用し，新たなモード選択アルゴリズムを提案した．参照ソフトウェアに実装しシミュレーションした結果，符号化効率にほとんど影響なく，大幅に演算量を削減できた．"},"publication_date":"2009-12","publication_name":{"en":"ICIC Express Letters","ja":"ICIC Express Letters"},"volume":"Vol.3","number":"No.4(A)","starting_page":"1179","ending_page":"1184","languages":["eng"],"published_paper_type":"scientific_journal"},"priority":"input_data"}
line:59, {"insert":{"user_id":"5000080634","type":"published_papers","id":"13729394"},"force":{"see_also":[{"@id":"http://ci.nii.ac.jp/naid/130000088167/","label":"url"},{"@id":"https://cir.nii.ac.jp/crid/1390001205214762624/","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=190590","label":"url"}],"paper_title":{"en":"H.264/AVC deblocking filter based on motion activity in video sequences","ja":"H.264/AVC deblocking filter based on motion activity in video sequences"},"authors":{"en":[{"name":"Raja Gulistan"},{"name":"Mirza Javed Muhammad"},{"name":"Song Tian"}],"ja":[{"name":"Raja Gulistan"},{"name":"Mirza Javed Muhammad"},{"name":"宋 天"}]},"description":{"en":"A new approach of H.264/AVC deblocking filter based on motion activity in video sequences is proposed. Based on sum of motion vectors the thresholds have been set through experimentation for categorizing different sequences. In this approach, a modified deblocking filter is used for low to moderate motion video sequences. Various simulations are conducted to evaluate the candidacy of the anticipated technique. The subjective and objective results are in conformity of the original H.264/AVC deblocking filter for low and moderate motion video sequences. A significant reduction in average number of operations is achieved without losing quality of the video.","ja":"A new approach of H.264/AVC deblocking filter based on motion activity in video sequences is proposed. Based on sum of motion vectors the thresholds have been set through experimentation for categorizing different sequences. In this approach, a modified deblocking filter is used for low to moderate motion video sequences. Various simulations are conducted to evaluate the candidacy of the anticipated technique. The subjective and objective results are in conformity of the original H.264/AVC deblocking filter for low and moderate motion video sequences. A significant reduction in average number of operations is achieved without losing quality of the video."},"publication_date":"2008-05-10","publication_name":{"en":"IEICE Electronics Express","ja":"IEICE Electronics Express"},"volume":"Vol.5","number":"No.19","starting_page":"809","ending_page":"814","languages":["eng"],"identifiers":{"doi":["10.1587/elex.5.809"],"issn":["1349-2543"]},"published_paper_type":"scientific_journal"},"priority":"input_data"}
line:60, {"insert":{"user_id":"5000080634","type":"published_papers","id":"13729395"},"force":{"see_also":[{"@id":"http://ci.nii.ac.jp/naid/130000087193/","label":"url"},{"@id":"https://cir.nii.ac.jp/crid/1390282680189865088/","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=175703","label":"url"}],"paper_title":{"en":"Fast Frame Memory Access Method for H.264/AVC","ja":"Fast Frame Memory Access Method for H.264/AVC"},"authors":{"en":[{"name":"Song Tian"},{"name":"Kishida Tomoyuki"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"宋 天"},{"name":"Kishida Tomoyuki"},{"name":"島本 隆"}]},"description":{"en":"This paper presents an efficient memory access interface architecture for H.264/AVC encoder. In the implementation of H.264/AVC encoder, the bandwidth compression of frame memory becomes a challenging issue due to some bandwidth intensive coding tools. In this work, by analyzing the memory access patterns of each coding function module of H.264/AVC, an efficient memory access method for the Direct Memory Access (DMA) module is proposed. The proposed method carefully designed an efficient memory mapping method to decrease the memory response delay. Simulation results show that over 50% memory access cycles can be saved by the proposed method.","ja":"訳: 本論文は，H.264/AVC 符号器を実装する際に外部メモリへの帯域幅を削減するために効率的なメモリインターフェイスアーキテクチャを提案している．動き探索，デブロッキングフィルタ，イントラ予測などの機能モジュールのメモリ探索パターンを分析し，その特徴に適したメモリインターフェイスアーキテクチャを提案した．シミュレーション結果より，従来手法に比べ50%のメモリアクセス量を削減できた．"},"publication_date":"2008-05-10","publication_name":{"en":"IEICE Electronics Express","ja":"IEICE Electronics Express"},"volume":"Vol.5","number":"No.9","starting_page":"344","ending_page":"348","languages":["eng"],"identifiers":{"doi":["10.1587/elex.5.344"],"issn":["1349-2543"]},"published_paper_type":"scientific_journal"},"priority":"input_data"}
line:61, {"insert":{"user_id":"5000080634","type":"published_papers","id":"13729396"},"force":{"see_also":[{"@id":"http://ci.nii.ac.jp/naid/130000088508/","label":"url"},{"@id":"https://cir.nii.ac.jp/crid/1390282680191396480/","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=153732","label":"url"}],"paper_title":{"en":"Reference Frame Data Compression Method for H.264/AVC","ja":"Reference Frame Data Compression Method for H.264/AVC"},"authors":{"en":[{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"宋 天"},{"name":"島本 隆"}]},"description":{"en":"In this paper, a novel frame memory compression method for the H.264/AVC is proposed. Proposed method introduce DAP (Differential of Adjacent Pixel) and Huffman coding to the original image data between the frame memory interface and the image coding process. Simulation results shows that this method can achieve not only a stable compression rate but also realize a lossless compression which cause no additional information loss to the coding process. Furthermore, the proposed method is hardware-friendly and no further delay during the memory access period. The proposed method is realized using only 7,000 gates.","ja":"訳: 本論文は，外部メモリへの帯域幅を削減するためのデータ圧縮技術を提案する．提案手法はまず転送するブロックデータのDAP (Differential of Adjacent Pixel) を計算し，次にハーフマン符号化を行う．参照ソフトウェアに実装しシミュレーションした結果，提案手法は安定した圧縮率を実現するとともに，無損失な圧縮を実現した．また，提案手法はハードウェア実装に向き，わずか7,000ゲートで実現できた．"},"publication_date":"2007-02-10","publication_name":{"en":"IEICE Electronics Express","ja":"IEICE Electronics Express"},"volume":"Vol.4","number":"No.3","starting_page":"121","ending_page":"126","languages":["eng"],"identifiers":{"doi":["10.1587/elex.4.121"],"issn":["1349-2543"]},"published_paper_type":"scientific_journal"},"priority":"input_data"}
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line:46, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869135"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=341994","label":"url"}],"presentation_title":{"en":"Fast PU Size Decision Algorithm Using RD-Cost and Depth Dispersion for Depth Intra Coding of 3D-HEVC","ja":"Fast PU Size Decision Algorithm Using RD-Cost and Depth Dispersion for Depth Intra Coding of 3D-HEVC"},"presenters":{"en":[{"name":"Yusa Shota"},{"name":"Katayama Takafumi"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"Yusa Shota"},{"name":"片山 貴文"},{"name":"宋 天"},{"name":"島本 隆"}]},"event":{"en":"Proceedings of Taiwan and Japan Conference on Circuits and Systems (TJCAS2018)","ja":"Proceedings of Taiwan and Japan Conference on Circuits and Systems (TJCAS2018)"},"publication_date":"2018-08-03","languages":["eng"],"location":{"en":"Taichung, Taiwan","ja":"Taichung, Taiwan"},"description":{"en":"本論文は，3D-HEVCの画面内符号化におけるRD-COSTと深度分散を用いたPUサイズ決定アルゴリズムを提案した．最も可能性の高いモードを高速探索し，ある程度候補を限定した後に，詳細な検索を行うアルゴリズムを提案した．提案手法を実装しシミュレーションした結果，最大41%の演算量削減を実現した．","ja":"本論文は，3D-HEVCの画面内符号化におけるRD-COSTと深度分散を用いたPUサイズ決定アルゴリズムを提案した．最も可能性の高いモードを高速探索し，ある程度候補を限定した後に，詳細な検索を行うアルゴリズムを提案した．提案手法を実装しシミュレーションした結果，最大41%の演算量削減を実現した．"},"is_international_presentation":true},"priority":"input_data"}
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line:53, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869142"},"force":{"see_also":[{"@id":"https://www.scopus.com/record/display.url?eid=2-s2.0-85048797519&origin=inward","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=335765","label":"url"}],"presentation_title":{"en":"Hardware-oriented Low Complexity Motion Estimation for HEVC","ja":"Hardware-oriented Low Complexity Motion Estimation for HEVC"},"presenters":{"en":[{"name":"Ito Yoshiki"},{"name":"Song Tian"},{"name":"Shi Wen"},{"name":"Katayama Takafumi"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"伊藤 良樹"},{"name":"宋 天"},{"name":"石 文"},{"name":"片山 貴文"},{"name":"島本 隆"}]},"event":{"en":"Proceedings of IEEE International Conference on Consumer Electronics(ICCE2018)","ja":"Proceedings of IEEE International Conference on Consumer Electronics(ICCE2018)"},"publication_date":"2018-01-13","languages":["eng"],"promoter":{"en":"IEEE","ja":"IEEE"},"location":{"en":"Las Vegas","ja":"Las Vegas"},"description":{"en":"本論文は，HEVCのハードウェア実装における低演算量動き探索アルゴリズムを提案する．空間領域と時間領域の動きベクトルの相関性を評価し，新規の探索中心予測アルゴリズムを提案し，それを用いた探索範囲選択アルゴリズムを提案した．提案手法を参照ソフトウェアHM16.7に実装しシミュレーションした結果，従来手法に比べ80%の高速符号化性能を実現した．","ja":"本論文は，HEVCのハードウェア実装における低演算量動き探索アルゴリズムを提案する．空間領域と時間領域の動きベクトルの相関性を評価し，新規の探索中心予測アルゴリズムを提案し，それを用いた探索範囲選択アルゴリズムを提案した．提案手法を参照ソフトウェアHM16.7に実装しシミュレーションした結果，従来手法に比べ80%の高速符号化性能を実現した．"},"is_international_presentation":true},"priority":"input_data"}
line:54, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869143"},"force":{"see_also":[{"@id":"https://www.scopus.com/record/display.url?eid=2-s2.0-85048832181&origin=inward","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=335763","label":"url"}],"presentation_title":{"en":"Early Mode Selection of High Resolution for HEVC Base on Bits-Mapping","ja":"Early Mode Selection of High Resolution for HEVC Base on Bits-Mapping"},"presenters":{"en":[{"name":"Kuroda Kazuki"},{"name":"Katayama Takafumi"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"黒田 一樹"},{"name":"片山 貴文"},{"name":"宋 天"},{"name":"島本 隆"}]},"event":{"en":"Proceedings of IEEE International Conference on Consumer Electronics(ICCE2018)","ja":"Proceedings of IEEE International Conference on Consumer Electronics(ICCE2018)"},"publication_date":"2018-01-13","languages":["eng"],"promoter":{"en":"IEEE","ja":"IEEE"},"location":{"en":"Las Vegas","ja":"Las Vegas"},"description":{"en":"本論文は，HEVCにおけるビットマップを用いた高解像度用高速モード選択アルゴリズムを提案した．検証結果からフレームの領域により生成ビットの偏りがあるため，この特徴を利用しフレームを8領域に分割し，生成するビットマップを予測し，これを用いた高速モード選択アルゴリズムを提案した．提案手法を参照ソフトウェアHM15.0に実装しシミュレーションした結果，従来手法に比べ画質の劣化がほとんどなく，平均50%の演算量削減を実現した．","ja":"本論文は，HEVCにおけるビットマップを用いた高解像度用高速モード選択アルゴリズムを提案した．検証結果からフレームの領域により生成ビットの偏りがあるため，この特徴を利用しフレームを8領域に分割し，生成するビットマップを予測し，これを用いた高速モード選択アルゴリズムを提案した．提案手法を参照ソフトウェアHM15.0に実装しシミュレーションした結果，従来手法に比べ画質の劣化がほとんどなく，平均50%の演算量削減を実現した．"},"is_international_presentation":true},"priority":"input_data"}
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line:56, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869145"},"force":{"see_also":[{"@id":"https://link.springer.com/chapter/10.1007%2F978-3-319-68121-4_30","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=334519","label":"url"}],"presentation_title":{"en":"A Coding Efficiency Improvement Algorithm for Future Video Coding","ja":"A Coding Efficiency Improvement Algorithm for Future Video Coding"},"presenters":{"en":[{"name":"Xiantao Jiang"},{"name":"XiaoFeng Wang"},{"name":"Yadong Yang"},{"name":"Song Tian"},{"name":"Wen Shi"},{"name":"Katayama Takafumi"}],"ja":[{"name":"Xiantao Jiang"},{"name":"XiaoFeng Wang"},{"name":"Yadong Yang"},{"name":"宋 天"},{"name":"Wen Shi"},{"name":"片山 貴文"}]},"event":{"en":"IFIP International Federation for Information Processing 2017","ja":"IFIP International Federation for Information Processing 2017"},"publication_date":"2017-10","languages":["eng"],"promoter":{"en":"Springer International Publishing AG","ja":"Springer International Publishing AG"},"location":{"en":"Shanghai","ja":"Shanghai"},"description":{"en":"本論文は，現在の符号化標準HEVCをベースとし，画面間予測に対して探索中心と探索範囲を改良した次世代動画像符号化のための高効率符号化アルゴリズムを提案した．まず，符号化中のCUの周辺動きベクトル情報を用いて高精度の動き探索中心決定アルゴリズムを提案し，更にその動きベクトル情報を用いて探索範囲を削減するアルゴリズムを提案した．提案アルゴリズムを実装し，シミュレーションした結果により，平均5.49%の符号化効率向上を実現した．","ja":"本論文は，現在の符号化標準HEVCをベースとし，画面間予測に対して探索中心と探索範囲を改良した次世代動画像符号化のための高効率符号化アルゴリズムを提案した．まず，符号化中のCUの周辺動きベクトル情報を用いて高精度の動き探索中心決定アルゴリズムを提案し，更にその動きベクトル情報を用いて探索範囲を削減するアルゴリズムを提案した．提案アルゴリズムを実装し，シミュレーションした結果により，平均5.49%の符号化効率向上を実現した．"},"is_international_presentation":true},"priority":"input_data"}
line:57, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869146"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=325614","label":"url"}],"presentation_title":{"en":"Coding Efficiency Improvement Algorithm for Inter-Layer Reference Prediction in SHVC","ja":"Coding Efficiency Improvement Algorithm for Inter-Layer Reference Prediction in SHVC"},"presenters":{"en":[{"name":"Tamura Koki"},{"name":"Katayama Takafumi"},{"name":"Shi Wen"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"Tamura Koki"},{"name":"片山 貴文"},{"name":"Shi Wen"},{"name":"宋 天"},{"name":"島本 隆"}]},"event":{"en":"Proceedings of International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC2017)","ja":"Proceedings of International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC2017)"},"publication_date":"2017-07-04","languages":["eng"],"location":{"en":"Busan","ja":"Busan"},"description":{"en":"本論文は，SHVCのインター符号化における高効率符号化アルゴリズムを提案した．SHVCのインターレイヤ符号化においてベースレイヤ情報をアップサンプリングする際のフィルタ処理を改良し，検証結果が優れたフィルタ2種を追加した．提案手法を参照ソフトウェアSHM11.0に実装しシミュレーションした結果，従来手法に比べ平均2%の符号化効率向上を実現した．","ja":"本論文は，SHVCのインター符号化における高効率符号化アルゴリズムを提案した．SHVCのインターレイヤ符号化においてベースレイヤ情報をアップサンプリングする際のフィルタ処理を改良し，検証結果が優れたフィルタ2種を追加した．提案手法を参照ソフトウェアSHM11.0に実装しシミュレーションした結果，従来手法に比べ平均2%の符号化効率向上を実現した．"},"is_international_presentation":true},"priority":"input_data"}
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line:77, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869166"},"force":{"see_also":[{"@id":"https://www.scopus.com/record/display.url?eid=2-s2.0-84959478536&origin=inward","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=295238","label":"url"}],"presentation_title":{"en":"Spatial Locality Based Supplemental Modes for Intra Prediction of HEVC","ja":"Spatial Locality Based Supplemental Modes for Intra Prediction of HEVC"},"presenters":{"en":[{"name":"Shi Wen"},{"name":"Jiang Xiantao"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"石 文"},{"name":"蒋 先涛"},{"name":"宋 天"},{"name":"島本 隆"}]},"event":{"en":"Proceedings of IEEE International Conference on Consumer Electronics(ICCE-Taiwan 2015)","ja":"Proceedings of IEEE International Conference on Consumer Electronics(ICCE-Taiwan 2015)"},"publication_date":"2015-06-06","languages":["eng"],"promoter":{"en":"IEEE","ja":"IEEE"},"location":{"en":"Taipei","ja":"Taipei"},"description":{"en":"本論文は，HEVCの画面内符号化において画素間の空間相関性を利用した新規符号化方式を提案した．符号化対象CUの画素に対し隣接4画素を4ブロックに分け，符号化済ブロックの情報を用いて残りのブロックを符号化する手法を提案し，使用する効率的なフィルタを提案した．提案手法を参照ソフトウェアJM12.1に実装しシミュレーションした結果，従来手法に比べ平均8.4%の符号化効率向上を実現した．","ja":"本論文は，HEVCの画面内符号化において画素間の空間相関性を利用した新規符号化方式を提案した．符号化対象CUの画素に対し隣接4画素を4ブロックに分け，符号化済ブロックの情報を用いて残りのブロックを符号化する手法を提案し，使用する効率的なフィルタを提案した．提案手法を参照ソフトウェアJM12.1に実装しシミュレーションした結果，従来手法に比べ平均8.4%の符号化効率向上を実現した．"},"is_international_presentation":true},"priority":"input_data"}
line:78, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869167"},"force":{"see_also":[{"@id":"https://www.scopus.com/record/display.url?eid=2-s2.0-84959487325&origin=inward","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=295237","label":"url"}],"presentation_title":{"en":"Merge Prediction Algorithm for Adaptive Parallel Improvement of High Efficiency Video Coding","ja":"Merge Prediction Algorithm for Adaptive Parallel Improvement of High Efficiency Video Coding"},"presenters":{"en":[{"name":"Jiang Xiantao"},{"name":"Song Tian"},{"name":"Shi Wen"},{"name":"Wang Lisheng"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"蒋 先涛"},{"name":"宋 天"},{"name":"石 文"},{"name":"Wang Lisheng"},{"name":"島本 隆"}]},"event":{"en":"Proceedings of IEEE International Conference on Consumer Electronics(ICCE-Taiwan 2015)","ja":"Proceedings of IEEE International Conference on Consumer Electronics(ICCE-Taiwan 2015)"},"publication_date":"2015-06-06","languages":["eng"],"promoter":{"en":"IEEE","ja":"IEEE"},"location":{"en":"Taipei","ja":"Taipei"},"description":{"en":"本論文は，GPUなど並列処理性能が高く要求される環境においてHEVCを実装する場合に，マージモードのアルゴリズムを改良することにより，並列処理性能を高めるアルゴリズムを提案した．処理単位CTUに対し，PUの動きベクトルをCTU周辺の動きベクトルより予測し，PU間の相関性を無くし，符号化効率への影響を最小限にする手法を提案した．提案手法を参照ソフトウェアHM12.0に実装しシミュレーションした結果，従来手法に比べわずか0.1%未満の符号化効率低下まで抑え，並列処理を可能にした．","ja":"本論文は，GPUなど並列処理性能が高く要求される環境においてHEVCを実装する場合に，マージモードのアルゴリズムを改良することにより，並列処理性能を高めるアルゴリズムを提案した．処理単位CTUに対し，PUの動きベクトルをCTU周辺の動きベクトルより予測し，PU間の相関性を無くし，符号化効率への影響を最小限にする手法を提案した．提案手法を参照ソフトウェアHM12.0に実装しシミュレーションした結果，従来手法に比べわずか0.1%未満の符号化効率低下まで抑え，並列処理を可能にした．"},"is_international_presentation":true},"priority":"input_data"}
line:79, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869168"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=291354","label":"url"}],"presentation_title":{"en":"Efficient Intra Coding for HEVC Based on Spatial Locality","ja":"Efficient Intra Coding for HEVC Based on Spatial Locality"},"presenters":{"en":[{"name":"Shi Wen"},{"name":"Jiang Xiantao"},{"name":"Song Tian"},{"name":"Leu Jenq-Shiou"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"石 文"},{"name":"蒋 先涛"},{"name":"宋 天"},{"name":"Leu Jenq-Shiou"},{"name":"島本 隆"}]},"event":{"en":"Proceedings of International Forum on Advanced Technologies (IFAT2015)","ja":"Proceedings of International Forum on Advanced Technologies (IFAT2015)"},"publication_date":"2015-03-09","languages":["eng"],"promoter":{"en":"Tokushima University","ja":"Tokushima University"},"location":{"en":"Tokushima","ja":"Tokushima"},"description":{"en":"本論文は，HEVCの画面内符号化における画素間の空間相関性を利用した新規符号化方式を提案した．符号化対象CUの画素に対し隣接4画素を4ブロックに分け，左上ブロックのみを符号化し，符号化済ブロックの情報を用いて残りのブロックを符号化した．提案手法を参照ソフトウェアJM12.1に実装しシミュレーションした結果，従来手法に比べ平均6%の符号化効率向上を実現した．","ja":"本論文は，HEVCの画面内符号化における画素間の空間相関性を利用した新規符号化方式を提案した．符号化対象CUの画素に対し隣接4画素を4ブロックに分け，左上ブロックのみを符号化し，符号化済ブロックの情報を用いて残りのブロックを符号化した．提案手法を参照ソフトウェアJM12.1に実装しシミュレーションした結果，従来手法に比べ平均6%の符号化効率向上を実現した．"},"is_international_presentation":true},"priority":"input_data"}
line:80, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869169"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=291353","label":"url"}],"presentation_title":{"en":"High Efficiency Inter CU Size Prediction Algorithm for HEVC","ja":"High Efficiency Inter CU Size Prediction Algorithm for HEVC"},"presenters":{"en":[{"name":"Jiang Xiantao"},{"name":"Song Tian"},{"name":"Leu Jenq-Shiou"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"蒋 先涛"},{"name":"宋 天"},{"name":"Leu Jenq-Shiou"},{"name":"島本 隆"}]},"event":{"en":"Proceedings of International Forum on Advanced Technologies (IFAT2015)","ja":"Proceedings of International Forum on Advanced Technologies (IFAT2015)"},"publication_date":"2015-03-09","languages":["eng"],"promoter":{"en":"Tokushima University","ja":"Tokushima University"},"location":{"en":"Tokushima","ja":"Tokushima"},"description":{"en":"本論文は，HEVCの画面間符号化において高効率CUサイズ決定アルゴリズムを提案した．符号化対象CUの周辺の動きベクトルを利用し，現在のCUに利用可能とする信頼度を評価し，その信頼度とMADを用いて総合的にCUサイズを決定するアルゴリズムを提案した．提案手法を参照ソフトウェアJM8に実装しシミュレーションした結果，従来手法に比べ平均42%の演算量の削減を実現した．","ja":"本論文は，HEVCの画面間符号化において高効率CUサイズ決定アルゴリズムを提案した．符号化対象CUの周辺の動きベクトルを利用し，現在のCUに利用可能とする信頼度を評価し，その信頼度とMADを用いて総合的にCUサイズを決定するアルゴリズムを提案した．提案手法を参照ソフトウェアJM8に実装しシミュレーションした結果，従来手法に比べ平均42%の演算量の削減を実現した．"},"is_international_presentation":true},"priority":"input_data"}
line:81, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869170"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=291352","label":"url"}],"presentation_title":{"en":"Received Signal Strength Indication(RSSI) Prediction-based Adaptive H.264/SVC Video Service on Smartphone","ja":"Received Signal Strength Indication(RSSI) Prediction-based Adaptive H.264/SVC Video Service on Smartphone"},"presenters":{"en":[{"name":"Leu Jenq-Shiou"},{"name":"Song Tian"}],"ja":[{"name":"Leu Jenq-Shiou"},{"name":"宋 天"}]},"event":{"en":"Proceedings of International Forum on Advanced Technologies","ja":"Proceedings of International Forum on Advanced Technologies"},"publication_date":"2015-03-09","invited":true,"languages":["eng"],"promoter":{"en":"Tokushima University","ja":"Tokushima University"},"description":{"en":"本論文は，携帯端末における受信信号強度によるH.264/SVC適応的ビデオ配信手法を提案した．携帯端末におけるビデオ通信の消費電力増大の問題に対し，通信状況を計測することにより低帯域の場合に適応的にビデオ配信量を抑えるアルゴリズムを提案した．提案手法を実装しシミュレーションを行った結果，提案手法は従来の手法に比べ平均10%の消費電力削減を実現できる．","ja":"本論文は，携帯端末における受信信号強度によるH.264/SVC適応的ビデオ配信手法を提案した．携帯端末におけるビデオ通信の消費電力増大の問題に対し，通信状況を計測することにより低帯域の場合に適応的にビデオ配信量を抑えるアルゴリズムを提案した．提案手法を実装しシミュレーションを行った結果，提案手法は従来の手法に比べ平均10%の消費電力削減を実現できる．"},"is_international_presentation":true},"priority":"input_data"}
line:82, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869171"},"force":{"see_also":[{"@id":"https://www.scopus.com/record/display.url?eid=2-s2.0-84937876981&origin=inward","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=288237","label":"url"}],"presentation_title":{"en":"Edge Information Based Fast Selection Algorithm for Intra Prediction of HEVC","ja":"Edge Information Based Fast Selection Algorithm for Intra Prediction of HEVC"},"presenters":{"en":[{"name":"Shi Wen"},{"name":"Jiang Xiantao"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"石 文"},{"name":"蒋 先涛"},{"name":"宋 天"},{"name":"島本 隆"}]},"event":{"en":"Proceedings of IEEE Asia Pacific Conference on Circuits & Systems(APCCAS2014)","ja":"Proceedings of IEEE Asia Pacific Conference on Circuits & Systems(APCCAS2014)"},"publication_date":"2014-11-17","languages":["eng"],"promoter":{"en":"IEEE","ja":"IEEE"},"location":{"en":"Okinawa","ja":"Okinawa"},"description":{"en":"New features of intra prediction in HEVC improves coding ef ciency, meanwhile, brings high computational complexity. This paper presents a fast algorithm for intra prediction of HEVC. An edge information based fast image preprocessing stage is designed. Based on the result of edge detection, reasonable PU size is decided ef ciently. Intra prediction mode selection optimization based on edge information also helps to achieve the goal of computational complexity reduction. Compared to the original HEVC, the result of the complexity reduction is over 27%, in the meantime, the increased BD-Rate and declining BD-PSNR is almost negligible.","ja":"New features of intra prediction in HEVC improves coding ef ciency, meanwhile, brings high computational complexity. This paper presents a fast algorithm for intra prediction of HEVC. An edge information based fast image preprocessing stage is designed. Based on the result of edge detection, reasonable PU size is decided ef ciently. Intra prediction mode selection optimization based on edge information also helps to achieve the goal of computational complexity reduction. Compared to the original HEVC, the result of the complexity reduction is over 27%, in the meantime, the increased BD-Rate and declining BD-PSNR is almost negligible."},"is_international_presentation":true},"priority":"input_data"}
line:83, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869172"},"force":{"see_also":[{"@id":"https://www.scopus.com/record/display.url?eid=2-s2.0-84937871412&origin=inward","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=288236","label":"url"}],"presentation_title":{"en":"AMVP Prediction Algorithm for Adaptive Parallel Improvement of HEVC","ja":"AMVP Prediction Algorithm for Adaptive Parallel Improvement of HEVC"},"presenters":{"en":[{"name":"Jiang Xiantao"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"},{"name":"Wang Lisheng"}],"ja":[{"name":"蒋 先涛"},{"name":"宋 天"},{"name":"島本 隆"},{"name":"Wang Lisheng"}]},"event":{"en":"Proceedings of IEEE Asia Pacific Conference on Circuits & Systems(APCCAS2014)","ja":"Proceedings of IEEE Asia Pacific Conference on Circuits & Systems(APCCAS2014)"},"publication_date":"2014-11-17","languages":["eng"],"promoter":{"en":"IEEE","ja":"IEEE"},"location":{"en":"Okinawa","ja":"Okinawa"},"description":{"en":"HEVC has been improved greatly including some parallel processing tools to achieve fast implementation on multi-core or many-core platforms. However, CU level parallel processing is still a challenging issue. In this paper, the relation among spatial motion candidates is analyzed firstly. Then, a parallelism spatial candidate list generation algorithm is proposed on the basis of the strong correlations among current prediction unit (PU), surrounding PUs and temporal correlated PUs. By evaluating the reliability of the motion vectors, the parallel granularity can be controlled adaptively. Experimental results show that the presented algorithm can achieve friendly parallel processing with only 0.26% BD-rate loss, based on the test model HM12.0.","ja":"HEVC has been improved greatly including some parallel processing tools to achieve fast implementation on multi-core or many-core platforms. However, CU level parallel processing is still a challenging issue. In this paper, the relation among spatial motion candidates is analyzed firstly. Then, a parallelism spatial candidate list generation algorithm is proposed on the basis of the strong correlations among current prediction unit (PU), surrounding PUs and temporal correlated PUs. By evaluating the reliability of the motion vectors, the parallel granularity can be controlled adaptively. Experimental results show that the presented algorithm can achieve friendly parallel processing with only 0.26% BD-rate loss, based on the test model HM12.0."},"is_international_presentation":true},"priority":"input_data"}
line:84, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869173"},"force":{"see_also":[{"@id":"https://www.scopus.com/record/display.url?eid=2-s2.0-84937839172&origin=inward","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=288235","label":"url"}],"presentation_title":{"en":"Temporal Prediction Improvement for Parallel Processing of HEVC","ja":"Temporal Prediction Improvement for Parallel Processing of HEVC"},"presenters":{"en":[{"name":"Jiang Xiantao"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"},{"name":"Shi Wen"},{"name":"Wang Lisheng"}],"ja":[{"name":"蒋 先涛"},{"name":"宋 天"},{"name":"島本 隆"},{"name":"石 文"},{"name":"Wang Lisheng"}]},"event":{"en":"Proceedings of IEEE Asia Pacific Conference on Circuits & Systems(APCCAS2014)","ja":"Proceedings of IEEE Asia Pacific Conference on Circuits & Systems(APCCAS2014)"},"publication_date":"2014-11-17","languages":["eng"],"promoter":{"en":"IEEE","ja":"IEEE"},"location":{"en":"Okinawa","ja":"Okinawa"},"description":{"en":"HEVC is based on a block-based hybrid coding architecture. Parallel processing is important tool to accelerate both on the encoder and decoder side. Advanced motion vector prediction (AMVP) is an efficient inter prediction tool in HEVC. However, neighbor block dependence in AMVP coding is major barrier for parallel processing. In this work, focusing on the parallel processing ability in HEVC, a parallel temporal prediction algorithm is proposed that make the encoder decide the temporal candidate once in a larger coding unit for all the sub-units. Experimental results demonstrate that the proposed algorithm realize parallel temporal prediction candidate with only 0.11% BD-rate loss, compared with the reference software model.","ja":"HEVC is based on a block-based hybrid coding architecture. Parallel processing is important tool to accelerate both on the encoder and decoder side. Advanced motion vector prediction (AMVP) is an efficient inter prediction tool in HEVC. However, neighbor block dependence in AMVP coding is major barrier for parallel processing. In this work, focusing on the parallel processing ability in HEVC, a parallel temporal prediction algorithm is proposed that make the encoder decide the temporal candidate once in a larger coding unit for all the sub-units. Experimental results demonstrate that the proposed algorithm realize parallel temporal prediction candidate with only 0.11% BD-rate loss, compared with the reference software model."},"is_international_presentation":true},"priority":"input_data"}
line:85, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869174"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=288415","label":"url"}],"presentation_title":{"en":"Hardware Architecture of the Fast Mode Decision Algorithm for H.265/HEVC","ja":"Hardware Architecture of the Fast Mode Decision Algorithm for H.265/HEVC"},"presenters":{"en":[{"name":"Zhao Wenjun"},{"name":"Onoe Takao"},{"name":"Song Tian"}],"ja":[{"name":"Zhao Wenjun"},{"name":"Onoe Takao"},{"name":"宋 天"}]},"event":{"en":"Proceedings of International Conference of Image Processing (ICIP2014)","ja":"Proceedings of International Conference of Image Processing (ICIP2014)"},"publication_date":"2014-10","languages":["eng"],"promoter":{"en":"IEEE","ja":"IEEE"},"location":{"en":"Paris","ja":"Paris"},"description":{"en":"In this paper, a course of low complexity Fast Mode Decision (FMD) algorithms as well as the corresponding hardware architecture is presented. Firstly, the depth information of co-located block from previous frame is used to predict the size of current block. Then, for a certain sized block, the inter prediction residual is analyzed to determine whether to terminate current check or to skip some unnecessary modes and split to smaller size. Finally, the corresponding hardware architecture is proposed based on state machine mechanism. Simulation results show that these proposed algorithms reduce the encoding time by 40.8~ 70.3%, without incurring any noticeable performance degradation. Hardware synthesis results demonstrate that the proposed architecture achieves a max frequency of about 193 MHz.","ja":"In this paper, a course of low complexity Fast Mode Decision (FMD) algorithms as well as the corresponding hardware architecture is presented. Firstly, the depth information of co-located block from previous frame is used to predict the size of current block. Then, for a certain sized block, the inter prediction residual is analyzed to determine whether to terminate current check or to skip some unnecessary modes and split to smaller size. Finally, the corresponding hardware architecture is proposed based on state machine mechanism. Simulation results show that these proposed algorithms reduce the encoding time by 40.8~ 70.3%, without incurring any noticeable performance degradation. Hardware synthesis results demonstrate that the proposed architecture achieves a max frequency of about 193 MHz."},"is_international_presentation":true},"priority":"input_data"}
line:86, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869175"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=279136","label":"url"}],"presentation_title":{"en":"Complexity Reduction Algorithm for Intra Prediction of HEVC","ja":"Complexity Reduction Algorithm for Intra Prediction of HEVC"},"presenters":{"en":[{"name":"Tanida Yutaroh"},{"name":"Shi Wen"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"谷田 祐太郎"},{"name":"石 文"},{"name":"宋 天"},{"name":"島本 隆"}]},"event":{"en":"The 29th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2014)","ja":"The 29th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2014)"},"publication_date":"2014-07-01","languages":["eng"],"location":{"en":"Phuket, THAILAND","ja":"Phuket, THAILAND"},"description":{"en":"The novel HEVC achieved higher coding efficiency than traditional video coding standards at the expense of increased encoding complexity. Compared with traditional intra prediction tools, high coding complexity comes from both of the increased block size and enhanced coding modes. In the proposed algorithm, a novel pixel gradient detection algorithm is proposed to reduce the candidate modes to be calculated with SATD. The proposed algorithm determines the mode with high probability in intra prediction using the difference of the adjacent pixels. As a result the proposed algorithm achieved a reduction of approximately 35% of the SATD calculation with almost no quality loss.","ja":"The novel HEVC achieved higher coding efficiency than traditional video coding standards at the expense of increased encoding complexity. Compared with traditional intra prediction tools, high coding complexity comes from both of the increased block size and enhanced coding modes. In the proposed algorithm, a novel pixel gradient detection algorithm is proposed to reduce the candidate modes to be calculated with SATD. The proposed algorithm determines the mode with high probability in intra prediction using the difference of the adjacent pixels. As a result the proposed algorithm achieved a reduction of approximately 35% of the SATD calculation with almost no quality loss."},"is_international_presentation":true},"priority":"input_data"}
line:87, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869176"},"force":{"see_also":[{"@id":"https://www.scopus.com/record/display.url?eid=2-s2.0-84907741160&origin=inward","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=278253","label":"url"}],"presentation_title":{"en":"High Efficiency Video Coding (HEVC) Motion Estimation Parallel Algorithms on GPU","ja":"High Efficiency Video Coding (HEVC) Motion Estimation Parallel Algorithms on GPU"},"presenters":{"en":[{"name":"Jiang Xiantao"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"},{"name":"Wang Lisheng"}],"ja":[{"name":"蒋 先涛"},{"name":"宋 天"},{"name":"島本 隆"},{"name":"Wang Lisheng"}]},"event":{"en":"Proceedings of IEEE International Conference on Consumer Electronics - Taiwan (2014 ICCE-Taiwan)","ja":"Proceedings of IEEE International Conference on Consumer Electronics - Taiwan (2014 ICCE-Taiwan)"},"publication_date":"2014-05-27","languages":["eng"],"promoter":{"en":"IEEE","ja":"IEEE"},"location":{"en":"Taipei","ja":"Taipei"},"description":{"en":"Exhausted motion estimation in HEVC with variable block sizes is the bottleneck for real time encoding. Previous works show that CTU-based parallel processing will induce much coding efficiency loss. In this paper, focusing on the parallel processing in one CTU, efficient parallel algorithms are presented to accelerate integer motion estimation (IME) and fractional motion estimation (FME) on GPU, including multistep composite method for IME and eliminating redundancies for FME. Experimental results show that the highest time reduction can reach up to about 52.38% compared with the non-parallel baseline implementation.","ja":"Exhausted motion estimation in HEVC with variable block sizes is the bottleneck for real time encoding. Previous works show that CTU-based parallel processing will induce much coding efficiency loss. In this paper, focusing on the parallel processing in one CTU, efficient parallel algorithms are presented to accelerate integer motion estimation (IME) and fractional motion estimation (FME) on GPU, including multistep composite method for IME and eliminating redundancies for FME. Experimental results show that the highest time reduction can reach up to about 52.38% compared with the non-parallel baseline implementation."},"is_international_presentation":true},"priority":"input_data"}
line:88, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869177"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=275321","label":"url"}],"presentation_title":{"en":"Edge Detector Based Fast Level Decision Algorithm for Intra Prediction of HEVC","ja":"Edge Detector Based Fast Level Decision Algorithm for Intra Prediction of HEVC"},"presenters":{"en":[{"name":"Shi Wen"},{"name":"Jiang Xiantao"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"石 文"},{"name":"蒋 先涛"},{"name":"宋 天"},{"name":"島本 隆"}]},"event":{"en":"Proceedings of International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP'14)","ja":"Proceedings of International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP'14)"},"publication_date":"2014-03-01","languages":["eng"],"promoter":{"en":"The Research Institute of Signal Processing Japan","ja":"The Research Institute of Signal Processing Japan"},"location":{"en":"Honolulu","ja":"Honolulu"},"description":{"en":"HEVC achieves significant coding efficiency than previous video coding standards. In intra prediction of HEVC, prediction unit sizes from 4x4 to 64x64 are employed, defined as level 1 ∼ level 5, to achieve higher coding efficiency. Nevertheless, it is at the expense of high computation complexity. This paper proposed a fast algorithm for intra prediction of HEVC that can efficiently select the level on the base of roberts-cross edge detector. It is composed mainly of a bottom-up level decision method and an efficient decision flow on the grounds of authentic image feature. The results of the proposed algorithm will achieve enormously computation complexity reduction comparing to the original HEVC.","ja":"HEVC achieves significant coding efficiency than previous video coding standards. In intra prediction of HEVC, prediction unit sizes from 4x4 to 64x64 are employed, defined as level 1 ∼ level 5, to achieve higher coding efficiency. Nevertheless, it is at the expense of high computation complexity. This paper proposed a fast algorithm for intra prediction of HEVC that can efficiently select the level on the base of roberts-cross edge detector. It is composed mainly of a bottom-up level decision method and an efficient decision flow on the grounds of authentic image feature. The results of the proposed algorithm will achieve enormously computation complexity reduction comparing to the original HEVC."},"is_international_presentation":true},"priority":"input_data"}
line:89, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869178"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=288413","label":"url"}],"presentation_title":{"en":"Hardware-oriented Fast Mode Decision Algorithm for Intra Prediction in HEVC","ja":"Hardware-oriented Fast Mode Decision Algorithm for Intra Prediction in HEVC"},"presenters":{"en":[{"name":"Zhao Wenjun"},{"name":"Onoe Takao"},{"name":"Song Tian"}],"ja":[{"name":"Zhao Wenjun"},{"name":"Onoe Takao"},{"name":"宋 天"}]},"event":{"en":"Proceedings of Picture Coding Symposium (PCS2013)","ja":"Proceedings of Picture Coding Symposium (PCS2013)"},"publication_date":"2013-12","languages":["eng"],"promoter":{"en":"IEEE","ja":"IEEE"},"location":{"en":"San Jose","ja":"San Jose"},"description":{"en":"In this paper, a hardware-oriented low complexity fast intra prediction algorithm is presented. The proposed algorithm adopts a fast Discrete Cross Differences (DCD) to detect the dominant direction of the coding unit. Based on DCD information, only a subset of the 35 candidate modes are selected for the rough mode decision process. Moreover, four simple but efficient early termination strategies are proposed to terminate the RDO process properly. Complexity analysis results demonstrate that the proposed algorithm can be easily implemented on hardware platform with fewer resources consumed. Simulation results show that the proposed algorithm reduce the encoding time by 66% on average, requiring bit-rate increase about 3.9% and PSNR decrease about 0.18dB, respectively.","ja":"In this paper, a hardware-oriented low complexity fast intra prediction algorithm is presented. The proposed algorithm adopts a fast Discrete Cross Differences (DCD) to detect the dominant direction of the coding unit. Based on DCD information, only a subset of the 35 candidate modes are selected for the rough mode decision process. Moreover, four simple but efficient early termination strategies are proposed to terminate the RDO process properly. Complexity analysis results demonstrate that the proposed algorithm can be easily implemented on hardware platform with fewer resources consumed. Simulation results show that the proposed algorithm reduce the encoding time by 66% on average, requiring bit-rate increase about 3.9% and PSNR decrease about 0.18dB, respectively."},"is_international_presentation":true},"priority":"input_data"}
line:90, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869179"},"force":{"see_also":[{"@id":"https://www.scopus.com/record/display.url?eid=2-s2.0-84892503635&origin=inward","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=269183","label":"url"}],"presentation_title":{"en":"Low Complexity Algorithm for Sub-Pixel Motion Estimation of HEVC","ja":"Low Complexity Algorithm for Sub-Pixel Motion Estimation of HEVC"},"presenters":{"en":[{"name":"Sotetsumoto Tsuyoshi"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"蘇鉄本 強"},{"name":"宋 天"},{"name":"島本 隆"}]},"event":{"en":"Proceedings of IEEE International Conference on Signal Processing, Communications and Computing (ICSPCC 2013)","ja":"Proceedings of IEEE International Conference on Signal Processing, Communications and Computing (ICSPCC 2013)"},"publication_date":"2013-08-05","languages":["eng"],"promoter":{"en":"IEEE","ja":"IEEE"},"location":{"en":"Kunming","ja":"Kunming"},"description":{"en":"The next generation video coding standard HEVC introduced many efficient algorithms to enhance the coding efficiency. However, the computational complexity of motion estimation is still the bottleneck for its implementation. In this paper, we propose a complexity reduction algorithm for fractional-pixel motion estimation (FPME). Firstly, a fast termination algorithm is proposed to fast terminate FPME using a threshold. Next, the proposed algorithm designs several original search orders and search patterns for 1/2 pixel and 1/4 pixel motion estimation, respectively. These proposed patterns are on the basis of the probability of each search point and its surrounding integer search points. Simulation results show that the proposed algorithm succeed in reduction of search point for up to 38% with almost no coding efficiency loss.","ja":"The next generation video coding standard HEVC introduced many efficient algorithms to enhance the coding efficiency. However, the computational complexity of motion estimation is still the bottleneck for its implementation. In this paper, we propose a complexity reduction algorithm for fractional-pixel motion estimation (FPME). Firstly, a fast termination algorithm is proposed to fast terminate FPME using a threshold. Next, the proposed algorithm designs several original search orders and search patterns for 1/2 pixel and 1/4 pixel motion estimation, respectively. These proposed patterns are on the basis of the probability of each search point and its surrounding integer search points. Simulation results show that the proposed algorithm succeed in reduction of search point for up to 38% with almost no coding efficiency loss."},"is_international_presentation":true},"priority":"input_data"}
line:91, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869180"},"force":{"see_also":[{"@id":"https://www.scopus.com/record/display.url?eid=2-s2.0-84883335247&origin=inward","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=269691","label":"url"}],"presentation_title":{"en":"High-Performance Multiplierless Transform Architecture for HEVC","ja":"High-Performance Multiplierless Transform Architecture for HEVC"},"presenters":{"en":[{"name":"Zhao Wenjun"},{"name":"Onoe Takao"},{"name":"Song Tian"}],"ja":[{"name":"Zhao Wenjun"},{"name":"Onoe Takao"},{"name":"宋 天"}]},"event":{"en":"Proceeding of IEEE International Symposium on Circuits and Systems(ISCAS')","ja":"Proceeding of IEEE International Symposium on Circuits and Systems(ISCAS')"},"publication_date":"2013-05","languages":["eng"],"promoter":{"en":"IEEE","ja":"IEEE"},"location":{"en":"Beijing","ja":"Beijing"},"description":{"en":"In this paper, a high-performance multiplierless VLSI architecture for the transform applied in the emerging HEVC is presented. The proposed architecture can support a variety of transform sizes from 4x4 to 32x32, and some simplification strategies are adopted during the implementation, such as reusing part of a larger sized transform structure reused by smaller ones, and turning multiplications by constant into shift and sum operations. Synthesis results on the FPGA platform indicate that the proposed design can double the throughput compared with previous work, with almost the same hardware cost. Moreover, synthesis results under 45nm technology show that it can support real-time processing of 4Kx2K (4096x2048, 30fps) video sequences.","ja":"In this paper, a high-performance multiplierless VLSI architecture for the transform applied in the emerging HEVC is presented. The proposed architecture can support a variety of transform sizes from 4x4 to 32x32, and some simplification strategies are adopted during the implementation, such as reusing part of a larger sized transform structure reused by smaller ones, and turning multiplications by constant into shift and sum operations. Synthesis results on the FPGA platform indicate that the proposed design can double the throughput compared with previous work, with almost the same hardware cost. Moreover, synthesis results under 45nm technology show that it can support real-time processing of 4Kx2K (4096x2048, 30fps) video sequences."},"is_international_presentation":true},"priority":"input_data"}
line:92, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869181"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=260125","label":"url"}],"presentation_title":{"en":"Fast Motion Estimation for Spatial Scalability of H.264/SVC","ja":"Fast Motion Estimation for Spatial Scalability of H.264/SVC"},"presenters":{"en":[{"name":"Nagao Yuto"},{"name":"Ogawa Naozumi"},{"name":"Ishikura Naoyuki"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"Nagao Yuto"},{"name":"小川 直純"},{"name":"石倉 直幸"},{"name":"宋 天"},{"name":"島本 隆"}]},"event":{"en":"Proceedings of International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP'13)","ja":"Proceedings of International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP'13)"},"publication_date":"2013-03-04","languages":["eng"],"promoter":{"en":"The Research Institute of Signal Processing Japan","ja":"The Research Institute of Signal Processing Japan"},"location":{"en":"Kona","ja":"Kona"},"description":{"en":"In this paper, we propose a fast algorithm for spatial scalability of H.264/SVC. First, verification is performed to confirm the redundancy of the previous motion estimation process of H.264/SVC. Then, based on the evaluation results we propose an improved algorithm that only focuses on the complexity reduction of enhancement layer. The proposed algorithm can decrease the computation complexity of the enhancement layer using the inter layer motion prediction. The proposed algorithm is evaluated using reference software JSVM. The simulation results show that the proposed algorithm can achieve over 66% computation complexity reduction comparing to the original JSVM algorithm.","ja":"In this paper, we propose a fast algorithm for spatial scalability of H.264/SVC. First, verification is performed to confirm the redundancy of the previous motion estimation process of H.264/SVC. Then, based on the evaluation results we propose an improved algorithm that only focuses on the complexity reduction of enhancement layer. The proposed algorithm can decrease the computation complexity of the enhancement layer using the inter layer motion prediction. The proposed algorithm is evaluated using reference software JSVM. The simulation results show that the proposed algorithm can achieve over 66% computation complexity reduction comparing to the original JSVM algorithm."},"is_international_presentation":true},"priority":"input_data"}
line:93, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869182"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=249836","label":"url"}],"presentation_title":{"en":"Computational Complexity Reduction Algorithm of Sub-Pixel Motion Estimation for HEVC","ja":"Computational Complexity Reduction Algorithm of Sub-Pixel Motion Estimation for HEVC"},"presenters":{"en":[{"name":"Sotetsumoto Tsuyoshi"},{"name":"Miki Takuya"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"蘇鉄本 強"},{"name":"三木 拓也"},{"name":"宋 天"},{"name":"島本 隆"}]},"event":{"en":"The 27th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2012)","ja":"The 27th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2012)"},"publication_date":"2012-07-15","languages":["eng"],"location":{"en":"Sapporo","ja":"Sapporo"},"description":{"en":"The emerging standard of HEVC (High Efficiency Video Coding) is on the last stage for recommendation. However, the computational complexity of motion estimation is still the bottleneck for the implementation of HEVC. In this paper, we propose a complexity reduction algorithm for the fractional-pixel motion estimation. The proposed algorithm designs several original search patterns for 1/2 pixel and 1/4 pixel motion estimation. These proposed patterns are on the basis of the probability of each search point and its surrounding integer search points. Simulation results show that the proposed algorithm succeed in reduction of search point for up to 35% with almost no coding efficiency loss.","ja":"The emerging standard of HEVC (High Efficiency Video Coding) is on the last stage for recommendation. However, the computational complexity of motion estimation is still the bottleneck for the implementation of HEVC. In this paper, we propose a complexity reduction algorithm for the fractional-pixel motion estimation. The proposed algorithm designs several original search patterns for 1/2 pixel and 1/4 pixel motion estimation. These proposed patterns are on the basis of the probability of each search point and its surrounding integer search points. Simulation results show that the proposed algorithm succeed in reduction of search point for up to 35% with almost no coding efficiency loss."},"is_international_presentation":true},"priority":"input_data"}
line:94, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869183"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=245226","label":"url"}],"presentation_title":{"en":"Motion Vector Management Architecture for 4K Resolution H.264/AVC Decoder","ja":"Motion Vector Management Architecture for 4K Resolution H.264/AVC Decoder"},"presenters":{"en":[{"name":"Takei Kentaro"},{"name":"Bando Takafumi"},{"name":"Ishikura Naoyuki"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"Takei Kentaro"},{"name":"板東 孝文"},{"name":"石倉 直幸"},{"name":"宋 天"},{"name":"島本 隆"}]},"event":{"en":"Proceedings of International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP'12)","ja":"Proceedings of International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP'12)"},"publication_date":"2012-03-04","languages":["eng"],"promoter":{"en":"The Research Institute of Signal Processing Japan","ja":"The Research Institute of Signal Processing Japan"},"location":{"en":"Honolulu","ja":"Honolulu"},"description":{"en":"The computation complexity of H.264/AVC especially for 4K resolution applications is still the bottleneck for real-time processing. In this work, a motion vector management architecture that is in charge of the total motion vectors management and calculation is proposed. The proposed architecture can calculate the predicted motion vector, select the reference motion vectors for direct mode, and calculate the motion vectors for interlace decoding. The simulation result shows that the proposed architecture can be implemented by about 99k gates working at 200MHz.","ja":"The computation complexity of H.264/AVC especially for 4K resolution applications is still the bottleneck for real-time processing. In this work, a motion vector management architecture that is in charge of the total motion vectors management and calculation is proposed. The proposed architecture can calculate the predicted motion vector, select the reference motion vectors for direct mode, and calculate the motion vectors for interlace decoding. The simulation result shows that the proposed architecture can be implemented by about 99k gates working at 200MHz."},"is_international_presentation":true},"priority":"input_data"}
line:95, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869184"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=269688","label":"url"}],"presentation_title":{"en":"Quadtree-based Adaptive Filter for Inter-layer Intra Prediction in H.264/SVC","ja":"Quadtree-based Adaptive Filter for Inter-layer Intra Prediction in H.264/SVC"},"presenters":{"en":[{"name":"Zhao Wenjun"},{"name":"Onoe Takao"},{"name":"Song Tian"},{"name":"Li Yi"}],"ja":[{"name":"Zhao Wenjun"},{"name":"Onoe Takao"},{"name":"宋 天"},{"name":"Li Yi"}]},"event":{"en":"Proceeding of International Conference on Embedded Systems and Intelligent Technology","ja":"Proceeding of International Conference on Embedded Systems and Intelligent Technology"},"publication_date":"2012-01","languages":["eng"],"promoter":{"en":"IEEE","ja":"IEEE"},"location":{"en":"Nara","ja":"Nara"},"description":{"en":"In this paper, an adaptive wiener filtering method based on the quadtree structure is proposed in addition to the inter-layer intra prediction within H.264/SVC codec. The proposed method adaptively applies the filter to individual blocks of different sizes that can be represented by the quadtree structure. Moreover, based on analysis, the proposed filter is redesigned for several times to find out the optimized filter suiting for the block region where filtering operation is actually needed. Experimental results show that the average reduction of the bitrate and PSNR improvement for 8 video sequences are 7.14% and 1.218 dB without considering the bit cost of filter operation.","ja":"In this paper, an adaptive wiener filtering method based on the quadtree structure is proposed in addition to the inter-layer intra prediction within H.264/SVC codec. The proposed method adaptively applies the filter to individual blocks of different sizes that can be represented by the quadtree structure. Moreover, based on analysis, the proposed filter is redesigned for several times to find out the optimized filter suiting for the block region where filtering operation is actually needed. Experimental results show that the average reduction of the bitrate and PSNR improvement for 8 video sequences are 7.14% and 1.218 dB without considering the bit cost of filter operation."},"is_international_presentation":true},"priority":"input_data"}
line:96, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869185"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=243734","label":"url"}],"presentation_title":{"en":"Fast Inter-layer Motion Estimation for Spatial Scalability of H.264/SVC","ja":"Fast Inter-layer Motion Estimation for Spatial Scalability of H.264/SVC"},"presenters":{"en":[{"name":"Ishikura Naoyuki"},{"name":"Takei Kentaro"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"石倉 直幸"},{"name":"武井 健太郎"},{"name":"宋 天"},{"name":"島本 隆"}]},"event":{"en":"International Conference on Innovative Computing, Information and Control (ICICIC2011)","ja":"International Conference on Innovative Computing, Information and Control (ICICIC2011)"},"publication_date":"2011-12-22","languages":["eng"],"promoter":{"en":"IEEE","ja":"IEEE"},"location":{"en":"Kitakyushu","ja":"Kitakyushu"},"description":{"en":"In this paper, we propose an improved low complexity algorithm for spatial scalability of H.264/SVC on the basis of the motions in the sequences. First, verification is performed to confirm the redundancy of the previous motion estimation process of H.264/SVC. Then, based on the evaluation results we propose an improved algorithm for our previous work that only focuses on the complexity reduction of enhancement layer. The proposed algorithm can decrease the computation complexity of the enhancement layer using the inter layer motion prediction. The simulation results show that the proposed algorithm can achieve over 95% computation complexity reduction comparing to the original JSVM algorithm.","ja":"In this paper, we propose an improved low complexity algorithm for spatial scalability of H.264/SVC on the basis of the motions in the sequences. First, verification is performed to confirm the redundancy of the previous motion estimation process of H.264/SVC. Then, based on the evaluation results we propose an improved algorithm for our previous work that only focuses on the complexity reduction of enhancement layer. The proposed algorithm can decrease the computation complexity of the enhancement layer using the inter layer motion prediction. The simulation results show that the proposed algorithm can achieve over 95% computation complexity reduction comparing to the original JSVM algorithm."},"is_international_presentation":true},"priority":"input_data"}
line:97, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869186"},"force":{"see_also":[{"@id":"https://www.scopus.com/record/display.url?eid=2-s2.0-80054830487&origin=inward","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=238774","label":"url"}],"presentation_title":{"en":"Novel INTRA modes with Temporal-Spatial Prediction for H.264/AVC","ja":"Novel INTRA modes with Temporal-Spatial Prediction for H.264/AVC"},"presenters":{"en":[{"name":"Song Tian"},{"name":"Shimamoto Takashi"},{"name":"Bando Takafumi"},{"name":"Zhao Wenjun"}],"ja":[{"name":"宋 天"},{"name":"島本 隆"},{"name":"板東 孝文"},{"name":"Zhao Wenjun"}]},"event":{"en":"2011 IEEE International Conference on Consumer Electronics - Berlin (ICCE-Berlin 2011)","ja":"2011 IEEE International Conference on Consumer Electronics - Berlin (ICCE-Berlin 2011)"},"publication_date":"2011-09-06","languages":["eng"],"promoter":{"en":"IEEE","ja":"IEEE"},"location":{"en":"Berlin, Germany","ja":"Berlin, Germany"},"description":{"en":"This work proposes a novel INTRA coding algorithm that can achieve high coding efficiency using temporal-spatial prediction for H.264/AVC. The proposed prediction algorithm can compensate the weak point of individual usage of spatial or temporal prediction. Firstly, a new prediction block is selected in the temporal previous frame. Next, the selected block in the previous frame is used as the reference data to perform spatial prediction with the same reference direction as traditional INTRA modes. The simulation results show that the proposed new INTRA modes can achieve about 1dB improvement than the original H.264/AVC.","ja":"This work proposes a novel INTRA coding algorithm that can achieve high coding efficiency using temporal-spatial prediction for H.264/AVC. The proposed prediction algorithm can compensate the weak point of individual usage of spatial or temporal prediction. Firstly, a new prediction block is selected in the temporal previous frame. Next, the selected block in the previous frame is used as the reference data to perform spatial prediction with the same reference direction as traditional INTRA modes. The simulation results show that the proposed new INTRA modes can achieve about 1dB improvement than the original H.264/AVC."},"is_international_presentation":true},"priority":"input_data"}
line:98, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869187"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=230918","label":"url"}],"presentation_title":{"en":"Keyframe Selection Method Based on the Motion Features of H.264","ja":"Keyframe Selection Method Based on the Motion Features of H.264"},"presenters":{"en":[{"name":"Li Yi"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"李 毅"},{"name":"宋 天"},{"name":"島本 隆"}]},"event":{"en":"The 26th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2011)","ja":"The 26th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2011)"},"publication_date":"2011-06-19","languages":["eng"],"location":{"en":"Gyeongju, Korea","ja":"Gyeongju, Korea"},"description":{"en":"In this paper, we propose a novel key-frame selection algorithm for video retrieval. Firstly, the video sequences are segmented into shots with the pixel features between consecutive frames. Then, based on the MV and MVD features of H.264, we notice that MV can reflect the displacement of objects in the frames and MVD can reflect the regularity of motion. Thus, the intensity of the motion can be reflected through MV and MVD features, and key-frames are selected with the greatest intensity of motion in each shot. The experimental results show that our proposed algorithm can weaken the influence of camera motion and select key-frames from video sequences effectively.","ja":"In this paper, we propose a novel key-frame selection algorithm for video retrieval. Firstly, the video sequences are segmented into shots with the pixel features between consecutive frames. Then, based on the MV and MVD features of H.264, we notice that MV can reflect the displacement of objects in the frames and MVD can reflect the regularity of motion. Thus, the intensity of the motion can be reflected through MV and MVD features, and key-frames are selected with the greatest intensity of motion in each shot. The experimental results show that our proposed algorithm can weaken the influence of camera motion and select key-frames from video sequences effectively."},"is_international_presentation":true},"priority":"input_data"}
line:99, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869188"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=230917","label":"url"}],"presentation_title":{"en":"Fast Parallel Algorithm of H.264/AVC Deblocking Filter for GPU Implementation","ja":"Fast Parallel Algorithm of H.264/AVC Deblocking Filter for GPU Implementation"},"presenters":{"en":[{"name":"Matsunohana Yuya"},{"name":"Sakai Yuhiro"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"松端 裕也"},{"name":"酒井 雄大"},{"name":"宋 天"},{"name":"島本 隆"}]},"event":{"en":"The 26th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2011)","ja":"The 26th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2011)"},"publication_date":"2011-06-19","languages":["eng"],"location":{"en":"Gyeongju, Korea","ja":"Gyeongju, Korea"},"description":{"en":"Due to the improvement of the processing capability of graphics processing unit (GPU), it is considered as a powerful processing tool to realize fast implementation of H.264/AVC. In this work, we propose a fast parallel algorithm for deblocking filter (DF) in H.264/AVC on a computer unified device architecture (CUDA) platform that is proposed by NVIDIA GPUs. The proposed algorithm modifies the filtering process to realize parallel processing of all macroblocks in one frame. Simulation results show that this modification will not induce PSNR loss and it realized over 10 times fast processing of DF than that of using CPU only.","ja":"Due to the improvement of the processing capability of graphics processing unit (GPU), it is considered as a powerful processing tool to realize fast implementation of H.264/AVC. In this work, we propose a fast parallel algorithm for deblocking filter (DF) in H.264/AVC on a computer unified device architecture (CUDA) platform that is proposed by NVIDIA GPUs. The proposed algorithm modifies the filtering process to realize parallel processing of all macroblocks in one frame. Simulation results show that this modification will not induce PSNR loss and it realized over 10 times fast processing of DF than that of using CPU only."},"is_international_presentation":true},"priority":"input_data"}
line:100, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869189"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=229428","label":"url"}],"presentation_title":{"en":"New Prediction Modes for Parallel Processing of H.264/AVC","ja":"New Prediction Modes for Parallel Processing of H.264/AVC"},"presenters":{"en":[{"name":"Bando Takafumi"},{"name":"Hirai Naoyuki"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"板東 孝文"},{"name":"平井 直行"},{"name":"宋 天"},{"name":"島本 隆"}]},"event":{"en":"Proceedings of International Conference on Multimedia and Signal Processing (CMSP'11)","ja":"Proceedings of International Conference on Multimedia and Signal Processing (CMSP'11)"},"publication_date":"2011-05-14","languages":["eng"],"promoter":{"en":"IEEE","ja":"IEEE"},"location":{"en":"Guilin, China","ja":"Guilin, China"},"description":{"en":"This work proposes a novel parallel processing algorithm for H.264/AVC that is dedicated to GPU implementation. Firstly, the original pixel data is used in the rate-distortion optimization (RDO) process instead of the reconstructed pixel data to realize the complete MB-level parallel processing of INTRA coding. It can help to parallel encode all the MB in one frame in the same time on GPU. Next, a new temporal prediction concept is introduced in the traditional spatial prediction to compensate the weak point of individual usage of spatial or temporal prediction. The simulation results show that when using the original pixel in the RDO process it will induce slight PSNR loss. However, when the proposed new modes are introduced the RD-curve shows about 1dB improvement than the original H.264/AVC.","ja":"This work proposes a novel parallel processing algorithm for H.264/AVC that is dedicated to GPU implementation. Firstly, the original pixel data is used in the rate-distortion optimization (RDO) process instead of the reconstructed pixel data to realize the complete MB-level parallel processing of INTRA coding. It can help to parallel encode all the MB in one frame in the same time on GPU. Next, a new temporal prediction concept is introduced in the traditional spatial prediction to compensate the weak point of individual usage of spatial or temporal prediction. The simulation results show that when using the original pixel in the RDO process it will induce slight PSNR loss. However, when the proposed new modes are introduced the RD-curve shows about 1dB improvement than the original H.264/AVC."},"is_international_presentation":true},"priority":"input_data"}
line:101, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869190"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=223726","label":"url"}],"presentation_title":{"en":"Motion Estimation Algorithm for Spatial Scalability in H.264/SVC","ja":"Motion Estimation Algorithm for Spatial Scalability in H.264/SVC"},"presenters":{"en":[{"name":"Katayama Takafumi"},{"name":"Hamamoto Takaaki"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"片山 貴文"},{"name":"濱本 高彰"},{"name":"宋 天"},{"name":"島本 隆"}]},"event":{"en":"Proceedings of International Workshop on Nonlinear Circuits, Communication and Signal Processing (NCSP'11)","ja":"Proceedings of International Workshop on Nonlinear Circuits, Communication and Signal Processing (NCSP'11)"},"publication_date":"2011-03-03","languages":["eng"],"promoter":{"en":"The Research Institute of Signal Processing Japan","ja":"The Research Institute of Signal Processing Japan"},"location":{"en":"Tianjin, China","ja":"Tianjin, China"},"description":{"en":"In this paper, we propose an improved low complexity algorithm for spatial scalability of H.264/SVC on the basis of the motions in the sequences. First, verification is performed to confirm the redundancy of the previous motion estimation process of H.264/SVC. Then, based on the evaluation results we propose an improved algorithm for our previous work in which only focuses on the complexity reduction of enhancement layer. The proposed algorithm can decrease the computation complexity of the enhancement layer using the inter layer motion prediction. The simulation results show that the proposed algorithm can achieve over 95% complexity reduction comparing to the original JSVM. When it is compared with our previous works, 12% complexity reduction has been achieved.","ja":"In this paper, we propose an improved low complexity algorithm for spatial scalability of H.264/SVC on the basis of the motions in the sequences. First, verification is performed to confirm the redundancy of the previous motion estimation process of H.264/SVC. Then, based on the evaluation results we propose an improved algorithm for our previous work in which only focuses on the complexity reduction of enhancement layer. The proposed algorithm can decrease the computation complexity of the enhancement layer using the inter layer motion prediction. The simulation results show that the proposed algorithm can achieve over 95% complexity reduction comparing to the original JSVM. When it is compared with our previous works, 12% complexity reduction has been achieved."},"is_international_presentation":true},"priority":"input_data"}
line:102, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869191"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=223725","label":"url"}],"presentation_title":{"en":"Improved Inter-layer Intra Prediction for Scalable Video Coding","ja":"Improved Inter-layer Intra Prediction for Scalable Video Coding"},"presenters":{"en":[{"name":"Zhao Wenjun"},{"name":"Song Tian"},{"name":"Wang Jinxiang"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"Zhao Wenjun"},{"name":"宋 天"},{"name":"Wang Jinxiang"},{"name":"島本 隆"}]},"event":{"en":"Proceedings of International Workshop on Nonlinear Circuits, Communication and Signal Processing (NCSP'11)","ja":"Proceedings of International Workshop on Nonlinear Circuits, Communication and Signal Processing (NCSP'11)"},"publication_date":"2011-03-03","languages":["eng"],"promoter":{"en":"The Research Institute of Signal Processing Japan","ja":"The Research Institute of Signal Processing Japan"},"location":{"en":"Tianjin, China","ja":"Tianjin, China"},"description":{"en":"In this paper, a method based on the two dimensional Wiener filter is proposed in addition to inter-layer intra prediction in H.264/SVC. The performance of inter-layer intra prediction is limited due to the up-sampling operation and the coding noise of base layer. The Wiener filter can be used as an optimizing filter to enhance the prediction of enhancement. However, prediction errors of some pixels are increased by this filter operation. The proposed method applies the filter for each block of different size adaptively. Experimental results show that the reduction of bit rate and PSNR improvement for QCIF-CIF Akiyo sequences are 3.74% and 1.15dB without considering the bit cost of filter operation.","ja":"In this paper, a method based on the two dimensional Wiener filter is proposed in addition to inter-layer intra prediction in H.264/SVC. The performance of inter-layer intra prediction is limited due to the up-sampling operation and the coding noise of base layer. The Wiener filter can be used as an optimizing filter to enhance the prediction of enhancement. However, prediction errors of some pixels are increased by this filter operation. The proposed method applies the filter for each block of different size adaptively. Experimental results show that the reduction of bit rate and PSNR improvement for QCIF-CIF Akiyo sequences are 3.74% and 1.15dB without considering the bit cost of filter operation."},"is_international_presentation":true},"priority":"input_data"}
line:103, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869192"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=223724","label":"url"}],"presentation_title":{"en":"Novel Variable Search Range Selection Algorithm for H.264/SVC","ja":"Novel Variable Search Range Selection Algorithm for H.264/SVC"},"presenters":{"en":[{"name":"Hamamoto Takaaki"},{"name":"Katayama Takafumi"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"濱本 高彰"},{"name":"片山 貴文"},{"name":"宋 天"},{"name":"島本 隆"}]},"event":{"en":"Proceedings of International Workshop on Nonlinear Circuits, Communication and Signal Processing (NCSP'11)","ja":"Proceedings of International Workshop on Nonlinear Circuits, Communication and Signal Processing (NCSP'11)"},"publication_date":"2011-03-03","languages":["eng"],"promoter":{"en":"The Research Institute of Signal Processing Japan","ja":"The Research Institute of Signal Processing Japan"},"location":{"en":"Tianjin, China","ja":"Tianjin, China"},"description":{"en":"In this paper, a novel variable search range selection algorithm is proposed for the H.264/SVC. The scalable extension of H.264/AVC achieves high scalability as well as high coding efficiency. However, the exhausted computation complexity becomes the implementation difficulty. In variable block size motion estimation, we find that motion estimation process has much redundancy. On the basis of this feature, we propose a novel variable search range algorithm that can significantly reduce the redundant search range. Simulation results show that the proposed method can achieve high computation complexity reduction with very slight PSNR loss.","ja":"In this paper, a novel variable search range selection algorithm is proposed for the H.264/SVC. The scalable extension of H.264/AVC achieves high scalability as well as high coding efficiency. However, the exhausted computation complexity becomes the implementation difficulty. In variable block size motion estimation, we find that motion estimation process has much redundancy. On the basis of this feature, we propose a novel variable search range algorithm that can significantly reduce the redundant search range. Simulation results show that the proposed method can achieve high computation complexity reduction with very slight PSNR loss."},"is_international_presentation":true},"priority":"input_data"}
line:104, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869193"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=223722","label":"url"}],"presentation_title":{"en":"Fast Parallel Algorithm of Motion Estimation for GPU Implementation","ja":"Fast Parallel Algorithm of Motion Estimation for GPU Implementation"},"presenters":{"en":[{"name":"Koshino Masashi"},{"name":"Matsunohana Yuya"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"古志野 真史"},{"name":"松端 裕也"},{"name":"宋 天"},{"name":"島本 隆"}]},"event":{"en":"Proceedings of International Workshop on Nonlinear Circuits, Communication and Signal Processing (NCSP'11)","ja":"Proceedings of International Workshop on Nonlinear Circuits, Communication and Signal Processing (NCSP'11)"},"publication_date":"2011-03-03","languages":["eng"],"promoter":{"en":"The Research Institute of Signal Processing Japan","ja":"The Research Institute of Signal Processing Japan"},"location":{"en":"Tianjin, China","ja":"Tianjin, China"},"description":{"en":"Due to the rapid growth of the processing capability of graphics processing unit (GPU), using GPU as a coprocessor to assist the CPU in computing massive data becomes essential. In this work, we propose a fast parallel algorithm for motion estimation (ME) process in H.264/AVC on a computer unified device architecture (CUDA) platform. The proposed algorithm performs the parallel calculation of the residuals and SAD. Simulation results show that with the assistance of GPU the processing time is about 2 times faster than that of using CPU only.","ja":"Due to the rapid growth of the processing capability of graphics processing unit (GPU), using GPU as a coprocessor to assist the CPU in computing massive data becomes essential. In this work, we propose a fast parallel algorithm for motion estimation (ME) process in H.264/AVC on a computer unified device architecture (CUDA) platform. The proposed algorithm performs the parallel calculation of the residuals and SAD. Simulation results show that with the assistance of GPU the processing time is about 2 times faster than that of using CPU only."},"is_international_presentation":true},"priority":"input_data"}
line:105, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869194"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=223720","label":"url"}],"presentation_title":{"en":"Fast Spiral Motion Estimation Algorithm for H.264/AVC","ja":"Fast Spiral Motion Estimation Algorithm for H.264/AVC"},"presenters":{"en":[{"name":"Hirai Naoyuki"},{"name":"Sakai Yuhiro"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"平井 直行"},{"name":"酒井 雄大"},{"name":"宋 天"},{"name":"島本 隆"}]},"event":{"en":"Proceedings of International Workshop on Nonlinear Circuits, Communication and Signal Processing (NCSP'11)","ja":"Proceedings of International Workshop on Nonlinear Circuits, Communication and Signal Processing (NCSP'11)"},"publication_date":"2011-03-03","languages":["eng"],"promoter":{"en":"The Research Institute of Signal Processing Japan","ja":"The Research Institute of Signal Processing Japan"},"location":{"en":"Tianjin, China","ja":"Tianjin, China"},"description":{"en":"Variable block size and multiple reference frames are introduced in H.264/AVC. However, these new features induce significant implementation complexity increases. In this paper, fast spiral motion estimation (FSME) is proposed based on our previous spiral motion estimation (SME) algorithm and its architecture. When the sum of absolute differences (SAD) closes to the best search position, a convergent value of SAD is available. The proposed FSME reduces the search point candidates with the characteristic of SAD. Simulation results show that about 63% search points in motion estimation is realized by negligible video quality degradation.","ja":"Variable block size and multiple reference frames are introduced in H.264/AVC. However, these new features induce significant implementation complexity increases. In this paper, fast spiral motion estimation (FSME) is proposed based on our previous spiral motion estimation (SME) algorithm and its architecture. When the sum of absolute differences (SAD) closes to the best search position, a convergent value of SAD is available. The proposed FSME reduces the search point candidates with the characteristic of SAD. Simulation results show that about 63% search points in motion estimation is realized by negligible video quality degradation."},"is_international_presentation":true},"priority":"input_data"}
line:106, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869195"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=219763","label":"url"}],"presentation_title":{"en":"Coding Efficient Improvement by Adaptive Search Center Definition","ja":"Coding Efficient Improvement by Adaptive Search Center Definition"},"presenters":{"en":[{"name":"Oba Kyohei"},{"name":"Bando Takafumi"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"大場 恭平"},{"name":"板東 孝文"},{"name":"宋 天"},{"name":"島本 隆"}]},"event":{"en":"Proceedings of 28th Picture Coding Symposium (PCS2010)","ja":"Proceedings of 28th Picture Coding Symposium (PCS2010)"},"publication_date":"2010-12-08","languages":["eng"],"location":{"en":"Nagoya","ja":"Nagoya"},"description":{"en":"In this paper, an efficient search center definition algorithm is proposed for H.264/AVC. H.264/AVC achieved high coding efficiency but the definition of the search center is not efficient in the case of significant motions. This work proposes some new search center candidates using spatial and temporal correlations of motion vectors to improve the coding efficiency. Simulation results show that the proposed search centers can achieve very much bit saving but induced high computation complexity. Additional complexity reduction algorithm is also introduced to improve the tradeoff between bit saving and implementation performance. This work realized a maximum bit saving of 19%.","ja":"In this paper, an efficient search center definition algorithm is proposed for H.264/AVC. H.264/AVC achieved high coding efficiency but the definition of the search center is not efficient in the case of significant motions. This work proposes some new search center candidates using spatial and temporal correlations of motion vectors to improve the coding efficiency. Simulation results show that the proposed search centers can achieve very much bit saving but induced high computation complexity. Additional complexity reduction algorithm is also introduced to improve the tradeoff between bit saving and implementation performance. This work realized a maximum bit saving of 19%."},"is_international_presentation":true},"priority":"input_data"}
line:107, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869196"},"force":{"see_also":[{"@id":"https://www.scopus.com/record/display.url?eid=2-s2.0-78651102812&origin=inward","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=214615","label":"url"}],"presentation_title":{"en":"Motion Based Low Complexity Algorithm for Spatial Scalability of H.264/SVC","ja":"Motion Based Low Complexity Algorithm for Spatial Scalability of H.264/SVC"},"presenters":{"en":[{"name":"Katayama Takafumi"},{"name":"Hamamoto Takaaki"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"片山 貴文"},{"name":"濱本 高彰"},{"name":"宋 天"},{"name":"島本 隆"}]},"event":{"en":"Proceedings of 2010 IEEE 17th International Conference on Image Processing (ICIP2010)","ja":"Proceedings of 2010 IEEE 17th International Conference on Image Processing (ICIP2010)"},"publication_date":"2010-09-26","languages":["eng"],"location":{"en":"Hong Kong","ja":"Hong Kong"},"description":{"en":"In this paper, we propose an improved low complexity algorithm for spatial scalability of H.264/SVC on the basis of the motions in the sequences. First, verification is performed to confirm the redundancy of the previous motion estimation process of H.264/SVC. Then, based on the evaluation results we propose an improved algorithm for our previous work that only focuses on the complexity reduction of enhancement layer. The simulation results show that the proposed algorithm can achieve over 90% computation complexity reduction comparing to the original JSVM algorithm. When it is compared with previous works, 10% complexity reduction and over 27% time saving have been achieved.","ja":"In this paper, we propose an improved low complexity algorithm for spatial scalability of H.264/SVC on the basis of the motions in the sequences. First, verification is performed to confirm the redundancy of the previous motion estimation process of H.264/SVC. Then, based on the evaluation results we propose an improved algorithm for our previous work that only focuses on the complexity reduction of enhancement layer. The simulation results show that the proposed algorithm can achieve over 90% computation complexity reduction comparing to the original JSVM algorithm. When it is compared with previous works, 10% complexity reduction and over 27% time saving have been achieved."},"is_international_presentation":true},"priority":"input_data"}
line:108, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869197"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=214614","label":"url"}],"presentation_title":{"en":"Real-Time Architecture for Inter-layer Prediction of H.264/SVC","ja":"Real-Time Architecture for Inter-layer Prediction of H.264/SVC"},"presenters":{"en":[{"name":"Takei Kentaro"},{"name":"Hirai Naoyuki"},{"name":"Katayama Takafumi"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"武井 健太郎"},{"name":"平井 直行"},{"name":"片山 貴文"},{"name":"宋 天"},{"name":"島本 隆"}]},"event":{"en":"Proceedings of Pacific-Rim Conference on Multimedia (PCM2010)","ja":"Proceedings of Pacific-Rim Conference on Multimedia (PCM2010)"},"publication_date":"2010-09-21","languages":["eng"],"location":{"en":"Shanghai","ja":"Shanghai"},"description":{"en":"In this paper, an efficient architecture for Inter-layer prediction of H.264/SVC is proposed. In the proposed architecture, the motion vector prediction mode is not concerned due to its limited coding efficiency. Using an efficient mode selection algorithm that is proposed by our previous work, the complexity of residual prediction is significantly reduced. Therefore, to realize real-time processing with low cost hardware, the proposed architecture makes use of a single-core coding engine. Using this coding core, the macroblock encoding is performed for base layer and enhancement layer alternatively. The proposed up-sampling module is described by Verilog-HDL and synthesis results show that the gate counts are 16,121 and the maximum working frequency is 141MHz.","ja":"In this paper, an efficient architecture for Inter-layer prediction of H.264/SVC is proposed. In the proposed architecture, the motion vector prediction mode is not concerned due to its limited coding efficiency. Using an efficient mode selection algorithm that is proposed by our previous work, the complexity of residual prediction is significantly reduced. Therefore, to realize real-time processing with low cost hardware, the proposed architecture makes use of a single-core coding engine. Using this coding core, the macroblock encoding is performed for base layer and enhancement layer alternatively. The proposed up-sampling module is described by Verilog-HDL and synthesis results show that the gate counts are 16,121 and the maximum working frequency is 141MHz."},"is_international_presentation":true},"priority":"input_data"}
line:109, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869198"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=214613","label":"url"}],"presentation_title":{"en":"Low Complexity Inter-Layer Motion Estimation Algorithm for H.264/SVC","ja":"Low Complexity Inter-Layer Motion Estimation Algorithm for H.264/SVC"},"presenters":{"en":[{"name":"Katayama Takafumi"},{"name":"Hamamoto Takaaki"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"片山 貴文"},{"name":"濱本 高彰"},{"name":"宋 天"},{"name":"島本 隆"}]},"event":{"en":"Proceedings of World Automation Congress (WAC2010)","ja":"Proceedings of World Automation Congress (WAC2010)"},"publication_date":"2010-09-19","languages":["eng"],"location":{"en":"Kobe","ja":"Kobe"},"description":{"en":"In this paper, we propose an improved low complexity algorithm on the basis of motions in the sequences for H.264/SVC. First, verification is performed to confirm the redundancy of the previous motion estimation process of H.264/SVC. Then, based on the evaluation results we propose an improved algorithm for our previous work that focuses on the complexity reduction of enhancement layer only. Furthermore, the proposed algorithm can decrease the computation complexity of the base layer using the feature of the hierarchical structure. The simulation results show that the proposed algorithm can achieve over 90% computation complexity reduction comparing to the original JSVM algorithm.","ja":"In this paper, we propose an improved low complexity algorithm on the basis of motions in the sequences for H.264/SVC. First, verification is performed to confirm the redundancy of the previous motion estimation process of H.264/SVC. Then, based on the evaluation results we propose an improved algorithm for our previous work that focuses on the complexity reduction of enhancement layer only. Furthermore, the proposed algorithm can decrease the computation complexity of the base layer using the feature of the hierarchical structure. The simulation results show that the proposed algorithm can achieve over 90% computation complexity reduction comparing to the original JSVM algorithm."},"is_international_presentation":true},"priority":"input_data"}
line:110, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869199"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=214184","label":"url"}],"presentation_title":{"en":"Complexity Reduction Algorithm for Enhancement Layer of H.264/SVC","ja":"Complexity Reduction Algorithm for Enhancement Layer of H.264/SVC"},"presenters":{"en":[{"name":"Takei Kentaro"},{"name":"Katayama Takafumi"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"武井 健太郎"},{"name":"片山 貴文"},{"name":"宋 天"},{"name":"島本 隆"}]},"event":{"en":"The Third International Symposium on Intelligent Informatics (ISII2010)","ja":"The Third International Symposium on Intelligent Informatics (ISII2010)"},"publication_date":"2010-09-05","languages":["eng"],"location":{"en":"Dalian","ja":"Dalian"},"description":{"en":"The inter-layer prediction of H.264/SVC can help to improve the coding efficiency as well as the computation complexity. This paper presents a low complexity algorithm for inter-layer prediction. Proposed algorithm focuses on the reduction of the candidate modes by making use of the correlations of the encoding cost between the base layer and enhancement layers. For macroblock with collocated macroblock coded by INTRA or INTER type, two algorithm are proposed, respectively. Both algorithm efficiently decrease the redundant candidate modes by estimating from the base layer coding information. The experiment results show that proposed algorithm can significantly reduce redundant computation complexity with almost no coding efficiency loss.","ja":"The inter-layer prediction of H.264/SVC can help to improve the coding efficiency as well as the computation complexity. This paper presents a low complexity algorithm for inter-layer prediction. Proposed algorithm focuses on the reduction of the candidate modes by making use of the correlations of the encoding cost between the base layer and enhancement layers. For macroblock with collocated macroblock coded by INTRA or INTER type, two algorithm are proposed, respectively. Both algorithm efficiently decrease the redundant candidate modes by estimating from the base layer coding information. The experiment results show that proposed algorithm can significantly reduce redundant computation complexity with almost no coding efficiency loss."},"is_international_presentation":true},"priority":"input_data"}
line:111, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869200"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=214183","label":"url"}],"presentation_title":{"en":"Efficient Deblocking Filter Architecture for High-Resolution Applications of H.264/AVC","ja":"Efficient Deblocking Filter Architecture for High-Resolution Applications of H.264/AVC"},"presenters":{"en":[{"name":"Akita Tomohiro"},{"name":"Hirai Naoyuki"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"秋田 朋洋"},{"name":"平井 直行"},{"name":"宋 天"},{"name":"島本 隆"}]},"event":{"en":"The Third International Symposium on Intelligent Informatics (ISII2010)","ja":"The Third International Symposium on Intelligent Informatics (ISII2010)"},"publication_date":"2010-09-05","languages":["eng"],"location":{"en":"Dalian","ja":"Dalian"},"description":{"en":"This paper presents an efficient deblocking-filter architecture for high-resolution applications of H.264/AVC. In this work, we try to reduce the redundant filtering process in the case of high-resolution applications with low quantization parameter (QP). We early terminate filtering process to cut down power consumption by detecting the case when all the boundary strength (BS) of 4×4 blocks for one macroblock are zero. An efficient architecture that can realize these two proposals is also proposed. Simulation results show that there is a maximum 90% reduction in the filtering calculations and 87% of BS calculation. Low power implementation can be realized with the proposed architecture.","ja":"This paper presents an efficient deblocking-filter architecture for high-resolution applications of H.264/AVC. In this work, we try to reduce the redundant filtering process in the case of high-resolution applications with low quantization parameter (QP). We early terminate filtering process to cut down power consumption by detecting the case when all the boundary strength (BS) of 4×4 blocks for one macroblock are zero. An efficient architecture that can realize these two proposals is also proposed. Simulation results show that there is a maximum 90% reduction in the filtering calculations and 87% of BS calculation. Low power implementation can be realized with the proposed architecture."},"is_international_presentation":true},"priority":"input_data"}
line:112, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869201"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=205283","label":"url"}],"presentation_title":{"en":"Four-bins Paralleled Architecture for CABAC in H.264/AVC","ja":"Four-bins Paralleled Architecture for CABAC in H.264/AVC"},"presenters":{"en":[{"name":"Liu Yizhong"},{"name":"Li Yi"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"Liu Yizhong"},{"name":"Li Yi"},{"name":"宋 天"},{"name":"島本 隆"}]},"event":{"en":"Proceedings of International Workshop on Nonlinear Circuits and Signal Processing (NCSP'10)","ja":"Proceedings of International Workshop on Nonlinear Circuits and Signal Processing (NCSP'10)"},"publication_date":"2010-03-03","languages":["eng"],"promoter":{"en":"The Research Institute of Signal Processing Japan","ja":"The Research Institute of Signal Processing Japan"},"location":{"en":"Honolulu","ja":"Honolulu"},"description":{"en":"In H.264/AVC, the entropy encode tool used in main and high profiles is context-based adaptive binary arithmetic coding (CABAC) which can achieve high coding efficiency. In this work, a high encoding throughput is achieved, but it only benefits from running at the much higher frequency that is not typical implementation for current applications. Another work proposed some acceleration architectures to encode 3 or 4 in one cycle. However in this architecture, only the bypass encoded which account for about 15% of the total are accelerated. This paper proposes an efficient pipelined architecture with the encoding ability of 4 per cycle supporting both the bypass mode and the context-adaptive mode in CABAC.","ja":"In H.264/AVC, the entropy encode tool used in main and high profiles is context-based adaptive binary arithmetic coding (CABAC) which can achieve high coding efficiency. In this work, a high encoding throughput is achieved, but it only benefits from running at the much higher frequency that is not typical implementation for current applications. Another work proposed some acceleration architectures to encode 3 or 4 in one cycle. However in this architecture, only the bypass encoded which account for about 15% of the total are accelerated. This paper proposes an efficient pipelined architecture with the encoding ability of 4 per cycle supporting both the bypass mode and the context-adaptive mode in CABAC."},"is_international_presentation":true},"priority":"input_data"}
line:113, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869202"},"force":{"see_also":[{"@id":"https://www.scopus.com/record/display.url?eid=2-s2.0-77951940920&origin=inward","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=196195","label":"url"}],"presentation_title":{"en":"Low Complexity Algorithm for Inter-layer Residual Prediction of H.264/SVC","ja":"Low Complexity Algorithm for Inter-layer Residual Prediction of H.264/SVC"},"presenters":{"en":[{"name":"Morigami Yoshitaka"},{"name":"Song Tian"},{"name":"Katayama Takafumi"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"Morigami Yoshitaka"},{"name":"宋 天"},{"name":"片山 貴文"},{"name":"島本 隆"}]},"event":{"en":"IEEE International Conference on Image Processing (ICIP2009)","ja":"IEEE International Conference on Image Processing (ICIP2009)"},"publication_date":"2009-11-07","languages":["eng"],"promoter":{"en":"IEEE","ja":"IEEE"},"location":{"en":"Cairo, Egypt","ja":"Cairo, Egypt"},"description":{"en":"In this paper, we propose an improved low complexity algorithm for spatial scalability of H.264/SVC on the basis of the motions in the sequences. First, verification is performed to confirm the redundancy of the previous motion estimation process of H.264/SVC. Then, based on the evaluation results we propose an improved algorithm for our previous work that only focuses on the complexity reduction of enhancement layer. The simulation results show that the proposed algorithm can achieve over 90% computation complexity reduction comparing to the original JSVM algorithm. When it is compared with some other previous works, 10% complexity reduction and over 27% time saving have been achieved.","ja":"In this paper, we propose an improved low complexity algorithm for spatial scalability of H.264/SVC on the basis of the motions in the sequences. First, verification is performed to confirm the redundancy of the previous motion estimation process of H.264/SVC. Then, based on the evaluation results we propose an improved algorithm for our previous work that only focuses on the complexity reduction of enhancement layer. The simulation results show that the proposed algorithm can achieve over 90% computation complexity reduction comparing to the original JSVM algorithm. When it is compared with some other previous works, 10% complexity reduction and over 27% time saving have been achieved."},"is_international_presentation":true},"priority":"input_data"}
line:114, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869203"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=194702","label":"url"}],"presentation_title":{"en":"Mode Selection Method for Hierarchical B-picture of H.264/SVC","ja":"Mode Selection Method for Hierarchical B-picture of H.264/SVC"},"presenters":{"en":[{"name":"Hamamoto Takaaki"},{"name":"Katayama Takafumi"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"Hamamoto Takaaki"},{"name":"片山 貴文"},{"name":"宋 天"},{"name":"島本 隆"}]},"event":{"en":"The Second International Symposium on Intelligent Informatics (ISII2009)","ja":"The Second International Symposium on Intelligent Informatics (ISII2009)"},"publication_date":"2009-09-13","languages":["eng"],"location":{"en":"QinHuangDao, China","ja":"QinHuangDao, China"},"description":{"en":"In this paper, a novel mode selection method for hierarchical B-picture of H.264/SVC is proposed. However, the exhausted computation complexity becomes the implementation difficulty. Observing the correlation in multi-layer structures, we find that the mode selection process has much redundancy. In particular, the redundant modes have essential relation with the encoding layers. On the basis of this feature, we propose a novel mode selection method that can significantly reduce the redundant candidate modes. Simulation results show that the proposed method can achieve high computation complexity with very slight PSNR loss.","ja":"In this paper, a novel mode selection method for hierarchical B-picture of H.264/SVC is proposed. However, the exhausted computation complexity becomes the implementation difficulty. Observing the correlation in multi-layer structures, we find that the mode selection process has much redundancy. In particular, the redundant modes have essential relation with the encoding layers. On the basis of this feature, we propose a novel mode selection method that can significantly reduce the redundant candidate modes. Simulation results show that the proposed method can achieve high computation complexity with very slight PSNR loss."},"is_international_presentation":true},"priority":"input_data"}
line:115, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869204"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=193426","label":"url"}],"presentation_title":{"en":"Improvement of Motion Estimation with Modified Search Center and Search Range for H.264/SVC","ja":"Improvement of Motion Estimation with Modified Search Center and Search Range for H.264/SVC"},"presenters":{"en":[{"name":"Katayama Takafumi"},{"name":"Morigami Yoshitaka"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"片山 貴文"},{"name":"Morigami Yoshitaka"},{"name":"宋 天"},{"name":"島本 隆"}]},"event":{"en":"The 24th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2009)","ja":"The 24th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2009)"},"publication_date":"2009-07-05","languages":["eng"],"location":{"en":"Cheju","ja":"Cheju"},"description":{"en":"In this paper, we propose a novel optimized motion estimation algorithm with a modified search center for spatial scalability when using inter-layer motion prediction of H.264/SVC. Firstly, up-sampled motion vector of base layer is evaluated to find the relation with the enhancement layer. Based on the results, we use the motion vector of the base layer to estimate the optimal search center for enhancement layer. Then, based on the modified search center we adaptively control the search range to reduce the redundant motion estimation. The simulation results show that the proposed algorithm can achieve over 80% computation complexity reduction of total motion estimation.","ja":"In this paper, we propose a novel optimized motion estimation algorithm with a modified search center for spatial scalability when using inter-layer motion prediction of H.264/SVC. Firstly, up-sampled motion vector of base layer is evaluated to find the relation with the enhancement layer. Based on the results, we use the motion vector of the base layer to estimate the optimal search center for enhancement layer. Then, based on the modified search center we adaptively control the search range to reduce the redundant motion estimation. The simulation results show that the proposed algorithm can achieve over 80% computation complexity reduction of total motion estimation."},"is_international_presentation":true},"priority":"input_data"}
line:116, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869205"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=193425","label":"url"}],"presentation_title":{"en":"An Efficient Architecture for Spiral-Type Motion Estimation for H.264/AVC","ja":"An Efficient Architecture for Spiral-Type Motion Estimation for H.264/AVC"},"presenters":{"en":[{"name":"Hirai Naoyuki"},{"name":"Kato Takahiro"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"Hirai Naoyuki"},{"name":"Kato Takahiro"},{"name":"宋 天"},{"name":"島本 隆"}]},"event":{"en":"The 24th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2009)","ja":"The 24th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2009)"},"publication_date":"2009-07-05","languages":["eng"],"location":{"en":"Cheju","ja":"Cheju"},"description":{"en":"In this paper, an efficient architecture for spiral-type ME is proposed. First, we propose a hardware friendly spiral search order. Then, an improved PE architecture for ME is proposed to achieve the proposed search order. The improved PE enables the shift of the reference pixel data to top, bottom, right, and left by 4 input and output ports. Moreover, the parallel calculation architecture to calculate all block size with the SAD of 4x4 is introduced in the proposed architecture. As a result of hardware implementation, the hardware cost is about 145K gates. Maximum clock frequency is 134MHz in the case of FPGA (Xilinx Vertex5) implementation.","ja":"In this paper, an efficient architecture for spiral-type ME is proposed. First, we propose a hardware friendly spiral search order. Then, an improved PE architecture for ME is proposed to achieve the proposed search order. The improved PE enables the shift of the reference pixel data to top, bottom, right, and left by 4 input and output ports. Moreover, the parallel calculation architecture to calculate all block size with the SAD of 4x4 is introduced in the proposed architecture. As a result of hardware implementation, the hardware cost is about 145K gates. Maximum clock frequency is 134MHz in the case of FPGA (Xilinx Vertex5) implementation."},"is_international_presentation":true},"priority":"input_data"}
line:117, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869206"},"force":{"see_also":[{"@id":"https://www.scopus.com/record/display.url?eid=2-s2.0-70350217914&origin=inward","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=192943","label":"url"}],"presentation_title":{"en":"Spatial-Temporal Correlation Based Mode Decision Algorithm for H.264/AVC","ja":"Spatial-Temporal Correlation Based Mode Decision Algorithm for H.264/AVC"},"presenters":{"en":[{"name":"Kozu Hiroki"},{"name":"Kuniyasu Hiroki"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"髙津 大樹"},{"name":"國安 大樹"},{"name":"宋 天"},{"name":"島本 隆"}]},"event":{"en":"The 13th IEEE International Symposium on Consumer Electronics (ISCE2009)","ja":"The 13th IEEE International Symposium on Consumer Electronics (ISCE2009)"},"publication_date":"2009-05-25","languages":["eng"],"promoter":{"en":"IEEE","ja":"IEEE"},"location":{"en":"Kyoto","ja":"Kyoto"},"description":{"en":"In this work, a fast mode decision algorithm for H.264/AVC is proposed. In order to reduce the computation complexity of the encoder of H.264/AVC, the proposed algorithm efficiently reduces the candidate modes. The proposed algorithm includes an early skip mode decision method and an adaptive rate distortion cost threshold for early INTER mode decision. A complexity reduction algorithm for INTRA modes which uses the information during INTER mode selection is also proposed. The experimental results show that compared with full-search algorithm the proposed algorithm can achieve up to 70-89% speed up with very slight PSNR loss.","ja":"In this work, a fast mode decision algorithm for H.264/AVC is proposed. In order to reduce the computation complexity of the encoder of H.264/AVC, the proposed algorithm efficiently reduces the candidate modes. The proposed algorithm includes an early skip mode decision method and an adaptive rate distortion cost threshold for early INTER mode decision. A complexity reduction algorithm for INTRA modes which uses the information during INTER mode selection is also proposed. The experimental results show that compared with full-search algorithm the proposed algorithm can achieve up to 70-89% speed up with very slight PSNR loss."},"is_international_presentation":true},"priority":"input_data"}
line:118, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869207"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=188152","label":"url"}],"presentation_title":{"en":"Efficient Mode Selection Algorithm for Inter-Layer Residual Prediction of H.264/SVC","ja":"Efficient Mode Selection Algorithm for Inter-Layer Residual Prediction of H.264/SVC"},"presenters":{"en":[{"name":"Morigami Yoshitaka"},{"name":"Matsuoka Shinpei"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"Morigami Yoshitaka"},{"name":"Matsuoka Shinpei"},{"name":"宋 天"},{"name":"島本 隆"}]},"event":{"en":"The 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2009)","ja":"The 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2009)"},"publication_date":"2009-03-09","languages":["eng"],"promoter":{"en":"Institute of Electronics, Information and Communication Engineers","ja":"Institute of Electronics, Information and Communication Engineers"},"location":{"en":"Okinawa","ja":"Okinawa"},"description":{"en":"This paper presents an efficient mode selection algorithm to reduce the computational complexity when using inter-layer residual prediction of H.264/SVC. Proposed two steps algorithm focuses on the complexity reduction of the inter-layer residual prediction. In the first step, the ordinary routine of rate-distortion optimization (RDO) for H.264/AVC is performed and a temporary best mode (TBM) is selected. Then, in the second step the TBM is used to determine the redundant coding modes from all the candidate modes. The experiment results show that the proposed algorithm can considerably reduce redundant computation complexity with almost no coding efficiency loss.","ja":"This paper presents an efficient mode selection algorithm to reduce the computational complexity when using inter-layer residual prediction of H.264/SVC. Proposed two steps algorithm focuses on the complexity reduction of the inter-layer residual prediction. In the first step, the ordinary routine of rate-distortion optimization (RDO) for H.264/AVC is performed and a temporary best mode (TBM) is selected. Then, in the second step the TBM is used to determine the redundant coding modes from all the candidate modes. The experiment results show that the proposed algorithm can considerably reduce redundant computation complexity with almost no coding efficiency loss."},"is_international_presentation":true},"priority":"input_data"}
line:119, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869208"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=188151","label":"url"}],"presentation_title":{"en":"Motion Based Frame Memory Access Reduction Method for H.264/AVC","ja":"Motion Based Frame Memory Access Reduction Method for H.264/AVC"},"presenters":{"en":[{"name":"Kishida Tomoyuki"},{"name":"Kuniyasu Hiroki"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"Kishida Tomoyuki"},{"name":"Kuniyasu Hiroki"},{"name":"宋 天"},{"name":"島本 隆"}]},"event":{"en":"Proceedings of International Workshop on Nonlinear Circuits and Signal Processing (NCSP'09)","ja":"Proceedings of International Workshop on Nonlinear Circuits and Signal Processing (NCSP'09)"},"publication_date":"2009-03-01","languages":["eng"],"promoter":{"en":"The Research Institute of Signal Processing Japan","ja":"The Research Institute of Signal Processing Japan"},"location":{"en":"Honolulu","ja":"Honolulu"},"description":{"en":"In this paper, considering the features of frame memory access patterns in RDO process, we introduce a novel memory access reduction method by estimating the motion information. The traditional necessary pixels data for the encoding of one macroblock in reference frame is 49 macroblocks. In this work, the search center is estimated by adjacent motion vectors. In the proposed method pixels data of only 9 or 25 macroblocks are adaptively used as reference data for motion estimation. Simulation results show that proposed method can realize about 50∼75% memory access reduction with almost no PSNR degradation.","ja":"In this paper, considering the features of frame memory access patterns in RDO process, we introduce a novel memory access reduction method by estimating the motion information. The traditional necessary pixels data for the encoding of one macroblock in reference frame is 49 macroblocks. In this work, the search center is estimated by adjacent motion vectors. In the proposed method pixels data of only 9 or 25 macroblocks are adaptively used as reference data for motion estimation. Simulation results show that proposed method can realize about 50∼75% memory access reduction with almost no PSNR degradation."},"is_international_presentation":true},"priority":"input_data"}
line:120, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869209"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=180169","label":"url"}],"presentation_title":{"en":"Coding Mode Decision Method for MPEG-2/H.264 Transcoder","ja":"Coding Mode Decision Method for MPEG-2/H.264 Transcoder"},"presenters":{"en":[{"name":"Koeta Eiji"},{"name":"Song Tian"},{"name":"Kondo Takeshi"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"Koeta Eiji"},{"name":"宋 天"},{"name":"Kondo Takeshi"},{"name":"島本 隆"}]},"event":{"en":"International Workshop on Vision, Communications and Circuits (IWVCC2008)","ja":"International Workshop on Vision, Communications and Circuits (IWVCC2008)"},"publication_date":"2008-11-02","languages":["eng"],"location":{"en":"Xi'an","ja":"Xi'an"},"description":{"en":"In this paper, a novel coding mode decision method for MPEG-2/H.264 is proposed. Some previous works showed that the selected INTRA or INTER mode for MPEG-2 is not suitable for H.264/AVC directly. Observing the features of the modes decided by MPEG-2 we find the optimal mode for H.264/AVC can be estimated by reusing existing information in MPEG-2 bitstream. Proposed method can not only select INTRA/INTER mode for H.264/AVC but also reduce the mode candidates of INTER mode by reusing existing encoded information of MPEG-2 bitstream. Simulation results show that the proposed transcoder can achieve high computation complexity reduction rate with very slight PSNR loss.","ja":"In this paper, a novel coding mode decision method for MPEG-2/H.264 is proposed. Some previous works showed that the selected INTRA or INTER mode for MPEG-2 is not suitable for H.264/AVC directly. Observing the features of the modes decided by MPEG-2 we find the optimal mode for H.264/AVC can be estimated by reusing existing information in MPEG-2 bitstream. Proposed method can not only select INTRA/INTER mode for H.264/AVC but also reduce the mode candidates of INTER mode by reusing existing encoded information of MPEG-2 bitstream. Simulation results show that the proposed transcoder can achieve high computation complexity reduction rate with very slight PSNR loss."},"is_international_presentation":true},"priority":"input_data"}
line:121, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869210"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=180168","label":"url"}],"presentation_title":{"en":"Motion Vector Predicted Variable Search Range Motion Estimation Algorithm for H.264/AVC","ja":"Motion Vector Predicted Variable Search Range Motion Estimation Algorithm for H.264/AVC"},"presenters":{"en":[{"name":"Kato Takahiro"},{"name":"Song Tian"},{"name":"Liu Yizhong"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"Kato Takahiro"},{"name":"宋 天"},{"name":"Liu Yizhong"},{"name":"島本 隆"}]},"event":{"en":"International Workshop on Vision, Communications and Circuits (IWVCC2008)","ja":"International Workshop on Vision, Communications and Circuits (IWVCC2008)"},"publication_date":"2008-11-02","languages":["eng"],"location":{"en":"Xi'an","ja":"Xi'an"},"description":{"en":"In this paper, a novel variable search range algorithm for H.264/AVC is proposed. In this work we try to find an adaptive search range selection algorithm to reduce the computation complexity without decreasing encoding efficiency. A novel definition of MVave that is derived from the mean of motion vector in the previous frame is firstly defined to describe the feature of motions in the sequences. Then another parameter of THp is defined to evaluate the distribution of the surrounding motion vectors. Simulation results show that proposed algorithm can reduce 10% of the computation complexity at sequences with less motion and 35% for sequences with more motions.","ja":"In this paper, a novel variable search range algorithm for H.264/AVC is proposed. In this work we try to find an adaptive search range selection algorithm to reduce the computation complexity without decreasing encoding efficiency. A novel definition of MVave that is derived from the mean of motion vector in the previous frame is firstly defined to describe the feature of motions in the sequences. Then another parameter of THp is defined to evaluate the distribution of the surrounding motion vectors. Simulation results show that proposed algorithm can reduce 10% of the computation complexity at sequences with less motion and 35% for sequences with more motions."},"is_international_presentation":true},"priority":"input_data"}
line:122, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869211"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=177651","label":"url"}],"presentation_title":{"en":"Coding Efficiency Improvement with Adaptive GOP Size Selection for H.264/SVC","ja":"Coding Efficiency Improvement with Adaptive GOP Size Selection for H.264/SVC"},"presenters":{"en":[{"name":"Matsuoka Shinpei"},{"name":"Morigami Yoshitaka"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"Matsuoka Shinpei"},{"name":"Morigami Yoshitaka"},{"name":"宋 天"},{"name":"島本 隆"}]},"event":{"en":"International Conference on Innovative Computing, Information and Control (ICICIC2008)","ja":"International Conference on Innovative Computing, Information and Control (ICICIC2008)"},"publication_date":"2008-06-19","languages":["eng"],"promoter":{"en":"IEEE","ja":"IEEE"},"location":{"en":"Dalian, China","ja":"Dalian, China"},"description":{"en":"In this paper, we present a novel adaptive GOP structure (AGS) for H.264/SVC. Proposed method adaptively defines the GOP structure by analyzing the input sequence characters. The accumulated difference of luminance pixel components is utilized to set a threshold for adaptive GOP size definition. Another scene change detection method is also proposed to reorganize the GOP structure. Different from previous AGS methods, the proposed method concentrates on the coding efficiency improvement on the basis of the Hierarchical B-picture structure. The simulation results show that proposed AGS method can improve up to 0.2dB of PSNR compared with fixed size GOP methods.","ja":"In this paper, we present a novel adaptive GOP structure (AGS) for H.264/SVC. Proposed method adaptively defines the GOP structure by analyzing the input sequence characters. The accumulated difference of luminance pixel components is utilized to set a threshold for adaptive GOP size definition. Another scene change detection method is also proposed to reorganize the GOP structure. Different from previous AGS methods, the proposed method concentrates on the coding efficiency improvement on the basis of the Hierarchical B-picture structure. The simulation results show that proposed AGS method can improve up to 0.2dB of PSNR compared with fixed size GOP methods."},"is_international_presentation":true},"priority":"input_data"}
line:123, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869212"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=175880","label":"url"}],"presentation_title":{"en":"Fast Deblocking Filter Implementation Method and It's Architecture for H.264/AVC","ja":"Fast Deblocking Filter Implementation Method and It's Architecture for H.264/AVC"},"presenters":{"en":[{"name":"Hayashi Yoshinori"},{"name":"Song Tian"},{"name":"Koeta Eiji"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"Hayashi Yoshinori"},{"name":"宋 天"},{"name":"Koeta Eiji"},{"name":"島本 隆"}]},"event":{"en":"International Conference in Electrical Engineering/Electronics, Computer, Telecommunications, and Information Technoly (ECTI-CON2008)","ja":"International Conference in Electrical Engineering/Electronics, Computer, Telecommunications, and Information Technoly (ECTI-CON2008)"},"publication_date":"2008-05-14","languages":["eng"],"promoter":{"en":"IEEE","ja":"IEEE"},"location":{"en":"Krabi, Thailand","ja":"Krabi, Thailand"},"description":{"en":"In this work, a fast implementation method for deblocking filter of H.264/AVC and its architecture are proposed. Proposed method makes use of the correlation of the adjacent pixels to decrease the redundant processing cycles. Simulation results show that using proposed method, the average coding cycles for one macroblock is reduced to 170. It is fast than that of the previous works that considered that the least filtering cycle number for one macroblock is 192. Implementation results show that the proposed architecture can be realized using 30.14K gates.","ja":"In this work, a fast implementation method for deblocking filter of H.264/AVC and its architecture are proposed. Proposed method makes use of the correlation of the adjacent pixels to decrease the redundant processing cycles. Simulation results show that using proposed method, the average coding cycles for one macroblock is reduced to 170. It is fast than that of the previous works that considered that the least filtering cycle number for one macroblock is 192. Implementation results show that the proposed architecture can be realized using 30.14K gates."},"is_international_presentation":true},"priority":"input_data"}
line:124, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869213"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=173411","label":"url"}],"presentation_title":{"en":"Switched CABAC/CAVLC Architecture for Real-Time High Profile Applications of H.264/AVC","ja":"Switched CABAC/CAVLC Architecture for Real-Time High Profile Applications of H.264/AVC"},"presenters":{"en":[{"name":"Okamoto Haruhiko"},{"name":"Hayashi Yoshinori"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"Okamoto Haruhiko"},{"name":"Hayashi Yoshinori"},{"name":"宋 天"},{"name":"島本 隆"}]},"event":{"en":"Proceedings of International Workshop on Nonlinear Circuits and Signal Processing (NCSP'08)","ja":"Proceedings of International Workshop on Nonlinear Circuits and Signal Processing (NCSP'08)"},"publication_date":"2008-03-06","languages":["eng"],"promoter":{"en":"The Research Institute of Signal Processing Japan","ja":"The Research Institute of Signal Processing Japan"},"location":{"en":"Gold Coast","ja":"Gold Coast"},"description":{"en":"In this paper, novel entropy coding implementation method and its efficient architecture of H.264/AVC for high bitrate real time HDTV are proposed. The proposed method makes use of this switching bit to adaptively switch the CABAC to CAVLC at the coding peak of CABAC. We also proposed an efficient architecture to realize the proposed switching method. The experimental results show that the proposed method can realize fast coding at the bit generation peak and cut down the buffer consumption with slight bit rate increase.","ja":"In this paper, novel entropy coding implementation method and its efficient architecture of H.264/AVC for high bitrate real time HDTV are proposed. The proposed method makes use of this switching bit to adaptively switch the CABAC to CAVLC at the coding peak of CABAC. We also proposed an efficient architecture to realize the proposed switching method. The experimental results show that the proposed method can realize fast coding at the bit generation peak and cut down the buffer consumption with slight bit rate increase."},"is_international_presentation":true},"priority":"input_data"}
line:125, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869214"},"force":{"see_also":[{"@id":"https://www.scopus.com/record/display.url?eid=2-s2.0-48049101874&origin=inward","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=165678","label":"url"}],"presentation_title":{"en":"Fast Transform and Quantization Architecture with All-Zero Detection and Bit Estimation for H.264/AVC","ja":"Fast Transform and Quantization Architecture with All-Zero Detection and Bit Estimation for H.264/AVC"},"presenters":{"en":[{"name":"Kuniyasu Hiroki"},{"name":"Kishida Tomoyuki"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"Kuniyasu Hiroki"},{"name":"Kishida Tomoyuki"},{"name":"宋 天"},{"name":"島本 隆"}]},"event":{"en":"2007 IEEE International Workshop on Signal Design and Its Applications in Communications(IWSDA'07)","ja":"2007 IEEE International Workshop on Signal Design and Its Applications in Communications(IWSDA'07)"},"publication_date":"2007-09-24","languages":["eng"],"promoter":{"en":"IEEE","ja":"IEEE"},"location":{"en":"Chengdu, China","ja":"Chengdu, China"},"description":{"en":"In this paper a fast processing architecture for the transform and quantization of the H.264/AVC, named DQ Engine, is proposed. The proposed DQ engine architecture could achieve 2 times fast processing of transform and quantization together with the inverse transform and inverse quantization when the rate-distortion optimization is performed. Moreover, proposed architecture introduced an all-zero block detection architecture that could cut down the redundant processing of the all-zero coefficient blocks. A bit estimation architecture is also introduced into the DQ Engine to fulfill fast estimation of the generated bits. Implementation results show that the proposed architecture could be fulfilled with only 126,728 transistors.","ja":"In this paper a fast processing architecture for the transform and quantization of the H.264/AVC, named DQ Engine, is proposed. The proposed DQ engine architecture could achieve 2 times fast processing of transform and quantization together with the inverse transform and inverse quantization when the rate-distortion optimization is performed. Moreover, proposed architecture introduced an all-zero block detection architecture that could cut down the redundant processing of the all-zero coefficient blocks. A bit estimation architecture is also introduced into the DQ Engine to fulfill fast estimation of the generated bits. Implementation results show that the proposed architecture could be fulfilled with only 126,728 transistors."},"is_international_presentation":true},"priority":"input_data"}
line:126, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869215"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=164946","label":"url"}],"presentation_title":{"en":"Efficient Motion Compensation Architecture with Rate-Distortion Optimization for H.264/AVC","ja":"Efficient Motion Compensation Architecture with Rate-Distortion Optimization for H.264/AVC"},"presenters":{"en":[{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"宋 天"},{"name":"島本 隆"}]},"event":{"en":"International Conference on Signal Processing and Multimedia Applications(SIGMAP2007)","ja":"International Conference on Signal Processing and Multimedia Applications(SIGMAP2007)"},"publication_date":"2007-07-28","languages":["eng"],"promoter":{"en":"IEEE","ja":"IEEE"},"location":{"en":"Barcelona, Spain","ja":"Barcelona, Spain"},"description":{"en":"In this paper, novel motion compensation architecture is proposed to support the Rate-Distortion Optimization (RDO) in H.264/AVC. First, the scope of the motion compensation in this work is defined not only including the half and quarter pixel motion compensation but also the deblocking filter and rate-distortion optimization. Then, based on the new concept of motion compensation an efficient architecture for H.264/AVC codec is constructed. Pipelined processing structure is designed for sub-block mode selection to achieve real-time processing for up to HDTV resolution inputs. Implementation result shows that proposed architecture could be realized with only 42,280 gates and 48,320 bits SRAM.","ja":"In this paper, novel motion compensation architecture is proposed to support the Rate-Distortion Optimization (RDO) in H.264/AVC. First, the scope of the motion compensation in this work is defined not only including the half and quarter pixel motion compensation but also the deblocking filter and rate-distortion optimization. Then, based on the new concept of motion compensation an efficient architecture for H.264/AVC codec is constructed. Pipelined processing structure is designed for sub-block mode selection to achieve real-time processing for up to HDTV resolution inputs. Implementation result shows that proposed architecture could be realized with only 42,280 gates and 48,320 bits SRAM."},"is_international_presentation":true},"priority":"input_data"}
line:127, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869216"},"force":{"see_also":[{"@id":"https://www.scopus.com/record/display.url?eid=2-s2.0-34548848259&origin=inward","label":"url"},{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=159164","label":"url"}],"presentation_title":{"en":"Adaptive Search Range Motion Estimation Algorithm for H.264/AVC","ja":"Adaptive Search Range Motion Estimation Algorithm for H.264/AVC"},"presenters":{"en":[{"name":"Song Tian"},{"name":"Ogata Kazuhiro"},{"name":"Saito Kosuke"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"宋 天"},{"name":"Ogata Kazuhiro"},{"name":"Saito Kosuke"},{"name":"島本 隆"}]},"event":{"en":"2007 IEEE International Symposium on Circuits and Systems(ISCAS'07)","ja":"2007 IEEE International Symposium on Circuits and Systems(ISCAS'07)"},"publication_date":"2007-05-27","languages":["eng"],"promoter":{"en":"IEEE","ja":"IEEE"},"location":{"en":"New Orleans","ja":"New Orleans"},"description":{"en":"In this paper, a novel variable search range algorithm is proposed for the H.264/AVC. From simulation results we find that how much the search range could be reduced to achieve an optimum search range have strong relation with the average of the frame motion vectors. Based on these simulation results an adaptive search range algorithm which estimate the most efficient search range from the previous frames with a adaptively search range adjustment method is proposed. Simulation results show that proposed algorithm could achieve the motion estimation by average 45% computation complexity compare with the reference software with equivalent PSNR and the bitrate results.","ja":"In this paper, a novel variable search range algorithm is proposed for the H.264/AVC. From simulation results we find that how much the search range could be reduced to achieve an optimum search range have strong relation with the average of the frame motion vectors. Based on these simulation results an adaptive search range algorithm which estimate the most efficient search range from the previous frames with a adaptively search range adjustment method is proposed. Simulation results show that proposed algorithm could achieve the motion estimation by average 45% computation complexity compare with the reference software with equivalent PSNR and the bitrate results."},"is_international_presentation":true},"priority":"input_data"}
line:128, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869217"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=153734","label":"url"}],"presentation_title":{"en":"Efficient Variable Search Range Motion Estimation Architecture for Real-time RDO of H.264/AVC","ja":"Efficient Variable Search Range Motion Estimation Architecture for Real-time RDO of H.264/AVC"},"presenters":{"en":[{"name":"Saito Kosuke"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"Saito Kosuke"},{"name":"宋 天"},{"name":"島本 隆"}]},"event":{"en":"Proceedings of RISP International Workshop on Nonlinear Circuits and Signal Processing (NCSP'07)","ja":"Proceedings of RISP International Workshop on Nonlinear Circuits and Signal Processing (NCSP'07)"},"publication_date":"2007-03-04","languages":["eng"],"promoter":{"en":"The Research Institute of Signal Processing Japan","ja":"The Research Institute of Signal Processing Japan"},"location":{"en":"Shanghai","ja":"Shanghai"},"description":{"en":"In this paper, novel motion estimation architecture of H.264/AVC is proposed. To reduce the computation complexity of RDO calculation, we propose a TAD+Top-down method with hardware-friendly structure that could efficiently reduce the number of candidate coding modes. The proposed architecture could support the variable search range motion estimation from the range 0 to ±16, which is possible to cooperate with any kind of variable search range methods proposed so far. The experimental results show that the proposed method could reduce computation complexity of motion estimation 80% average without PSNR and bitrate loss compared with the reference software JM8.2.","ja":"In this paper, novel motion estimation architecture of H.264/AVC is proposed. To reduce the computation complexity of RDO calculation, we propose a TAD+Top-down method with hardware-friendly structure that could efficiently reduce the number of candidate coding modes. The proposed architecture could support the variable search range motion estimation from the range 0 to ±16, which is possible to cooperate with any kind of variable search range methods proposed so far. The experimental results show that the proposed method could reduce computation complexity of motion estimation 80% average without PSNR and bitrate loss compared with the reference software JM8.2."},"is_international_presentation":true},"priority":"input_data"}
line:129, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869218"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=153733","label":"url"}],"presentation_title":{"en":"Multi-State Estimated Architecture of CABAC for H.264/AVC","ja":"Multi-State Estimated Architecture of CABAC for H.264/AVC"},"presenters":{"en":[{"name":"Yamada Atsushi"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"Yamada Atsushi"},{"name":"宋 天"},{"name":"島本 隆"}]},"event":{"en":"Proceedings of RISP International Workshop on Nonlinear Circuits and Signal Processing (NCSP'07)","ja":"Proceedings of RISP International Workshop on Nonlinear Circuits and Signal Processing (NCSP'07)"},"publication_date":"2007-03-03","languages":["eng"],"promoter":{"en":"The Research Institute of Signal Processing Japan","ja":"The Research Institute of Signal Processing Japan"},"location":{"en":"Shanghai","ja":"Shanghai"},"description":{"en":"In this paper, a novel fast context-adaptive binary arithmetic coder (CABAC) implementation method and an efficient architecture are proposed. Proposed method achieve multi-bits arithmetic coding in one cycle by introducing a Multi-State Estimation(MSE) scheme which accomplish multiple update of state, range and low in one cycle. Discussing the tradeoff between the coding speed and the hardware resource, we give an example solution of two-state estimation implementation with which could cut down half of the coding cycles. We also proposed an efficient architecture with a selectable memory solution for different target applications. Implementation result shows that proposed method could be realized with about 20,000 gates.","ja":"In this paper, a novel fast context-adaptive binary arithmetic coder (CABAC) implementation method and an efficient architecture are proposed. Proposed method achieve multi-bits arithmetic coding in one cycle by introducing a Multi-State Estimation(MSE) scheme which accomplish multiple update of state, range and low in one cycle. Discussing the tradeoff between the coding speed and the hardware resource, we give an example solution of two-state estimation implementation with which could cut down half of the coding cycles. We also proposed an efficient architecture with a selectable memory solution for different target applications. Implementation result shows that proposed method could be realized with about 20,000 gates."},"is_international_presentation":true},"priority":"input_data"}
line:130, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869219"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=147083","label":"url"}],"presentation_title":{"en":"Frame Memory Compression Method for H.264/AVC","ja":"Frame Memory Compression Method for H.264/AVC"},"presenters":{"en":[{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"宋 天"},{"name":"島本 隆"}]},"event":{"en":"The 2006 International Technical Conference on Circuits/Systems, Computers and Communications","ja":"The 2006 International Technical Conference on Circuits/Systems, Computers and Communications"},"publication_date":"2006-07-10","languages":["eng"],"location":{"en":"Chiang Mai, Thailand","ja":"Chiang Mai, Thailand"},"description":{"en":"In this paper, a novel frame memory compression method for the H.264/AVC is proposed. Proposed method introduce DAP (Differential of Adjacent Pixel) and Huffman coding to the original image data between the frame memory interface and the image coding process. Simulation results shows that this method can achieve not only a stable compression rate but also realize a lossless compression which cause no additional information loss to the coding process. Furthermore, proposed method is hardware-friendly and cause no further delay during the memory access period. Proposed method can be realized by only about 7,000 gates.","ja":"In this paper, a novel frame memory compression method for the H.264/AVC is proposed. Proposed method introduce DAP (Differential of Adjacent Pixel) and Huffman coding to the original image data between the frame memory interface and the image coding process. Simulation results shows that this method can achieve not only a stable compression rate but also realize a lossless compression which cause no additional information loss to the coding process. Furthermore, proposed method is hardware-friendly and cause no further delay during the memory access period. Proposed method can be realized by only about 7,000 gates."},"is_international_presentation":true},"priority":"input_data"}
line:131, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869220"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=142437","label":"url"}],"presentation_title":{"en":"Evolutional Algorithms of A Steiner Tree Problem in 3-D VLSI","ja":"Evolutional Algorithms of A Steiner Tree Problem in 3-D VLSI"},"presenters":{"en":[{"name":"Kawaoka Yasunori"},{"name":"Shimamoto Takashi"},{"name":"Song Tian"}],"ja":[{"name":"Kawaoka Yasunori"},{"name":"島本 隆"},{"name":"宋 天"}]},"event":{"en":"Proceedings of RISP International Workshop on Nonlinear Circuits and Signal Processing (NCSP'06)","ja":"Proceedings of RISP International Workshop on Nonlinear Circuits and Signal Processing (NCSP'06)"},"publication_date":"2006-03-03","languages":["eng"],"promoter":{"en":"The Research Institute of Signal Processing Japan","ja":"The Research Institute of Signal Processing Japan"},"location":{"en":"Honolulu","ja":"Honolulu"},"description":{"en":"In this paper, we propose an efficient routing algorithm for 3-D VLSI. In our method, first, we construct a Euclidian minimum spanning tree and then obtain individual 3-D rectilinear Steiner tree by replacing each pair of terminals in the tree with segments that are parallel to X, Y, or Z-axis using genetic algorithms. Secondly, we shuffling the order of wiring net, replacing each wiring pair and applying to Breadth First Search (BFS) algorithms to those under optimized nets. Several simulation results demonstrate that our method can achieve an optimized total wire length and radius with a higher routing ratio.","ja":"In this paper, we propose an efficient routing algorithm for 3-D VLSI. In our method, first, we construct a Euclidian minimum spanning tree and then obtain individual 3-D rectilinear Steiner tree by replacing each pair of terminals in the tree with segments that are parallel to X, Y, or Z-axis using genetic algorithms. Secondly, we shuffling the order of wiring net, replacing each wiring pair and applying to Breadth First Search (BFS) algorithms to those under optimized nets. Several simulation results demonstrate that our method can achieve an optimized total wire length and radius with a higher routing ratio."},"is_international_presentation":true},"priority":"input_data"}
line:132, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869221"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=135524","label":"url"}],"presentation_title":{"en":"Complexity Reduced Variable Block Size Motion Estimation Algorithm for H.264","ja":"Complexity Reduced Variable Block Size Motion Estimation Algorithm for H.264"},"presenters":{"en":[{"name":"Kosuke Saito"},{"name":"Song Tian"},{"name":"Shimamoto Takashi"}],"ja":[{"name":"Kosuke Saito"},{"name":"宋 天"},{"name":"島本 隆"}]},"event":{"en":"The 2005 International Technical Conference on Circuits/Systems, Computers and Communications","ja":"The 2005 International Technical Conference on Circuits/Systems, Computers and Communications"},"publication_date":"2005-07-04","languages":["eng"],"location":{"en":"Cheju","ja":"Cheju"},"description":{"en":"In this paper, a Block Size-Estimated Variable Block Size Motion Estimation (BSE-VBSME) algorithm is proposed. First, we discussed two proposed methods to estimate the motion estimation block size utilizing temporal block size information of previous frame and the spatial information of the current block. Then, a novel algorithm is proposed to decrease the computation complexity of VBSME by integrating traditional top-down and bottom-up methods into proposed block size estimation methods. Compared with the traditional VBSME algorithm recommended by JM8, the proposed method shows about 50% average computation reduction with almost no quality and bitrate loss.","ja":"In this paper, a Block Size-Estimated Variable Block Size Motion Estimation (BSE-VBSME) algorithm is proposed. First, we discussed two proposed methods to estimate the motion estimation block size utilizing temporal block size information of previous frame and the spatial information of the current block. Then, a novel algorithm is proposed to decrease the computation complexity of VBSME by integrating traditional top-down and bottom-up methods into proposed block size estimation methods. Compared with the traditional VBSME algorithm recommended by JM8, the proposed method shows about 50% average computation reduction with almost no quality and bitrate loss."},"is_international_presentation":true},"priority":"input_data"}
line:133, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869222"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=288412","label":"url"}],"presentation_title":{"en":"Low Complexity Triplet Search Motion Estimation for H.264","ja":"Low Complexity Triplet Search Motion Estimation for H.264"},"presenters":{"en":[{"name":"Song Tian"},{"name":"Fujita Gen"},{"name":"Onoe Takao"},{"name":"Shirakawa Isao"}],"ja":[{"name":"宋 天"},{"name":"Fujita Gen"},{"name":"Onoe Takao"},{"name":"Shirakawa Isao"}]},"event":{"en":"International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)","ja":"International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)"},"publication_date":"2004-07","languages":["eng"],"location":{"en":"Sendai","ja":"Sendai"},"description":{"en":"In this paper, we propose a fast motion estimation method for H.264, named Triplet Search Motion Estimation(TS-ME). In the same manner as typical traditional fast motion estimation methods such as Three Steps Search(TSS) and Diamond Search(DS), TS-ME is based on the hierarchic motion search, while introducing some new features, 1) high accuracy first step search using triplet patterns, 2) computational cost reduction by referring surrounding motion vectors, and 3) computational cost reduction for sub pixel motion search in accordance with the motion vector appearance probability. From the simulation results, estimation speed is improved by a factor of up to 38 comparing to the JM7.3 reference code of H.264, with very slight loss in picture quality.","ja":"In this paper, we propose a fast motion estimation method for H.264, named Triplet Search Motion Estimation(TS-ME). In the same manner as typical traditional fast motion estimation methods such as Three Steps Search(TSS) and Diamond Search(DS), TS-ME is based on the hierarchic motion search, while introducing some new features, 1) high accuracy first step search using triplet patterns, 2) computational cost reduction by referring surrounding motion vectors, and 3) computational cost reduction for sub pixel motion search in accordance with the motion vector appearance probability. From the simulation results, estimation speed is improved by a factor of up to 38 comparing to the JM7.3 reference code of H.264, with very slight loss in picture quality."},"is_international_presentation":true},"priority":"input_data"}
line:134, {"insert":{"user_id":"5000080634","type":"presentations","id":"42869223"},"force":{"see_also":[{"@id":"https://web.db.tokushima-u.ac.jp/cgi-bin/edb_browse?EID=288408","label":"url"}],"presentation_title":{"en":"Low Power Architecture for H.263 Version2 Codec","ja":"Low Power Architecture for H.263 Version2 Codec"},"presenters":{"en":[{"name":"Song Tian"},{"name":"Fujita Gen"},{"name":"Onoe Takao"},{"name":"Shirakawa Isao"}],"ja":[{"name":"宋 天"},{"name":"Fujita Gen"},{"name":"Onoe Takao"},{"name":"Shirakawa Isao"}]},"event":{"en":"International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)","ja":"International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)"},"publication_date":"2001-07-10","languages":["eng"],"location":{"en":"Tokushima","ja":"Tokushima"},"description":{"en":"In this paper, an efficient algorithm and its VLSI architecture are proposed for H.263 version2. In the H.263 version2, there are 3 main extension are recommended. To these 3 extensions, 3 different algorithms are proposed to realize small area and low power VLSI implementation, respectively. Because these algorithms are hardware oriented improvement for H.263 version2, a very small hardware cost are needed in addition to original H.263 codec.","ja":"In this paper, an efficient algorithm and its VLSI architecture are proposed for H.263 version2. In the H.263 version2, there are 3 main extension are recommended. To these 3 extensions, 3 different algorithms are proposed to realize small area and low power VLSI implementation, respectively. Because these algorithms are hardware oriented improvement for H.263 version2, a very small hardware cost are needed in addition to original H.263 codec."},"is_international_presentation":true},"priority":"input_data"}
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