Tokushima University / Educator and Researcher Directory --- Tamesada, Takeomi

Field of Study

○	Electronic Circuit Engineering

Subject of Study

○	高速演算回路, 論理回路の設計と検査 (logic circuit, design and test)

Book / Paper

Book:

1.	石黒美種, 仁田工吉, Norio Akamatsu, 生田信晧, Katsuo Isaka, Akio Ushida, Hiroshi Kawakami, Yohsuke Kinouchi, 小林邦博, 島田良作, Takayuki Suzuki, Takeomi Tamesada, 森一郎, Masuo Fukui and 横井良秀 : 電気·電子工学実験(electrical and eiectronic experiments,in japanese), 産業図書, Tokyo, Apr. 1974. (Summary) 本書は，電気電子工学を学ぶ学生のための実験指導書である．内容は基礎実験，材料·能動素子実験，電気機器実験，電力·照明実験，制御及びアナログ演算実験，パルスおよびデジタル回路実験，通信工学実験などの項目で構成されている．第3章:材料および能動素子の実験のホール効果，比抵抗の測定，光電変換素子についての原理，実験方法などを解説した．

Academic Paper (Judged Full Paper):

1.	月本功, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : ばらつきを有するICで構成したTTL回路の電源電流による統計的断線故障検出法, Journal of Japan Institute of Electronics Packaging, Vol.8, No.3, 199-207, 2005. (Summary) In this paper, a supply-current test method is proposed for detecting open faults in logic circuits made of TTL ICs on printed circuit boards. This method is applicable even if there is any variation of the supply current among the ICs used. In this method, variation of the supply current in a logic circuit is modeled as a Gaussian distribution and a statistical analysis method with level of significance is used for fault detection. In this paper, the fault coverage of the test method is evaluated experimentally. In the experimental evaluation, test input vectors of the supply-current test method are generated for detecting single open faults of signal lines in ISCAS-85 benchmark circuits made of TTL SSIs. The results show that more open faults can be detected by this test method than by a functional test method if the deviation (ς/μ) of the supply current in each SSI used is smaller than 1.1%. (Keyword) Open / Supply Current Test / TTL (Link to Publication Site) ● Publication site (DOI): 10.5104/jiep.8.199 (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1520853834658646016 ● Search Scopus @ Elsevier (DOI): 10.5104/jiep.8.199 (DOI: 10.5104/jiep.8.199, CiNii: 1520853834658646016)
2.	Masaki Hashizume, Teruyoshi Matsushima, Takashi Shimamoto, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Akio Sakamoto : Genetic State Reduction Method of Incompletely Specified Machines, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E87-A, No.6, 1555-1563, 2004. (Summary) A new state reduction method of incompletely specified sequential machines is proposed in this paper. The method is based on a genetic algorithm implementing a dormant mechanism. MCNC benchmark machines are simplified by using this method to evaluate the method. The experimental results show that machines of almost the same number of states as the minimum ones can be derived by this method. (Keyword) incompletely specified machine / maximal compatible set / state reduction (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1574231877208281344 ● Summary page in Scopus @ Elsevier: 2-s2.0-3042693560 (CiNii: 1574231877208281344, Elsevier: Scopus)
3.	Masao Takagi, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Lead Open Detection Based on Supply Current of CMOS LSIs, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E87-A, No.6, 1330-1337, 2004. (Summary) In this paper, a test method is proposed to detect lead opens in CMOS LSIs. The test method is based on supply current which flows when test input vectors and AC electric field are provided from the outside of the ICs. Also, an application method of the test input vectors is proposed in this paper. It is shown experimentally that lead opens of SSIs and LSIs will be detected by providing each of the test input vectors per the period of AC electric field applied. (Keyword) lead open / CMOS LSI / supply current test / electric field (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1572261552371298560 ● Summary page in Scopus @ Elsevier: 2-s2.0-3042543542 (CiNii: 1572261552371298560, Elsevier: Scopus)
4.	Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Test Sequence Generation for Test Time Reduction of IDDQ Testing, IEICE Transactions on Information and Systems, Vol.E87-D, No.3, 537-543, 2004. (Summary) In this paper, test time reduction for IDDQ testing is discussed. Although IDDQ testing is known to be effective to detect faults in CMOS circuit, test time of IDDQ testing is larger than that of logic testing since supply current is measured after a circuit is in its quiescent state. It is shown by simulation that test time of IDDQ test mostly depends on switching current. A procedure to modify test vectors and a procedure to arrange test vectors are presented for reducing the test time of IDDQ testing. A test sequence is modified such that switching current quickly disappears. The procedure utilizes a unit delay model to estimate the time of the last transition of logic value from L to H in a circuit. Experimental results for benchmark circuits show the effectiveness of the procedure. (Keyword) IDDQ testing / bridging faults / switching current / supply current test / CMOS circuits (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1570009752557232384 ● Summary page in Scopus @ Elsevier: 2-s2.0-1642322367 (CiNii: 1570009752557232384, Elsevier: Scopus)
5.	Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Identification and Frequency Estimation of Feedback Bridging Faults Generating Logical Oscillation in CMOS Circuits, IEICE Transactions on Information and Systems, Vol.E87-D, No.3, 571-579, 2004. (Summary) When a feedback bridging fault occurs in a combinational circuit and it is activated, logical oscillation may occur in the circuit. In this paper, some electrical conditions are proposed to identify whether a feedback bridging fault occurs logical oscillation. Also, it is proposed how to estimate the oscillation frequency. They are based on piece linearized models and do not require circuit simulation of large size of circuits. They are evaluated by some experiments. In the experiments, all of the feedback bridging faults occurring logical oscillation are identified. Also, oscillation frequencies larger than the ones obtained by SPICE simulation are derived by the proposed estimation method in the experiments. It promises us that the methods will be used for identifying such bridging faults and estimating the oscillation frequencies. (Keyword) feedback bridging fault / combinational circuit / logical oscillation (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1571980077394203904 ● Summary page in Scopus @ Elsevier: 2-s2.0-1642388921 (CiNii: 1571980077394203904, Elsevier: Scopus)
6.	Hiroyuki Yotsuyanagi, Taisuke Iwakiri, Masaki Hashizume and Takeomi Tamesada : Test Pattern Generation for CMOS Open Defect Detection by Supply Current Testing under AC Electric Field, IEICE Transactions on Information and Systems, Vol.E86-D, No.12, 2666-2673, 2003. (Summary) In this paper, supply current testing for detecting open defects in CMOS circuits is discussed. It is known that open defects cause unpredictable faulty effects and are difficult to be detected. In our test method, an AC electric field is applied during testing. The voltage at a floating node caused by an open defect is varied by the applied electric field and then the defect can be detected. The test pattern generation procedure for open defects is proposed and is applied to benchmark circuits. The experimental results shows that the number of test vectors for opens are much smaller than that for stuck-at faults. The experimental evaluation for an LSI chip is also shown to present the feasibility of our test method. (Keyword) open defects / supply current test / CMOS circuits / electric field (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1573668927254908928 ● Summary page in Scopus @ Elsevier: 2-s2.0-0842332030 (CiNii: 1573668927254908928, Elsevier: Scopus)
7.	Masaki Hashizume, 田坂英司, Hiroyuki Yotsuyanagi, Takeomi Tamesada, 茅原敏広, Ikuro Morita and Takahiro Oie : CMOSマイクロコンピュータ回路の電源電流によるブリッジ故障検出法, Journal of Japan Institute of Electronics Packaging, Vol.6, No.7, 564-572, 2003. (Summary) A new supply current test method is proposed for bridging faults in CMOS microprocessor based circuits which are implemented circuit boards with discrete ICs. The method is based on supply current of a circuit under test, which flows when a test program is executed. A commercial microcomputer circuit is tested by the proposed method. In the tests, 98.7% of the bridging faults between two neighboring pins in the circuit are detected within 326 msec. It promises us that the method can be used in production tests of microprocessor based circuits. Also, it is sown that the test program can be developed by means of timing charts in data sheets of the microprocessor. (Keyword) Bridging Fault / Microcomputer / Supply Current Testing (Link to Publication Site) ● Publication site (DOI): 10.5104/jiep.6.564 (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1520290884709986560 ● Search Scopus @ Elsevier (DOI): 10.5104/jiep.6.564 (DOI: 10.5104/jiep.6.564, CiNii: 1520290884709986560)
8.	Masahiro Ichimiya, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : A Test Circuit for Pin Shorts Generating Oscillation in CMOS Logic Circuits, The Transactions of the Institute of Electronics, Information and Communication Engineers D-I, Vol.J86-D-I, No.6, 402-411, 2003. (Summary) CMOS論理ICをプリント配線板上にはんだ付けする際，ICピン短絡故障が発生する可能性がある．その故障励起時に，故障発生箇所に論理発振が生じる場合がある．その論理発振を生じる故障を論理回路に流れる電源電流によって検出するための検査法とその検査回路を本論文では提案している．実際にその検査回路を試作し，故障励起時に論理発振を生じる故障がその検査回路で検出できることを実験により明らかにしている． (Keyword) ICピン短絡故障 / 検査回路 / CMOS論理回路 / フィードバックブリッジ故障 / 電流テスト (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1520572357417353088 (CiNii: 1520572357417353088)
9.	Masahiro Ichimiya, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Pin Open Detection for CMOS Logic ICs by Measuring Supply Current under AC Electric Field, Journal of Japan Institute of Electronics Packaging, Vol.6, No.2, 140-146, 2003. (Summary) A new test method is proposed in this paper for detecting pin opens in CMOS logic circuits fabricated on printed circuit boards, which are caused by missing solder and so on. In our test method, supply current of an IC is measured with AC electric filed applied outside of CMOS ICs. When any pin opens do not occur in the IC, only quiescent supply current will flow. If a pin open occurs, large supply current change will be generated. The proposed test method uses this property for detecting pin opens. In this paper, the feasibility of the test method is evaluated by some experiments. Also, the test input vectors are proposed for this test method. (Keyword) Current Testing / Pin Open / CMOS Logic Circuit / Electric Field (Link to Publication Site) ● Publication site (DOI): 10.5104/jiep.6.140 (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1520853834658559360 ● Search Scopus @ Elsevier (DOI): 10.5104/jiep.6.140 (DOI: 10.5104/jiep.6.140, CiNii: 1520853834658559360)
10.	Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : CMOS Open Defect Detection by Supply Current Measurement under Time-Variable Electric Field Supply, IEICE Transactions on Information and Systems, Vol.E85-D, No.10, 1542-1550, 2002. (Summary) In this paper, a new test method is proposed for detecting open defects in CMOS logic ICs. The method is based on supply current of ICs generated by supplying time-variable supply voltage and electric field from the outside of the ICs. Also, test input vectors for the test method are proposed and it is shown that they can be generated more easily than functional test methods based on stuck-at fault models. The feasibility of the test is examined by some experiments. The empirical results promise us that by using the method, open defects in CMOS ICs can be detected. (Keyword) open defect / CMOS / supply current test / electric field (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1574231876981112832 ● Summary page in Scopus @ Elsevier: 2-s2.0-0036825554 (CiNii: 1574231876981112832, Elsevier: Scopus)
11.	Masaki Hashizume, Hiroshi Hoshika, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Testable Static CMOS PLA for IDDQ Testing, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E84-A, No.6, 1488-1495, 2001. (Summary) A new IDDQ tastable design method is proposed for static CMOS PLA circuits. A testable PLA circuit of NOR-NOR type is designed using this method. It is shown that all bridging faults in NOR planes of the tastable designed PLA circuit can be detected by IDDQ testing with 4 sets of test input vectors. The test input vectors are independent of the logical functions to be realized in the PLA circuit. PLA circuits are designed using this method so that the quiescent supply current generated when they are tested will be zero. Thus, high resolution of IDDQ tests for the PLA circuits can be obtained by using the testable design method. Results of IDDQ tests of PLA circuits designed using this testable design method confirm not that the expected output can be generated from the circuits but that the circuits are fabricated without bridging faults in NOR planes. Since bridging faults often occur in state-of-the-art IC fabrication, the testable design is indispensable for realizing highly reliable logic systems. (Keyword) static PLA / testable design / IDDQ test / bridging fault (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1571135652357071360 ● Summary page in Scopus @ Elsevier: 2-s2.0-0035367034 (CiNii: 1571135652357071360, Elsevier: Scopus)
12.	Masaki Hashizume, Takeomi Tamesada, 小山健 and A.J. van de Goor : CMOS SRAM ICの書き込み時静的電源電流による論理故障検出法, The Transactions of the Institute of Electronics, Information and Communication Engineers D-I, Vol.J82-D-I, No.7, 906-915, 1999.
13.	口井敏匡, Masaki Hashizume and Takeomi Tamesada : プリント回路板上のTTL組み合わせ回路の電源電流による断線故障検出法, Journal of Japan Institute of Electronics Packaging, Vol.1, No.4, 284-293, 1998.
14.	Masaki Hashizume, Takeomi Tamesada, Takashi Shimamoto and Akio Sakamoto : Heuristic State Reduction Methods of Incompletely Specified Machines Preceding to Satisfy Covering Condition, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E81-A, No.6, 1045-1054, 1998. (Summary) This paper presents two kinds of simplification methods for incompletely specified sequential machines. The strategy of the methods is that as many states in original machines are covered in the simplification processes as possible. With the methods, one of the minimal machines can not be always derived, but a near-minimal machine can be obtained more quickly with less memory. In this paper, the effectiveness of the methods is checked by applying them to simplification problems of incompletely specified machines generated by using random numbers, and of the MCNC benchmark machines. The experimental results show that our methods can derive a simplified machine quickly.
15.	Masaki Hashizume, 矢野武志, 口井敏匡 and Takeomi Tamesada : 電流テストによるバイポーラ組合せ論理回路のブリッジ故障検出のための検査容易化設計法, The Transactions of the Institute of Electronics, Information and Communication Engineers D-I, Vol.J79-I, No.12, 1092-1104, 1996.
16.	Masaki Hashizume, Y. Iwata and Takeomi Tamesada : Performance Evaluation for Fault Detection of Analog Electronic Circuits, Fuzzy Logic and Its Applications to Engineering, 255-264, 1995.
17.	Masaki Hashizume, Takeomi Tamesada and Koji Nii : Fuzzy Multiobjective Satisficing Programming Utilizing Expertise Knowledge, Fuzzy Optimization Recent Advances, 220-233, 1994.
18.	Masaki Hashizume, Takeomi Tamesada and 新居浩二 : 下限満足度制約をもつファジィ多目的計画問題の近似的満足解導出法, The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.J74-D-I, No.2, 109-116, 1991.
19.	Masaki Hashizume, Takeomi Tamesada and 新居浩二 : 凸ファジー決定によるアナログ回路の回路定数最適化法, The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.J73-A, No.8, 1350-1358, 1990.
20.	Masaki Hashizume and Takeomi Tamesada : TTL組合せ論理回路の電源電流による故障検出法, The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.J73-D-I, No.7, 621-629, 1990.
21.	Masaki Hashizume, 桝田真喜夫, 山田和浩 and Takeomi Tamesada : 自己回帰モデルを用いた電源電流波形による論理回路の故障診断法, The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.J71-D, No.9, 1804-1814, 1988.
22.	Takeomi Tamesada : 最小冗長P進表現を用いた高速除算, The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.J71-D, No.6, 957-965, 1988.
23.	Takeomi Tamesada : 必要最小冗長P進表現を用いた高速複数オペランド加減算, The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.J71-D, No.4, 626-635, 1988.
24.	Takeomi Tamesada : 最小冗長P進表現を用いた高速乗算, The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.J71-D, No.1, 44-51, 1988.
25.	Takeomi Tamesada : 最小冗長P進表現を用いた高速加減算, The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.J70-D, No.10, 1853-1858, 1987.
26.	Masaki Hashizume, 山本博資, Takeomi Tamesada and 埴渕敏明 : 内容検索メモリを用いた検索システムの速度性能の評価, The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.J70-D, No.9, 1709-1717, 1987.
27.	Takeomi Tamesada : 無安定マルチバイブレータの再生転移に関する基礎解析, The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.J69-D, No.2, 248-258, 1986.
28.	Takeomi Tamesada and 山本博資 : TTL-NANDゲートを用いた無安定マルチバイブレータの動作モード解析, The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.J65-D, No.2, 218-225, 1982.
29.	Takeomi Tamesada : Sequential Machines having Quasi-Stable States and Their State Reduction, Transactions of the IEICE of Japan, Vol.E-64, No.3, 147-154, 1981.
30.	Takeomi Tamesada : Sequential Machines having Quasi-Stable States, Transactions on Computers, Vol.C-29, No.5, 405-408, 1980.
31.	木下敏治, 原田尚文, Takeomi Tamesada, 稲井義正 and 榊原久司 : 電動義手の柔らかい協調動作制御の一方式, バイオメカニズム, Vol.2, No.2, 121-130, 1978.
32.	Takeomi Tamesada, 原田尚文 and 島田良作 : 3個のNAND/NOR回路を基本回路とする3相マルチバイブレータ, The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.59-D, No.9, 605-612, 1976.
33.	Takeomi Tamesada, 原田尚文 and 島田良作 : 準安定状態をもつ順序回路の合成, The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.59-D, No.4, 276-283, 1976.
34.	Takeomi Tamesada, 原田尚文 and 島田良作 : 準安定状態をもつ順序論理回路とその論理解析, The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.59-D, No.2, 69-76, 1976.
35.	島田良作 and Takeomi Tamesada : RS形双安定回路の転移条件と臨界トリガ·パルス, IEICE Transactions on Electronics, Vol.52, No.4, 226-232, 1969.

Academic Paper (Unrefereed Paper):

1.	木下敏治, Takeomi Tamesada, 高木正夫, 高橋直樹 and 垂水靖志 : 近似制御式を用いた肩義手の顔面方位制御システム, 詫間電波工業高等専門学校研究紀要, No.17, 59-72, 1989.
2.	Takeomi Tamesada and Masahiro Ichimiya : ECLゲートを用いた無安定マルチバイブレータの特性, Bulletin of Faculty of Engineering, The University of Tokushima, No.34, 45-55, 1989.
3.	木下敏治, 高木正夫, Takeomi Tamesada, 顧蘭明 and 倉本雅史 : X-Y-Z座標変換制御アルゴリズムを用いた肩義手の上体方位制御システム, 詫間電波工業高等専門学校研究紀要, No.16, 61-75, 1988.
4.	長岡暁, 細川義夫, 木下敏治, 原田尚文 and Takeomi Tamesada : 電動義手の視点制御方式の改良に関する研究, Bulletin of Faculty of Engineering, The University of Tokushima, No.24, 77-86, 1979.
5.	山本友一郎, 榊原久司, 原田尚文, 島田良作 and Takeomi Tamesada : 表面筋電図と針電極筋電図の比較について, Bulletin of Faculty of Engineering, The University of Tokushima, No.19, 113-123, 1974.
6.	西野豊, 原田尚文, 島田良作, Takeomi Tamesada and 榊原久司 : 電動義手の協調動作制御回路について, Bulletin of Faculty of Engineering, The University of Tokushima, No.19, 105-111, 1974.
7.	原田尚文, 島田良作 and Takeomi Tamesada : 三相マルチバイブレータ(その2), Bulletin of Faculty of Engineering, The University of Tokushima, Vol.18, No.18, 151-159, 1973. (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1520853835154277504 (CiNii: 1520853835154277504)
8.	森村和由, 原田尚文, 島田良作 and Takeomi Tamesada : 学習制御についての一研究, Bulletin of Faculty of Engineering, The University of Tokushima, Vol.18, No.18, 161-168, 1973. (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1520572360126873600 (CiNii: 1520572360126873600)
9.	戸倉信之, 原田尚文, 島田良作 and Takeomi Tamesada : 薄膜磁性線三値記憶装置, Bulletin of Faculty of Engineering, The University of Tokushima, No.17, 17-20, 1972.
10.	原田尚文, 島田良作 and Takeomi Tamesada : 三相マルチバイブレータ(その1), Bulletin of Faculty of Engineering, The University of Tokushima, No.17, 21-32, 1972.
11.	根来重泰, 原田尚文, 島田良作 and Takeomi Tamesada : シミュレーション手法によるサンプル値制御系の最適調整について, Bulletin of Faculty of Engineering, The University of Tokushima, No.16, 117-122, 1971.
12.	岸本明, 原田尚文, 島田良作 and Takeomi Tamesada : 置換と束演算を用いた三値論理回路の設計, Bulletin of Faculty of Engineering, The University of Tokushima, No.16, 105-115, 1971.
13.	Takeomi Tamesada, 島田良作 and 原田尚文 : トランジスタ双安定MVのトリガに関する研究, Bulletin of Faculty of Engineering, The University of Tokushima, Vol.13, No.13, 57-70, 1968. (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1520853835125994496 (CiNii: 1520853835125994496)
14.	浜口幸彦, 原田尚文, 島田良作 and Takeomi Tamesada : Analysis of the Short-wave Recording on a Magnetic Tape, Bulletin of Faculty of Engineering, The University of Tokushima, Vol.12, No.12, 101-107, 1967. (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1520009410224214144 (CiNii: 1520009410224214144)
15.	岩佐恭一, 繖晃一郎, 原田尚文, 島田良作 and Takeomi Tamesada : Investigation on Three Valued Logic Circuits, Bulletin of Faculty of Engineering, The University of Tokushima, Vol.12, No.12, 95-99, 1967. (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1520572360113815808 (CiNii: 1520572360113815808)
16.	Takeomi Tamesada, 島田良作 and 原田尚文 : トランジスタ双安定MVのトリガに関する研究, Bulletin of Faculty of Engineering, The University of Tokushima, No.11, 79-92, 1966.

Academic Letter:

1.	Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Sequential Redundancy Removal Using Test Generation and Multiple Strongly Unreachable States, IEICE Transactions on Information and Systems, Vol.E85-D, No.10, 1605-1608, 2002. (Summary) A procedure to remove redundancies in sequential circuits is proposed using strongly unreachable states, which are the states with no incoming transitions. Test generation is used to find undetectable faults related to two or more strongly unreachable states. Experimental results show the new procedure can find more redundancies of sequential circuits. (Keyword) synthesis for testability / redundancy removal / sequential circuit / undetectable faults / unreachable states (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1573950402004399616 ● Summary page in Scopus @ Elsevier: 2-s2.0-0036826120 (CiNii: 1573950402004399616, Elsevier: Scopus)
2.	Masaki Hashizume, Tasaka Eiji, Takeomi Tamesada, Kayahara Toshihiro and Yamazoe Tomohisa : A Practical Functional Test Using Flowchart for Production Testing of Microprocessor Based Sequence Controllers, Transactions of the IEICE of Japan, Vol.E76-D, No.7, 837-841, 1993.
3.	Masaki Hashizume, Takeomi Tamesada and 山田和浩 : TTL組合せ論理回路の故障検出のための電源電流標準パターン候補導出法, The Transactions of the Institute of Electronics, Information and Communication Engineers D-I, Vol.J73-D-I, No.7, 637-640, 1990.
4.	Masaki Hashizume, 山本博資, Takeomi Tamesada and 高橋一磨 : 樹枝状に分割可能な組合せ回路の故障検出入力生成法, Transactions of Information Processing Society of Japan, Vol.29, No.6, 627-630, 1988.
5.	Takeomi Tamesada : 最小冗長P進表現を用いた高速減算, The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.J70-D, No.12, 2800-2801, 1987.
6.	Takeomi Tamesada and Masahiro Ichimiya : 無安定マルチバイブレータの起動回路とその効果, The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.J68-D, No.3, 408-409, 1985.
7.	Takeomi Tamesada and Masahiro Ichimiya : TTL-NAND無安定マルチバイブレータの出力電圧波形の改善, The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.J67-D, No.7, 819-820, 1984.
8.	Takeomi Tamesada : TTL-NANDゲートを用いた出力波形と始動性の良好な無安定マルチバイブレータ, The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.J66-D, No.5, 617-618, 1983.
9.	Takeomi Tamesada : 3個のTTL-NANDゲートを用いた三相無安定マルチバイブレータ, The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.J66-D, No.2, 226-227, 1983.
10.	Takeomi Tamesada : TTL-NANDゲートを用いた単一発振モード無安定マルチバイブレータ, The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.J65-D, No.4, 486-487, 1982.

Proceeding of International Conference:

1.	Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Open Lead Detection Based on Supply Current of CMOS Logic Circuits by AC Voltage Signal Application, Proceedings of ICEP2006, 147-152, Tokyo, Apr. 2006. (Keyword) Lead Open / CMOS / PCB Test
2.	Tomohiko Nagashima, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Test Time Reduction Method for Scan Design with Clock-Control DFT, Proc. RISP International Workshop on Nonlinear Circuit and Signal Processing, 441-444, Honolulu, Mar. 2006. (Summary) This paper presents a test generation method for sequential circuits. Our method utilizes the test vectors obtained for full scan design. In this parer, we combined two design-for- testability(DFT) method:one is transparent scan, the other is clock-control DFT. The simulation results for some benchmark circuits are shown.
3.	Masaki Hashizume, Tomomi Nishida, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Yukiya Miura : Current Testable Design of Resistor String DACs, The IEEE International Workshop on Electronic Design, Test and Applications, 197-200, Kuala Lumpur, Malaysia, Jan. 2006. (Summary) In this paper, supply current testability is examined experimentally for opens and shorts in a general 3 bit resistor string digital/analog converter (DAC). The results show that all of the shorts and the opens are detected by supply current testing, while opens of the MOS switches are not detected. A DFT method for resistor string DACs is proposed in this paper to detect the opens by supply current testing. Also, testability of a resistor string DAC designed with the DFT method is examined. It is shown that all of the targeted shorts and opens in the testable designed DAC are detected by supply current testing. (Link to Publication Site) ● Publication site (DOI): 10.1109/DELTA.2006.28 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/DELTA.2006.28 (DOI: 10.1109/DELTA.2006.28)
4.	Tomohiko Nagashima, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Test Generation for Scan Circuits Using Random Selection of the Operations of Scan Flip-flops, 6th Workshop on RTL and High Level Testing (WRTLT05), 79-83, Harbin, China, Jul. 2005. (Summary) This paper presents a test generation method for scan circuits. In the proposed method control signals of scan flip-flops are treated as the same as the primary inputs. Our method utilizes the test vectors obtained for full scan design and apply the vectors repeatedly in the given order to achieve low test data volume. For each test vector, the operation of scan flip-flops is selected from one of the following: normal, scan and freeze operation. The simulation results for some benchmark circuits are shown.
5.	Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Electric Field for Detecting Open Leads in CMOS Logic Circuits by Supply Current Testing, Proc. of IEEE International Symposium on Circuits and Systems, 2995-2998, Kobe, May 2005. (Summary) Open leads are one type of defect occurring frequently when logic circuits are implemented on printed circuit boards (PCBs) with ICs. A powerful supply current test method has been proposed for detecting an open lead in a CMOS logic circuit. The method is based on the supply current of a circuit under test which flows when a time-varying electric field is supplied from the outside of the circuit. The paper proposes a time-varying electric field which enables us to detect open leads in a CMOS logic circuit with an inexpensive test setup. (Link to Publication Site) ● Publication site (DOI): 10.1109/ISCAS.2005.1465257 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/ISCAS.2005.1465257 (DOI: 10.1109/ISCAS.2005.1465257)
6.	Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Vectorless Open Pin Detection Method for CMOS Logic Circuits, Proc. of International Conference on Electronics Packaging, 391-396, Tokyo, Apr. 2005.
7.	Takashi Sakaguchi, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Tetsuo Tada, Takeshi Koyama, Yasuhiro Miyagawa, Seiji Tanaka and Toshihiro Kayahara : Fail-Safe Evaluation Method for Boiler Control Circuits by Circuit Simulation, Proc. RISP International Workshop on Nonlinear Circuit and Signal Processing, 395-398, Honolulu, Mar. 2005. (Summary) The fail-safe property is strongly requested for boiler control circuits. A boiler control circuit is a microprocessor based circuit and the operation is specified by a control program. Until now, there have been no methods to evaluate fail-safe property of boiler control circuits. In this paper, a fail safe evaluation method is proposed for boiler control circuits. The method utilizes a circuit simulator to check it. It is checked by the method whether it is stopped supplying fuel to a boiler when a fault occurs inside the boiler control circuit in operation. In order to evaluate the feasibility of fail-safe evaluation by the method, fail-safe property in a general boiler control circuit is examined by using the method. The result shows that fail-safe property will be checked by using the evaluation method.
8.	Seiichi Nishimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Electrical Detection of Pin Shorts by Supply Current of PIC, Proc. RISP International Workshop on Nonlinear Circuit and Signal Processing, 171-174, Honolulu, Mar. 2005. (Summary) In this paper, we propose a new test method for detecting pin shorts of a PIC. This test method is based on supply current of the PIC. Targeted faults of this test method are input/output pins of the PIC. The property is used for detecting the shorts in the test method that input/output mode of each of the pins is programmable. Each of the fault is excited by executing a test program so that supply current change can appear. We checked the feasibility of the test method by some experiments. The results shows that the shorts will be detected by the test method.
9.	Masahiro Ichimiya, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Test Equipment for CMOS Lead Open Detection Based on Supply Current under AC Electric Field Application, Proc. of the ECWC 10 Conference, P03-5-1-P03-5-5, Anaheim, Feb. 2005. (Summary) Open leads have often occurred in logic circuits implemented on printed circuit boards with the state-of-art technology. We proposed an electrical test method to detect them with high fault coverage. The test method is based on supply current change of a circuit under test that is caused with AC electric field supplied from the outside of the circuit. In this paper, we propose a test equipment for the test method. A voltage signal that is obtained by mixing a rectangle waveform signal and a sine waveform one is supplied between electrodes to generate the electric field. Amplitude of the signal continues to increase in proportion to time during a specified time. When supply current change that is larger than a threshold value appears, it stops increasing the amplitude and it is concluded that open leads occur in the circuit. If the supply current change does not appear within the specified time, it is concluded that no open leads occur in the circuit. In this paper, it is shown experimentally that an open lead at a CPLD of PLCC package is detected with the test equipment.
10.	Masaki Hashizume, Daisuke Yoneda, Hiroyuki Yotsuyanagi, Tetsuo Tada, Takeshi Koyama, Ikuro Morita and Takeomi Tamesada : IDDQ Test Method Based on Wavelet Transformation for Noisy Current Measurement Environment, Proc. of 13th Asian Test Symposium, 112-117, Kenting, Taiwan, Nov. 2004. (Summary) An IDDQ test method is proposed in this paper, which is applicable even if supply current measurement is impaired by noise. Wavelet transformation is used for noise elimination in the test method. In this paper, it is shown by some experiments that bridging faults will be detected by using the proposed test method. Since expert knowledge on filter design is not needed in noise elimination of the IDDQ test method, it is expected that the test method will be used in many IDDQ tests. (Link to Publication Site) ● Publication site (DOI): 10.1109/ATS.2004.50 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/ATS.2004.50 (DOI: 10.1109/ATS.2004.50)
11.	Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Test Circuit for CMOS Lead Open Detection by Supply Current Testing under AC Electric Field Application, Proc. of the 2004 47-th Midwest Symposium on Circuits and Systems, I-557-I-560, Hiroshima, Jul. 2004. (Summary) A test circuit is proposed for detecting lead opens of CMOS ICs by measuring the supply current of a CMOS circuit made of the ICs which flows when AC electric field is applied from the outside. A signal of a sine waveform is provided to the test circuit. In the test circuit, the amplitude of the signal increases in proportion to time during a prespecified time. The amplified signal is provided to electrodes for AC electric field to be supplied to a circuit under test. When supply current change which is larger than a threshold value appears, it stops increasing the amplitude and the test circuit concludes that a lead open occurs in the circuit. If the elevated supply current change does not appear within the specified time, the test circuit concludes that the circuit is fault-free. It is shown by our experiments that lead opens in a CMOS IC is detected with the test circuit. (Link to Publication Site) ● Publication site (DOI): 10.1109/MWSCAS.2004.1354051 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/MWSCAS.2004.1354051 (DOI: 10.1109/MWSCAS.2004.1354051)
12.	Takagi Masao, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Tsukimoto Isao and Takeomi Tamesada : AC Electric Field for Detecting Pin Opens by Supply Current of CMOS ICs, Proc. of International Conference on Electronics Packaging, 217-222, Tokyo, Apr. 2004.
13.	Daisuke Ezaki, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : A Power Supply Circuit Recycling Charge in Adiabatic Dynamic CMOS Logic Circuits, Proc. of the second IEEE International Workshop on Electronic Design, Test, and Applications, 306-311, Perth, Australia, Jan. 2004. (Summary) In this paper, a power supply circuit is proposed for adiabatic dynamic CMOS logic circuit. Charge in load capacitors of gates can be recycled by using this power supply circuit. It leads to lower power consumption than without recycling. In this paper, source voltage of adiabatic dynamic CMOS inverter chain circuits is supplied with the circuit to evaluate the usefulness of the circuit. The results show that the circuits can work with smaller power consumption than without recycling. (Link to Publication Site) ● Publication site (DOI): 10.1109/DELTA.2004.10022 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/DELTA.2004.10022 (DOI: 10.1109/DELTA.2004.10022)
14.	Isao Tsukimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Practical Fault Coverage of Supply Current Tests for Bipolar ICs, Proc. of the second IEEE International Workshop on Electronic Design, Test, and Applications, 189-194, Perth, Australia, Jan. 2004. (Summary) Bipolar logic circuits are indispensable for implementing high-speed logic circuits. Since quiescent supply current flows into the circuits without faults, they can not be tested by a conventional IDDQ test method. We proposed a quiescent supply current test method which is applicable for the bipolar circuit tests, and examined the testability of open faults under an ideal assumption that there are not any process variations. Actually, there are some variations in the quiescent supply current of each gate in implemented logic circuits. Thus, It is necessary to examine the practical testability of the test method before applying to production tests of bipolar logic ICs. In this paper, the practical testability obtained under an assumption that there are some unit-to-unit variations of supply current among gates is examined for ISCAS-85 benchmark circuits. The experimental results show that larger fault coverage can be obtained with a smaller number of test input vectors by our supply current test method than the functional test one based on stuck-at fault models. (Link to Publication Site) ● Publication site (DOI): 10.1109/DELTA.2004.10035 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/DELTA.2004.10035 (DOI: 10.1109/DELTA.2004.10035)
15.	Masaki Hashizume, Tetsuo Akita, Hiroyuki Yotsuyanagi and Takeomi Tamesada : CMOS Open Fault Detection by Appearance Time of Switching Supply Current, Proc. of the second IEEE International Workshop on Electronic Design, Test, and Applications, 183-188, Perth, Australia, Jan. 2004. (Summary) In this paper, a new dynamic supply current test method is proposed for detecting open defects on signal lines in CMOS logic circuits. The method is based on the appearance time of dynamic supply current that flows when a test input vector is provided to a circuit under test. Also, we introduce our designed sensor circuit of the appearance time. Feasibility of tests based on the test method is examined by some experiments. The experimental results show that open defects on signal lines in CMOS logic circuits will be detected by the test method. (Link to Publication Site) ● Publication site (DOI): 10.1109/DELTA.2004.10036 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/DELTA.2004.10036 (DOI: 10.1109/DELTA.2004.10036)
16.	Masaki Hashizume, Teppei Takeda, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura and Kozo Kinoshita : A BIST Circuit for IDDQ Tests, Proc. of Twelfth Asian Test Symposium, 390-395, Xi'an, Nov. 2003. (Summary) In this paper, an IDDQ test time reduction method is proposed which is suitable for BIST approaches. Also, a BIST circuit for IDDQ tests, based on the method, is proposed. The layout of a CMOS logic circuit having the BIST circuit is designed and the performance is evaluated by SPICE simulation. The results show us that IDDQ test time can be reduced by using this test circuit. (Link to Publication Site) ● Publication site (DOI): 10.1109/ATS.2003.1250843 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/ATS.2003.1250843 (DOI: 10.1109/ATS.2003.1250843)
17.	Masaki Hashizume, Makoto Kawajiri, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Testability of Supply Current Test in an AGC Circuit, Proc. of 2003 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.2, 836-839, Kang-Won Do, Korea, Jul. 2003. (Summary) In this paper, it is examined whether AGC circuits can be tested by measuring supply current of the circuits. A general AGC circuit is designed and a fault, which is one of shorts, opens and parametric faults, is inserted to the circuit. Supply current waveforms of faulty circuits are derived by circuit simulation and compared to the one of the fault-free circuit. The experimental results show that many faults in the AGC circuit can be detected by measuring the supply current.
18.	Takagi Masao, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Testability of Pin Open in Small Outline Package ICs by Supply Current Test, Proc. of the 2003 International Technical Conference on Circuits/Systems, Computers and Communications, 832-835, Kang-Won Do, Korea, Jul. 2003.
19.	Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Electric Field Application Method Effective for Pin Open Detection Based on Supply Current in CMOS Logic Circuits, Proc. of International Conference on Electronics Packaging, 75-80, Tokyo, Apr. 2003.
20.	Masaki Hashizume, Teruyoshi Matsushima, Takashi Shimamoto, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Akio Sakamoto : Simplification of Incompletely Specified Machine Based on Genetic Algorithm Implementing Dormant Mechanism, 3rd Workshop on RTL and High Level Testing (WRTLT02), 74-78, Guam, USA, Nov. 2002.
21.	Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Test Time Reduction for IDDQ Testing by Arranging Test Vectors, Proc. of Eleventh Asian Test Symposium, 423-428, Guam, USA, Nov. 2002. (Summary) In this paper, test time reduction for IDDQ testing is discussed. Although IDDQ testing is known to be effective in detecting faults in CMOS circuits, the test time of IDDQ testing is larger than that of logic testing. It is shown that the test time of IDDQ test mostly depends on the switching current. To reduce the test time of IDDQ testing, a procedure to arrange test vectors such that the switching current quickly disappears is proposed for combinational circuits. The procedure utilizes a unit delay model to estimate the time of the last transition of logic values from low to high in a circuit. Experimental results for benchmark circuits show the effectiveness of the procedure. (Link to Publication Site) ● Publication site (DOI): 10.1109/ATS.2002.1181748 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/ATS.2002.1181748 (DOI: 10.1109/ATS.2002.1181748)
22.	Masaki Hashizume, Nobuyuki Inou, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Oscillation Frequency Estimation for Detecting Feedback Bridging Faults, Proc. of 2002International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 1980-1983, Phuket, Thailand, Jul. 2002. (Summary) When a feedback bridging fault is activated in a circuit, logical oscillation may occur at a signal line. If the oscillation appears, the fault may not be detected by logic testing. In order to detect such bridging faults, output logic values of the circuit should be measured at higher frequency than frequency of the logical oscillation. In this paper, a method for estimating the maximum frequency of logical oscillation is proposed to detect such bridging faults in a circuit by logic testing. Also, it is shown by some experiments that such bridging faults can be detected by measuring output logic values at the frequency obtained by the method.
23.	Isao Tsukimoto, Masaki Hashizume, Yukiko Mushiaki, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Testability of Current Testing for Open Faults Undetected by Functional Testing in TTL Combinational Circuits, Proc. of 2002International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 1972-1975, Phuket, Thailand, Jul. 2002. (Summary) A new test approach based on a supply current test method is proposed for testing open faults in bipolar logic circuits. In the approach, only the open faults are detected by the supply current test method, which are difficult to be detected by functional test methods. The effectiveness of the approach is examined experimentally on open fault detection in TTL combinational circuits. The results shows that higher fault coverage can be established by applying a small number of test input vectors of the supply current test method after test vectors of functional test methods based on stuck-at models.
24.	Masaki Hashizume, Tasaka Eiji, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Toshihiro Kayahara : Power-off Vectorless Test Method for Pin Opens in CMOS Logic Circuits, Proc. of International Conference on Electronics Packaging, 416-420, Tokyo, Apr. 2002. (Summary) A new test method is proposed in this paper for detecting pin opens in CMOS logic circuits fabricated on printed circuit boards, which are generated by missing solder and so on. Our test method is based on the current which flows through a protection circuit connecting to each pin by supplying a voltage source between the targeted pin and VSS line of a circuit under test. The test method does not require test input generation. When a pin open occurs, smaller current will be supplied from the voltage source than in the case of the fault-free circuit. Our test method uses the property for detecting pin opens. In this paper, the feasibility of the test method is evaluated by some experiments.
25.	Masaki Hashizume, Masashi Sato, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Power Supply Circuit for High Speed Operation of Adiabatic Dynamic CMOS Logic Circuits, Proc. of the IEEE International Workshop on Electronic Design, Test, and Applications, 459-461, Christchurch, New Zealand, Jan. 2002. (Summary) In this paper, a power supply circuit is proposed for adiabatic dynamic CMOS logic circuits proposed by K. Takahashi et. al. With this supply circuit, the circuits can work at higher speed. In this paper, source voltage of adiabatic dynamic CMOS inverter gates is supplied by the circuit and the power consumption is examined. The results show that the gates can work with smaller power dissipation than conventional static CMOS circuits (Link to Publication Site) ● Publication site (DOI): 10.1109/DELTA.2002.994673 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/DELTA.2002.994673 (DOI: 10.1109/DELTA.2002.994673)
26.	Hiroyuki Yotsuyanagi, Masaki Hashizume, Taisuke Iwakiri, Masahiro Ichimiya and Takeomi Tamesada : Random Pattern Testability of the Open Defect Detection Method using Application of Time-variable Electric Field, Proc. of the IEEE International Workshop on Electronic Design, Test, and Applications, 387-391, Christchurch, New Zealand, Jan. 2002. (Summary) In this paper, random pattern testability of the open defect detection method is discussed. In the test method, time-variable electric field is applied from the outside of ICs so as to vary the voltage at floating nodes caused by a defect. To detect opens the excessive supply current caused by the applied electric field is measured. The test pattern requirements for detecting opens are shown. The fault coverage for open defects is calculated for benchmark circuits. The experimental results shows random pattern can be effectively utilized for the test method even if it cannot attain high fault coverage for stuck-at-faults (Link to Publication Site) ● Publication site (DOI): 10.1109/DELTA.2002.994656 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/DELTA.2002.994656 (DOI: 10.1109/DELTA.2002.994656)
27.	Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : CMOS Open Defect Detection Based on Supply Current in Time-variable Electric Field and Supply Voltage Application, Proc. of Tenth Asian Test Symposium, 117-122, Kyoto, Nov. 2001. (Summary) In this paper, a new test method is proposed for detecting open defects in CMOS ICs. The method is based on supply current of ICs generated by applying time-variable supply voltage and electric field from the outside of the ICs. The feasibility of the test is examined by some experiments. The empirical results show that, by using the method, open defects in CMOS ICs can be detected. Also, the test input vectors for the test method are proposed and it is shown that they can be generated more easily than functional test methods based on stuck-at fault models (Link to Publication Site) ● Publication site (DOI): 10.1109/ATS.2001.990269 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/ATS.2001.990269 (DOI: 10.1109/ATS.2001.990269)
28.	Hiroyuki Yotsuyanagi, Shinsuke Hata, Masaki Hashizume and Takeomi Tamesada : Sequential Redundancy Removal Using Test Generation and Multiple Unreachable States, Proc. of Tenth Asian Test Symposium, 23-28, Kyoto, Nov. 2001. (Summary) In this paper, a procedure to reduce sequential circuits by removing undetectable faults in sequential circuits is proposed. To identify whether an undetectable fault is removable or not, strongly unreachable states, which are the states with no incoming transitions, are utilized. It is proved that part of undetectable faults related to strongly unreachable states can be removed from a circuit. Test generation method is used to find undetectable faults related to two or more strongly, unreachable states. Experimental results for ISCAS benchmark circuits are shown (Link to Publication Site) ● Publication site (DOI): 10.1109/ATS.2001.990253 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/ATS.2001.990253 (DOI: 10.1109/ATS.2001.990253)
29.	Hiroyuki Yotsuyanagi, Masaki Hashizume, Taisuke Iwakiri, Masahiro Ichimiya and Takeomi Tamesada : Test Pattern for Supply Current Test of Open Defects by Applying Time-variable Electric Field, Proc. of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 287-295, San Francisco, Oct. 2001. (Summary) Test input vectors for a supply current test method are discussed which is used for detecting open defects in CMOS ICs. In the test method, time-variable electric field is applied from the outside of ICs so as to vary the voltage at a floating node. To generate excessive supply current by the induced voltage change at the floating node, test pattern must be provided so that a conducting path from VDD to GND can be generated in the faulty circuit. In this paper, the requirements are denoted to be satisfied as a test input vector of the test method. Also, it is shown that test pattern of functional tests based on stuck-at fault models can be used for the open defect detection method. Furthermore, the experimental results in this paper promise that high fault coverage can be achieved by applying the subset of the stuck-at test pattern to the detection of open defects (Link to Publication Site) ● Publication site (DOI): 10.1109/DFTVS.2001.966781 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-0035202383 (DOI: 10.1109/DFTVS.2001.966781, Elsevier: Scopus)
30.	Teppei Takeda, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : A High Speed IDDQ Sensor Circuit, Proc. of 2001 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.2, 438-441, Tokushima, Jul. 2001.
31.	Masaki Hashizume, Eiji Tasaka, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Toshihiro Kayahara : Fault Simulator for Test Program Generation in Supply Current Tests of Microprocessor Based Boiler Control Circuits, Proc. of 2001 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 446-449, Tokushima, Jul. 2001.
32.	Akihiro Tsuji, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Pin Open Detection Method Based on Supply Current in Time-variable Magnetic Field, Proc. of 2001 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 438-441, Tokushima, Jul. 2001.
33.	Masaki Hashizume, Akihiro Tsuji, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Supply Current Test for Pin Opens in CMOS Logic Circuits, Proc. of International Conference on Electronics Packaging, 363-368, Tokyo, Apr. 2001.
34.	Masaki Hashizume, Masahiro Ichimiya, Hiroshi Hoshika, Hiroyuki Yotsuyanagi and Takeomi Tamesada : CMOS Open Defect Detection by Supply Current Test, Proc. of Design, Automation and Test in Europe Conference 2001, 509-513, Munich, Mar. 2001. (Summary) In this paper, a new test method is proposed for detecting open defects in CMOS ICs. The method is based on supply current of ICs generated by applying time-variable electric field from the outside of the ICs. The feasibility of the test is examined by some experiments. The empirical results promised that, by using the method, open defects in CMOS ICs can be detected by measuring supply current which flows when time-variable electric field is applied (Link to Publication Site) ● Publication site (DOI): 10.1109/DATE.2001.915071 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/DATE.2001.915071 (DOI: 10.1109/DATE.2001.915071)
35.	Masaki Hashizume, Hiroyuki Yotsuyanagi, Masahiro Ichimiya, Takeomi Tamesada and Masashi Takeda : High Speed IDDQ Test and Its Testability for Process Variation, IEEE Asian Test Symposium, 344-349, TAIPEI TAIWAN, Dec. 2000. (Summary) A new high speed IDDQ test method is proposed. It is based on charge current for load capacitances of gates whose output logic values are changed from L to H by test input vector application. In this paper, the testability of the test method is examined for some process variations generated in CMOS IC production (Link to Publication Site) ● Publication site (DOI): 10.1109/ATS.2000.893647 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-0034497760 (DOI: 10.1109/ATS.2000.893647, Elsevier: Scopus)
36.	Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Masashi Takeda : Testability Analysis of IDDQ Testing with Large Threshold Value, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 367-375, Yamanashi Japan, Oct. 2000. (Summary) By using large threshold value in IDDQ tests, test time can be shortened. However, the fault coverage of the IDDQ tests will be affected by process variation. In this paper, effects on fault coverage of IDDQ tests generated by variations of zero biased threshold voltage of each MOS transistor in a circuit under test are examined with a circuit simulator. The result suggests us that IDDQ testing with large threshold value is applicable to production tests of CMOS ICs (Link to Publication Site) ● Publication site (DOI): 10.1109/DFTVS.2000.887177 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-0034517501 (DOI: 10.1109/DFTVS.2000.887177, Elsevier: Scopus)
37.	Masashi Sato, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Power Supply Circuits with Small Size for Adiabatic Dynamic CMOS Logic Circuits, Proc. of 2000 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 179-182, Busan, Jul. 2000.
38.	Yukiko Mushiaki, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Practical Fault Coverage of Supply Current Testing for Open Fault in TTL Combinational Circuits, Proc. of 2000 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 383-386, Busan, Jul. 2000.
39.	Takahiro Ohnishi, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : A Test Input Sequence for Test Time Reduction of IDDQ Testing, Proc. of 2000 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 367-370, Busan, Jul. 2000. (Summary) It is shown that IDDQ testing is very useful for shipping fault-free CMOS ICs. However, test time of IDDQ testing is extremely larger than one of logic testing. In this paper, a new test input sequence generation methodology is proposed to reduce the test time of lDDQ testing. At first, it is shown that IDDQ test time will be denominated by charge supply current for load capacitance of gates whose output logic values are changed by test input vector application and the charge current depends on input sequence of test vectors. After that, a test input sequence generation methodology is proposed, The feasibility is checked by some experiments.
40.	Hiroshi Hoshika, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : IDDQ Testable Design of Static CMOS PLAs with Low Power Consumption, Proc. of 2000 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 351-354, Busan, Jul. 2000.
41.	Sou Yamamoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Oscillation Frequency Estimation of Feedback Bridging Faults for Test Circuit Design, Proc. of 2000 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 343-346, Busan, Jul. 2000.
42.	Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Synthesis for Testability by Adding Transitions of Undefined States to State Transition Tables, Proc. of 2000 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 355-358, Busan, Jul. 2000. (Summary) In this paper we propose procedures to enhance testability by modifying state transition tables. In these procedures, transitions about undefined states, which are not described in state transition tables but exist in a synthesized gate level circuit, are added to a state transition table. Experimental results for MCNC benchmarks are shown.
43.	Masaki Hashizume, Hiroshi Hoshika, Hiroyuki Yotsuyanagi and Takeomi Tamesada : IDDQ Testable Design of Static CMOS PLAs, IEEE International Workshop on Defect Based Testing, 70-75, Montreal, Apr. 2000. (Summary) A new IDDQ testable design method is proposed for static CMOS PLA circuits. A testable PLA circuit of NOR-NOR type is designed by using this method. It is shown that all bridging faults in NOR planes of the testable designed PLA circuit can be detected by IDDQ testing with 4 kinds of test input vectors. The test input vectors are independent of the logical functions to be realized in the PLA circuit. PLA circuits are designed by using this method so that quiescent supply current generated when they are tested can be zero. Thus, high resolution of IDDQ tests for the PLA circuits can be obtained by using this testable design method. (Link to Publication Site) ● Publication site (DOI): 10.1109/DBT.2000.843693 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/DBT.2000.843693 (DOI: 10.1109/DBT.2000.843693)
44.	Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Identification of Feedback Bridging Faults with Oscillation, IEEE Eighth Asian Test Symposium, 25-30, Shanghai, Nov. 1999. (Summary) When a feedback bridging fault occurs in a combinational circuit and it is activated, logical oscillation may be generated in the circuit. In this paper, the necessary conditions are presented for feedback bridging faults to generate logical oscillation. Also, a method is proposed to identify such faults in feedback bridging ones. It is based on piecewise-linearized models obtained from input/output characteristics of logic gates and does not require circuit simulation of large size of circuits to identify them. In the experiments for evaluating the method, all of the feedback bridging faults to generate logical oscillation are identified by using the method (Link to Publication Site) ● Publication site (DOI): 10.1109/ATS.1999.810725 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/ATS.1999.810725 (DOI: 10.1109/ATS.1999.810725)
45.	Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Eiji Tasaka and Toshihiro Kayahara : Supply Current testing for Bridging Faults in Microprocessor Based Sequence Control Circuits, Proc. of Electronic Circuits World Convention 8, 31-37, Tokyo, Sep. 1999.
46.	Masaki Hashizume, Masashi Sato, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Power Supply Circuit for Adiabatic Dynamic CMOS Logic Circuits, Proc. of 1999 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 162-165, Niigata, Jul. 1999.
47.	Teruyoshi Matsushima, Masaki Hashizume, Takeomi Tamesada, Takashi Shimamoto and Akio Sakamoto : State Reduction of Incompletely Specified Machines based on Genetic Approach, The 1999 International Technical Conference on Circuits/Systems, Computers and Communications, 888-891, Sado Island, Niigata, Jul. 1999.
48.	Masaki Hashizume, Yukiya Miura, Masahiro Ichimiya, Takeomi Tamesada and Kozo Kinoshita : A High Speed IDDQ Sensor for Low Voltage ICs, IEEE Seventh Asian Test Symposium, 327-331, Singapore, Dec. 1998.
49.	Toshimasa Kuchii, Masaki Hashizume and Takeomi Tamesada : Test Input Generation for Supply Current Testing of Bridging Faults in Bipolar Combinational Logic Circuits, Proc. of the IEEE International Workshop on IDDQ Testing, 14-18, San Jose, Nov. 1998.
50.	Masaki Hashizume, Takeomi Tamesada, Takeshi Koyama and Goor de A.J.van : CMOS SRAM Functional Test with Quiescent Write Supply Current, Proc. of the IEEE International Workshop on IDDQ Testing, 4-8, San Jose, Nov. 1998.
51.	Toshihiro Sezaki, Masaki Hashizume, Takeomi Tamesada and Ikuro Morita : Supply Current Measurement Circuit for Bridging Fault Detection in Microprocessor Based Circuit, Proceedings of ITC-CSCC'97 International Technical Conference on Circuits Systems, Computers and Comunications, 935-938, Okinawa, Jul. 1997.
52.	Masaki Hashizume, Takeomi Tamesada, Takashi Shimamoto and Akio Sakamoto : Genetic Approaches to State Reduction of Incompletely Specified Machines, The 1997 International Technical Conference on Circuits/Systems, Computers and Communications, 463-466, Okinawa, Jul. 1997.

Proceeding of Domestic Conference:

1.	Seiichi Nishimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Supply Current Test Program for Pin Short Detection in Z80, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 383, Sep. 2005.
2.	Tatsuya Shimizu, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Power Consumption of a Time Varying Power Supplied Dynamic CMOS Adder, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 132, Sep. 2005.
3.	Hiroshi Ohmura, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Testability Evaluation of Open Faults in Consideration of the Voltage of the Adjacent Lines, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 130, Sep. 2005.
4.	Katsumi Inoue, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Design of Scan Tree Configuration of Sequential Circuits using CAD, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 129, Sep. 2005.
5.	Takashi Sakaguchi, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Yukiya Miura : Torelance of a Built-in IDDQ Test Circuit for Process Variation, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 120, Sep. 2005.
6.	Takeshi Iihara, Masaki Hashizume, Tetsuo Tada, Takeshi Koyama, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Testabillity Analysis System of IDDQ Testing Based on Wavelet Transformation, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 119, Sep. 2005.
7.	Masao Takagi, Masaki Hashizume, Isao Tukimoto, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Effects on Testability of Logic Value Outputting to Faulty Line in Lead Open Detection by Supply Current Testing, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 118, Sep. 2005.
8.	Tatsuya Shimizu, Daisuke Ezaki, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Power Consumption in a Time Varying Power Supplied Dynamic CMOS Timer Circuit, Proceedings of IEICE Society Conference, 92, Sep. 2005.
9.	Seiichi Nishimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : At-Speed Test for Pin Shorts in Z80 by Supply Current Testing, Proceedings of IEICE Society Conference, 83, Sep. 2005.
10.	Takashi Sakaguchi, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Tetsuo Tada, Takeshi Koyama, Yasuhiro Miyagawa, Seiji Tanaka and Toshihiro Kayahara : Fail-safe Evaluation System for Boiler Control Circuits, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 117, Sep. 2004.
11.	Seiichi Nishimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : A Supply Current Test Method for Pin Shorts in PIC ICs, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 116, Sep. 2004.
12.	Tetsuo Akita, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Mitsuo Shimotani : Detection of Open Fault Realized by Transmission Gate with IDDT Disappearance Time Detection Circuit, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 115, Sep. 2004.
13.	Daisuke Ezaki, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Operating Speed of Dynamic CMOS Logic Circuit Driven by Supply Voltage of Rectangle Waveform, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 114, Sep. 2004.
14.	Shintaro Nakayashiki, Masahiro Ichimiya, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : IDDQ Test Circuit with a High Speed External Current Sensor, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 112, Sep. 2004.
15.	Tomomi Nishida, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Yukiya Miura : Testability of Supply Current Testing for DA Converters of Resistor String Type, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 111, Sep. 2004.
16.	Masao Takagi, Masaki Hashizume, H. Ishii, Isao Tukimoto, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Pin Open Detection in CMOS TQFP ICs of Low Supply Voltage by Measuring Supply Current under AC Electric Field, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 110, Sep. 2004.
17.	Isao Tsukimoto, Masao Takagi, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Deterministic Test Vector Generation of Supply Current Test for Open Faults Undetected by Functional Tests in TTL ICs, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 109, Sep. 2004.
18.	Makoto Kawajiri, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Spice Model for Deriving Fault Model of Charge Coupled Devices, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 108, Sep. 2004.
19.	Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Constructing Scan Trees based on a Circuit Structure, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 156, Oct. 2003.
20.	Hirokazu Sano, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Test Generation for Sequential Circuits using Structure Based Partitioning, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 155, Oct. 2003.
21.	Daisuke Ezaki, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : A Power Supply Circuit for Dynamic CMOS Logic Circuits, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 139, Oct. 2003.
22.	Kenji Kaishita, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Low Power Dynamic CMOS Logic Circuits, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 138, Oct. 2003.
23.	Tetsuo Akita, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Mitsuo Shimotani : IDDT Test Circuit for Detecting Open Faults in CMOS ICs, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 137, Oct. 2003.
24.	Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Tetsuo Tada, Takeshi Koyama, Yasuhiro Miyagawa, Seiji Tanaka and Toshihiro Kayahara : Fail-safe Analysis for a Breaker Valve Circuit in a Boiler Control Circuit, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 136, Oct. 2003.
25.	Masao Takagi, Isao Tukimoto, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Pin Open Detection for CMOS Logic ICs of TQFP Package by Measuring Supply Current under AC Electric Field, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 134, Oct. 2003.
26.	Daisuke Yoneda, Masaki Hashizume, Tetsuo Tada, Takeshi Koyama, Hiroyuki Yotsuyanagi and Takeomi Tamesada : IDDQ Testing with Wavelet Transformation Technique, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 133, Oct. 2003.
27.	Isao Tsukimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi, Masao Takagi and Takeomi Tamesada : Practical Fault Coverage of Supply Current Tests for TTL ICs, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 132, Oct. 2003.
28.	Makoto Kawajiri, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Testability of Current Tests in an AGC Circuit, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 131, Oct. 2003.
29.	Satoshi Matsuda, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Bridging Faults for Oscillation Frequency to be Estimated for the Fault Detection, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 130, Oct. 2003.
30.	Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Finding Invalid States Using Strongly Unreachable States, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 149, Oct. 2002.
31.	Yoshihide Shoji, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : An Improvement of Generating Test Sequence for Test Time Reduction of Current Testing, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 148, Oct. 2002.
32.	Hirokazu Sano, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Reduction of Test Vectors by Focusing on the Number of Detection of Stuck-at Faults in Combinational Circuits, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 147, Oct. 2002.
33.	Taisuke Iwakiri, Hiroyuki Yotsuyanagi, Masaki Hashizume, Masahiro Ichimiya and Takeomi Tamesada : Test Set Compaction for Supply Current Test of Open Defects in CMOS ICs, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 146, Oct. 2002.
34.	Daisuke Yoneda, Masaki Hashizume, Takeshi Koyama, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Noise Removal for IDDQ Testing by Wavelet Transformation, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 143, Oct. 2002.
35.	Teppei Takeda, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Feasibility of IDDQ Test Time Reduction by Changing Test Input Application Interval, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 142, Oct. 2002.
36.	Takao Minami, Masaki Hashizume, Eiji Tasaka, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Toshihiro Kayahara : A Power-off Test Method for IC Pin Opens, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 141, Oct. 2002.
37.	Naoki Maeda, Masahiro Ichimiya, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Feasibility of Pin Open Detection in BGA ICs by Supply Current Test under AC Magnetic Field, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 140, Oct. 2002.
38.	Masao Takagi, Isao Tsukimoto, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Pin Open Detection for CMOS Logic ICs of PLCC Package by Measuring Supply Current under AC Electric Field, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 139, Oct. 2002.
39.	Isao Tsukimoto, Masaki Hashizume, Yukiko Mushiaki, Hiroyuki Yotsuyanagi, Masao Takagi and Takeomi Tamesada : Effectivity of Current Testing for Open Faults Undetected by Functional Testing in TTL Combinational Circuits, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 138, Oct. 2002.
40.	Takahiro Ohnishi, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Logic Simulator for Test Input Sequence Evaluation for IDDQ Testing, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 151, Sep. 2001.
41.	Taisuke Iwakiri, Hiroyuki Yotsuyanagi, Masaki Hashizume, Masahiro Ichimiya and Takeomi Tamesada : Evaluation of Stuck-at Pattern and Random Pattern in Supply Current Test of Open Defects, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 150, Sep. 2001.
42.	Shinsuke Hata, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Sequential Redundancy Removal Based on Multiple Unreachable States, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 145, Sep. 2001.
43.	Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Finding Unreachable States with Reducing Search Space, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 144, Sep. 2001.
44.	Masaki Hashizume, Masashi Sato, Hiroyuki Yotsuyanagi, Masahiro Ichimiya and Takeomi Tamesada : Power Consumption in High Speed ADCL Circuits, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 143, Sep. 2001.
45.	Akihiro Tsuji, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Experimental Evaluation of Pin Open Detection Method with Time-variable Magnetic Field, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 141, Sep. 2001.
46.	Naoki Maeda, Masahiro Ichimiya, 谷俊一, Masaki Hashizume and Takeomi Tamesada : Preventive Saturation Amplifier of Electrical Diagnostic System for Entrapment Neuropathy, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 138, Sep. 2001.
47.	Yukiko Mushiaki, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Fault Coverages of Supply Current Testing for Open Faults in TTL Circuits, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, No.10-10, 150, Oct. 2000.
48.	Akihiro Tsuji, Masahiro Ichimiya, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : A Solder Floating Test by Current Testing with AC Electric Field Applied, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, No.10-9, 149, Oct. 2000.
49.	Tomonari Matsuo, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Eiji Tasaka and Toshihiro Kayahara : Functional Fault Simulator for Bridging Faults in Boiler Control Microcomputer, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, No.10-8, 148, Oct. 2000.
50.	Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Synthesis for Testability by Adding State Transitions and Redundancy Removal, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, No.10-7, 147, Oct. 2000.
51.	Takahiro Ohnishi, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : A Test Input Sequence for Test Time Reduction of I_DDQ Testing, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, No.10-6, 146, Oct. 2000.
52.	Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Open Fault Detection Based on Supply Current in CMOS ICs, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, No.10-5, 145, Oct. 2000.
53.	Sou Yamamoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Oscillation Frequency Estimation Method of Feedback Bridging Faults, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, No.9-5, 133, Oct. 2000.
54.	Hiroshi Hoshika, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Improvement of IDDQ Testable Design for Static CMOS PLAs, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, No.9-4, 132, Oct. 2000.
55.	Kouichi Sugimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : High Speed Current Test Circuit for CMOS Logic Circuits, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, No.9-3, 131, Oct. 2000.
56.	Masashi Sato, Masaki Hashizume, Hiroyuki Yotsuyanagi, Masahiro Ichimiya and Takeomi Tamesada : Power Supply Circuit for High Speed ADCL Circuits, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, No.9-2, 130, Oct. 2000.

Et cetera, Workshop:

1.	Seiichi Nishimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : At-Speed Current Test Method of Open and Short Defects at Buses in Microcomputers, 第54回FTC研究会資料, Jan. 2006.
2.	Takeshi Iihara, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : On Configuring Scan Trees for Multiple-core Design Based on Circuit Structure, 第54回FTC研究会資料, Jan. 2006.
3.	Tomohiko Nagashima, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : On Test Generation for Sequential Circuits Using Limited Scan Operation Considering Initial States, 第52回FTC研究会資料, Jan. 2005.
4.	Yoshiteru Fujimoto, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Extraction of Fault Candidate Areas with Layout Information, IEICE Technical Report, Vol.104, No.478, 79-84, Dec. 2004. (Summary) In this paper, we present a method for extracting fault candidate areas using layout information obtained by CAD. In highly-integrated circuits, a bridging fault may affect not only between two signal lines, but also among multiple signal lines. In this work, we propose a procesure for extracting fault candidate areas of bridging faults between two lines and bridging faults among three lines. The procedure extracts pairs of signal lines whose distance is within the given distance and identifies them as the fault candidate of a bridging fault, and also extracts groups of three signal lines within the given distance and identifies them as the fault candidate of a multinode bridging fault. The procedure that utilizes a layout information obtained from CAD tools to extract fault candidate areas of bridging faults among two or three lines is shown. The experimental results for benchmark circuits are shown for the comparison between the number of the fault candidate areas obtained by the proposed method and the number of the bridging faults between two lines assumed from gate-level. (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1520009408554202240 (CiNii: 1520009408554202240)
5.	Daisuke Yoneda, Masaki Hashizume, Hiroyuki Yotsuyanagi, Tetsuo Tada, Takeshi Koyama and Takeomi Tamesada : IDDQ Testing Based on Wavelet Transform, 第50回FTC研究会資料, Jan. 2004.
6.	Hirokazu Sano, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Test Generation for Sequential Circuits by Logic Simulation using State Partitioning, IEICE Technical Report, No.DC2003-34, 1-6, Nov. 2003. (Summary) 本論文では,状態集合分割を用いた論理シミュレーションによるテスト生成について述べる.本研究で行うテスト生成では,複数の候補ベクトルを作成し,未到達状態へ遷移可能なベクトルをテストベクトルとして採用する.故障検出に有効な状態遷移を得るために,フリップフロップを複数の集合に分割し,重み付けによる状態変化の優先度の設定を行う.状態集合の分割法として,フリップフロップの論理値の制御容易性に基づく分割法と,未検出故障への影響の大きいフリップフロップを回路構造から求め集合分割を行う手法の2つを用いる.本研究では各未検出故障の励起,伝搬に必要なフリップフロップを考慮した集合分割を用いることで,未検出故障の検出に必要な状態遷移を優先する.提案する集合分割法をテスト生成に適用した結果により,集合分割法の有効性について示す. (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1520009409437334144 (CiNii: 1520009409437334144)
7.	Tetsuo Akita, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Built-in Supply Current Sensor Circuit for Detecting Open Faults in CMOS ICs, 第49回FTC研究会資料, Jul. 2003.
8.	Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : AC Electric Field Application Method in Supply Current Tests for IC Pin Open Detection, 第48回FTC研究会資料, Jan. 2003.
9.	Nobuyuki Inoo, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Oscillation Frequency Estimation for Detecting Feedback Bridging Faults, 第47回FTC研究会資料, Jul. 2002.
10.	Takahiro Ohnishi, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : A Test Input Sequence for Test Time Reduction of IDDQ Testing, 第46回FTC研究会資料, Jan. 2002.
11.	Akihiro Tsuji, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Pin Open Detection Method Based on Supply Current in Time-variable Magnetic Field, 第45回FTC研究会資料, Jul. 2001.
12.	Hiroyuki Yotsuyanagi, Masaki Hashizume, Takeomi Tamesada and Masahiro Ichimiya : On Detecting CMOS Open Defect by Applying Electric Field and Generating Its Test Pattern, 第44回FTC研究会資料, Jan. 2001.
13.	Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Adding Transitions of Undefined States to State Transition Tables for Testability Enhancement, Workshop on RTL ATPG & DFT (WRTLT00), Sep. 2000. (Summary) In this paper we propose procedures to enhance testability by adding transitions of undefined states to state transition tables. In these procedures, transitions about undefined states, which are not described in state transition tables but exist in a synthesized gate level circuit, are added to a state transition table. Experimental results for MCNC benchmarks are shown.
14.	Masaki Hashizume, Masashi Sato, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Power Supply Circuit for Adiabatic Dymanic CMOS Circuits, IEICE Technical Report, No.FTS99-6, 1-6, Apr. 1999. (Summary) 本論文では，断熱的ダイナミックCMOS論理回路用の電源回路を提案している．断熱的ダイナミックCMOS回路では従来のCMOS論理回路の場合のような一定電圧でなく, 正弦波や三角波のような時変電圧を発生する電源を必要とする．断熱的ダイナミックCMOS回路の動作速度はその電源波形の周波数で決まることから, 高速に電源電圧を変化させ, かつ寄生容量に蓄積されたエネルギーを急速に回収できる電源が必要である．本論文ではそれが可能な電源回路を提案し, 断熱的ダイナミックCMOSインバータ回路を駆動し, その消費電力を回路シミュレーションにより調査している．その結果は, ADCL回路を本電源回路で駆動することにより, 従来のCMOS回路に比べ大幅な低消費電力化が実現できることを示している． (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1520009410310609536 (CiNii: 1520009410310609536)
15.	Hiroyuki Yotsuyanagi, Masaki Hashizume, Takeomi Tamesada and Kozo Kinoshita : A Method for Removing Sequentially Redundant Lines Simultaneously Based on Unreachable States, IEICE Technical Report, No.FTS98-124, 9-16, Feb. 1999. (Summary) We propose a redundancy removal method based on strongly unreachable states, which are states that have no incoming transition from any state. If a fault affects the output sequence or the state transition only when the circuit starts from strongly unreachable states, then the fault is undetectable. More over, if the unreachable states are also strongly unreachable in the faulty circuit, the line corresponding the fault is redundant. In this paper, we present the theorem that the undetectable faults obtained from a strongly unreachable state remain undetectable for the circuit after removing the redundant lines corresponding to one of the faults. We also consider the condition for removing redundant lines simultaneously. Experimental results for benchmark circuits are shown. (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1571698602307652224 (CiNii: 1571698602307652224)
16.	Masaki Hashizume, Takeomi Tamesada and Ikuro Morita : 上肢切断者のための顔面方位による計算機への入力キー選択法, 第14回バイオメカニカルシンポジウム, 175-184, Jul. 1995.
17.	山田和浩, Masaki Hashizume, Takeomi Tamesada and 河上正明 : 電源電流による組合せ回路の故障検出法, IEICE Technical Report, Vol.VLD-88, No.55, 1-8, 1988.
18.	H. Y. Kawai, Masaki Hashizume and Takeomi Tamesada : A Tr-Amplifier Design Utilizing a Circuit Simulator, IEICE Technical Report, Vol.CAS-88, No.69, 67-73, 1988.
19.	井下順功, Masaki Hashizume and Takeomi Tamesada : 回路モジュールのタイミングチャートを利用した論理シミュレータ, IEICE Technical Report, Vol.VLD-87, No.103, 45-52, 1987.
20.	桝田真喜夫, 山田和浩, Masaki Hashizume and Takeomi Tamesada : 電源電流波形による論理回路の故障診断法, IEICE Technical Report, Vol.FTS-87, No.16, 5-10, 1987.
21.	平野収三, Masaki Hashizume and Takeomi Tamesada : マイクロコンピュータの編集設計システムの試作, 情報処理学会設計自動化研究会, Vol.DA-34, No.5, 1-8, 1986.
22.	Masaki Hashizume, 山本博資, Takeomi Tamesada and 埴渕敏明 : 内容検索メモリの性能評価, IEICE Technical Report, Vol.EC84, No.50, 1-11, 1985.
23.	竹内成和, 山本博資 and Takeomi Tamesada : リープフロッグ形SCF構成法に関する一検討, CAS, Vol.82, No.13, 65-72, May 1982.

Patent:

1.	古川靖夫, Masahiro Ichimiya, Masaki Hashizume and Takeomi Tamesada : LSI試験装置, 401987 (Dec. 2000), .
2.	古川靖夫, Masaki Hashizume, Masahiro Ichimiya and Takeomi Tamesada : IDDQ試験装置, (Sep. 1999), .
3.	Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, 茅原敏広 and 田坂英司 : ディジタル電子計算機回路の故障検査方法, 009177 (Jan. 1999), .
4.	Masaki Hashizume, Takeomi Tamesada, 田坂英司 and 茅原敏広 : シーケンス制御機器の故障検査法, 313569 (Oct. 1991), 19533 (Jan. 1994), 2611892 (Feb. 1997).

Professor Emeritus : Tamesada, Takeomi

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