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Research Activity

Field of Study

Electronic Circuit Engineering

Subject of Study

高速演算回路, 論理回路の設計と検査 (logic circuit, Design & Test)

Book / Paper

Book:

1. 石黒 美種, 仁田 工吉, Norio Akamatsu, 生田 信晧, Katsuo Isaka, Akio Ushida, Hiroshi Kawakami, Yohsuke Kinouchi, 小林 邦博, 島田 良作, Takayuki Suzuki, Takeomi Tamesada, 森 一郎, Masuo Fukui and 横井 良秀 :
電気·電子工学実験(electrical and eiectronic experiments,in japanese),
産業図書, Tokyo, Apr. 1974.

Academic Paper (Judged Full Paper):

1. 月本 功, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
ばらつきを有するICで構成したTTL回路の電源電流による統計的断線故障検出法,
Journal of Japan Institute of Electronics Packaging, Vol.8, No.3, 199-207, 2005.
(DOI: 10.5104/jiep.8.199,   CiNii: 10015530074)
2. Masaki Hashizume, Teruyoshi Matsushima, Takashi Shimamoto, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Akio Sakamoto :
Genetic State Reduction Method of Incompletely Specified Machines,
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E87-A, No.6, 1555-1563, 2004.
(CiNii: 110003213072,   Elsevier: Scopus)
3. Masao Takagi, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Lead Open Detection Based on Supply Current of CMOS LSIs,
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E87-A, No.6, 1330-1337, 2004.
(CiNii: 110003213039,   Elsevier: Scopus)
4. Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
Test Sequence Generation for Test Time Reduction of IDDQ Testing,
IEICE Transactions on Information and Systems, Vol.E87-D, No.3, 537-543, 2004.
(CiNii: 110003213908,   Elsevier: Scopus)
5. Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Identification and Frequency Estimation of Feedback Bridging Faults Generating Logical Oscillation in CMOS Circuits,
IEICE Transactions on Information and Systems, Vol.E87-D, No.3, 571-579, 2004.
(CiNii: 110003213913,   Elsevier: Scopus)
6. Hiroyuki Yotsuyanagi, Taisuke Iwakiri, Masaki Hashizume and Takeomi Tamesada :
Test Pattern Generation for CMOS Open Defect Detection by Supply Current Testing under AC Electric Field,
IEICE Transactions on Information and Systems, Vol.E86-D, No.12, 2666-2673, 2003.
(CiNii: 110003213691,   Elsevier: Scopus)
7. Masaki Hashizume, 田坂 英司, Hiroyuki Yotsuyanagi, Takeomi Tamesada, 茅原 敏広, Ikuro Morita and Takahiro Oie :
CMOSマイクロコンピュータ回路の電源電流によるブリッジ故障検出法,
Journal of Japan Institute of Electronics Packaging, Vol.6, No.7, 564-572, 2003.
(DOI: 10.5104/jiep.6.564,   CiNii: 10013959093)
8. Masahiro Ichimiya, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
A Test Circuit for Pin Shorts Generating Oscillation in CMOS Logic Circuits,
The Transactions of the Institute of Electronics, Information and Communication Engineers D-I, Vol.J86-D-I, No.6, 402-411, 2003.
(CiNii: 110003206846)
9. Masahiro Ichimiya, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Pin Open Detection for CMOS Logic ICs by Measuring Supply Current under AC Electric Field,
Journal of Japan Institute of Electronics Packaging, Vol.6, No.2, 140-146, 2003.
(DOI: 10.5104/jiep.6.140,   CiNii: 10013958458)
10. Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
CMOS Open Defect Detection by Supply Current Measurement under Time-Variable Electric Field Supply,
IEICE Transactions on Information and Systems, Vol.E85-D, No.10, 1542-1550, 2002.
(CiNii: 110006376584,   Elsevier: Scopus)
11. Masaki Hashizume, Hiroshi Hoshika, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Testable Static CMOS PLA for IDDQ Testing,
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E84-A, No.6, 1488-1495, 2001.
(CiNii: 110003208959,   Elsevier: Scopus)
12. Masaki Hashizume, Takeomi Tamesada, 小山 健 and A.J. van de Goor :
CMOS SRAM ICの書き込み時静的電源電流による論理故障検出法,
The Transactions of the Institute of Electronics, Information and Communication Engineers D-I, Vol.J82-D-I, No.7, 906-915, 1999.
13. 口井 敏匡, Masaki Hashizume and Takeomi Tamesada :
プリント回路板上のTTL組み合わせ回路の電源電流による断線故障検出法,
エレクトロニクス実装学会誌, Vol.1, No.4, 284-293, 1998.
14. Masaki Hashizume, Takeomi Tamesada, Takashi Shimamoto and Akio Sakamoto :
Heuristic State Reduction Methods of Incompletely Specified Machines Preceding to Satisfy Covering Condition,
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E81-A, No.6, 1045-1054, 1998.
15. Masaki Hashizume, 矢野 武志, 口井 敏匡 and Takeomi Tamesada :
電流テストによるバイポーラ組合せ論理回路のブリッジ故障検出のための検査容易化設計法,
The Transactions of the Institute of Electronics, Information and Communication Engineers D-I, Vol.J79-I, No.12, 1092-1104, 1996.
16. Masaki Hashizume, Y. Iwata and Takeomi Tamesada :
Performance Evaluation for Fault Detection of Analog Electronic Circuits,
Fuzzy Logic and Its Applications to Engineering, 255-264, 1995.
17. Masaki Hashizume, Takeomi Tamesada and Koji Nii :
Fuzzy Multiobjective Satisficing Programming Utilizing Expertise Knowledge,
Fuzzy Optimization Recent Advances, 220-233, 1994.
18. Masaki Hashizume, Takeomi Tamesada and 新居 浩二 :
下限満足度制約をもつファジィ多目的計画問題の近似的満足解導出法,
The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.J74-D-I, No.2, 109-116, 1991.
19. Masaki Hashizume, Takeomi Tamesada and 新居 浩二 :
凸ファジー決定によるアナログ回路の回路定数最適化法,
The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.J73-A, No.8, 1350-1358, 1990.
20. Masaki Hashizume and Takeomi Tamesada :
TTL組合せ論理回路の電源電流による故障検出法,
The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.J73-D-I, No.7, 621-629, 1990.
21. Masaki Hashizume, 桝田 真喜夫, 山田 和浩 and Takeomi Tamesada :
自己回帰モデルを用いた電源電流波形による論理回路の故障診断法,
The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.J71-D, No.9, 1804-1814, 1988.
22. Takeomi Tamesada :
最小冗長P進表現を用いた高速除算,
The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.J71-D, No.6, 957-965, 1988.
23. Takeomi Tamesada :
必要最小冗長P進表現を用いた高速複数オペランド加減算,
The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.J71-D, No.4, 626-635, 1988.
24. Takeomi Tamesada :
最小冗長P進表現を用いた高速乗算,
The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.J71-D, No.1, 44-51, 1988.
25. Takeomi Tamesada :
最小冗長P進表現を用いた高速加減算,
The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.J70-D, No.10, 1853-1858, 1987.
26. Masaki Hashizume, 山本 博資, Takeomi Tamesada and 埴渕 敏明 :
内容検索メモリを用いた検索システムの速度性能の評価,
The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.J70-D, No.9, 1709-1717, 1987.
27. Takeomi Tamesada :
無安定マルチバイブレータの再生転移に関する基礎解析,
The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.J69-D, No.2, 248-258, 1986.
28. Takeomi Tamesada and 山本 博資 :
TTL-NANDゲートを用いた無安定マルチバイブレータの動作モード解析,
The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.J65-D, No.2, 218-225, 1982.
29. Takeomi Tamesada :
Sequential Machines having Quasi-Stable States and Their State Reduction,
Transactions of the IEICE of Japan, Vol.E-64, No.3, 147-154, 1981.
30. Takeomi Tamesada :
Sequential Machines having Quasi-Stable States,
Transactions on Computers, Vol.C-29, No.5, 405-408, 1980.
31. 木下 敏治, 原田 尚文, Takeomi Tamesada, 稲井 義正 and 榊原 久司 :
電動義手の柔らかい協調動作制御の一方式,
バイオメカニズム, Vol.2, No.2, 121-130, 1978.
32. Takeomi Tamesada, 原田 尚文 and 島田 良作 :
3個のNAND/NOR回路を基本回路とする3相マルチバイブレータ,
The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.59-D, No.9, 605-612, 1976.
33. Takeomi Tamesada, 原田 尚文 and 島田 良作 :
準安定状態をもつ順序回路の合成,
The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.59-D, No.4, 276-283, 1976.
34. Takeomi Tamesada, 原田 尚文 and 島田 良作 :
準安定状態をもつ順序論理回路とその論理解析,
The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.59-D, No.2, 69-76, 1976.
35. 島田 良作 and Takeomi Tamesada :
RS形双安定回路の転移条件と臨界トリガ·パルス,
IEICE Transactions on Electronics, Vol.52, No.4, 226-232, 1969.

Academic Paper (Unrefereed Paper):

1. 木下 敏治, Takeomi Tamesada, 高木 正夫, 高橋 直樹 and 垂水 靖志 :
近似制御式を用いた肩義手の顔面方位制御システム,
詫間電波工業高等専門学校研究紀要, No.17, 59-72, 1989.
2. Takeomi Tamesada and Masahiro Ichimiya :
ECLゲートを用いた無安定マルチバイブレータの特性,
Bulletin of Faculty of Engineering, The University of Tokushima, No.34, 45-55, 1989.
3. 木下 敏治, 高木 正夫, Takeomi Tamesada, 顧 蘭明 and 倉本 雅史 :
X-Y-Z座標変換制御アルゴリズムを用いた肩義手の上体方位制御システム,
詫間電波工業高等専門学校研究紀要, No.16, 61-75, 1988.
4. 長岡 暁, 細川 義夫, 木下 敏治, 原田 尚文 and Takeomi Tamesada :
電動義手の視点制御方式の改良に関する研究,
Bulletin of Faculty of Engineering, The University of Tokushima, No.24, 77-86, 1979.
5. 山本 友一郎, 榊原 久司, 原田 尚文, 島田 良作 and Takeomi Tamesada :
表面筋電図と針電極筋電図の比較について,
Bulletin of Faculty of Engineering, The University of Tokushima, No.19, 113-123, 1974.
6. 西野 豊, 原田 尚文, 島田 良作, Takeomi Tamesada and 榊原 久司 :
電動義手の協調動作制御回路について,
Bulletin of Faculty of Engineering, The University of Tokushima, No.19, 105-111, 1974.
7. 原田 尚文, 島田 良作 and Takeomi Tamesada :
三相マルチバイブレータ(その2),
Bulletin of Faculty of Engineering, The University of Tokushima, Vol.18, No.18, 151-159, 1973.
(CiNii: 110001045071)
8. 森村 和由, 原田 尚文, 島田 良作 and Takeomi Tamesada :
学習制御についての一研究,
Bulletin of Faculty of Engineering, The University of Tokushima, Vol.18, No.18, 161-168, 1973.
(CiNii: 110001045072)
9. 戸倉 信之, 原田 尚文, 島田 良作 and Takeomi Tamesada :
薄膜磁性線三値記憶装置,
Bulletin of Faculty of Engineering, The University of Tokushima, No.17, 17-20, 1972.
10. 原田 尚文, 島田 良作 and Takeomi Tamesada :
三相マルチバイブレータ(その1),
Bulletin of Faculty of Engineering, The University of Tokushima, No.17, 21-32, 1972.
11. 根来 重泰, 原田 尚文, 島田 良作 and Takeomi Tamesada :
シミュレーション手法によるサンプル値制御系の最適調整について,
Bulletin of Faculty of Engineering, The University of Tokushima, No.16, 117-122, 1971.
12. 岸本 明, 原田 尚文, 島田 良作 and Takeomi Tamesada :
置換と束演算を用いた三値論理回路の設計,
Bulletin of Faculty of Engineering, The University of Tokushima, No.16, 105-115, 1971.
13. Takeomi Tamesada, 島田 良作 and 原田 尚文 :
トランジスタ双安定MVのトリガに関する研究,
Bulletin of Faculty of Engineering, The University of Tokushima, Vol.13, No.13, 57-70, 1968.
(CiNii: 110001040265)
14. 浜口 幸彦, 原田 尚文, 島田 良作 and Takeomi Tamesada :
Analysis of the Short-wave Recording on a Magnetic Tape,
Bulletin of Faculty of Engineering, The University of Tokushima, Vol.12, No.12, 101-107, 1967.
(CiNii: 110001036758)
15. 岩佐 恭一, 繖 晃一郎, 原田 尚文, 島田 良作 and Takeomi Tamesada :
Investigation on Three Valued Logic Circuits,
Bulletin of Faculty of Engineering, The University of Tokushima, Vol.12, No.12, 95-99, 1967.
(CiNii: 110001036757)
16. Takeomi Tamesada, 島田 良作 and 原田 尚文 :
トランジスタ双安定MVのトリガに関する研究,
Bulletin of Faculty of Engineering, The University of Tokushima, No.11, 79-92, 1966.

Academic Letter:

1. Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
Sequential Redundancy Removal Using Test Generation and Multiple Strongly Unreachable States,
IEICE Transactions on Information and Systems, Vol.E85-D, No.10, 1605-1608, 2002.
(CiNii: 110006376593,   Elsevier: Scopus)
2. Masaki Hashizume, Tasaka Eiji, Takeomi Tamesada, Kayahara Toshihiro and Yamazoe Tomohisa :
A Practical Functional Test Using Flowchart for Production Testing of Microprocessor Based Sequence Controllers,
Transactions of the IEICE of Japan, Vol.E76-D, No.7, 837-841, 1993.
3. Masaki Hashizume, Takeomi Tamesada and 山田 和浩 :
TTL組合せ論理回路の故障検出のための電源電流標準パターン候補導出法,
The Transactions of the Institute of Electronics, Information and Communication Engineers D-I, Vol.J73-D-I, No.7, 637-640, 1990.
4. Masaki Hashizume, 山本 博資, Takeomi Tamesada and 高橋 一磨 :
樹枝状に分割可能な組合せ回路の故障検出入力生成法,
Transactions of Information Processing Society of Japan, Vol.29, No.6, 627-630, 1988.
5. Takeomi Tamesada :
最小冗長P進表現を用いた高速減算,
The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.J70-D, No.12, 2800-2801, 1987.
6. Takeomi Tamesada and Masahiro Ichimiya :
無安定マルチバイブレータの起動回路とその効果,
The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.J68-D, No.3, 408-409, 1985.
7. Takeomi Tamesada and Masahiro Ichimiya :
TTL-NAND無安定マルチバイブレータの出力電圧波形の改善,
The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.J67-D, No.7, 819-820, 1984.
8. Takeomi Tamesada :
TTL-NANDゲートを用いた出力波形と始動性の良好な無安定マルチバイブレータ,
The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.J66-D, No.5, 617-618, 1983.
9. Takeomi Tamesada :
3個のTTL-NANDゲートを用いた三相無安定マルチバイブレータ,
The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.J66-D, No.2, 226-227, 1983.
10. Takeomi Tamesada :
TTL-NANDゲートを用いた単一発振モード無安定マルチバイブレータ,
The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.J65-D, No.4, 486-487, 1982.

Proceeding of International Conference:

1. Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Open Lead Detection Based on Supply Current of CMOS Logic Circuits by AC Voltage Signal Application,
Proceedings of ICEP2006, 147-152, Tokyo, Apr. 2006.
2. Tomohiko Nagashima, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
Test Time Reduction Method for Scan Design with Clock-Control DFT,
Proc. RISP International Workshop on Nonlinear Circuit and Signal Processing, 441-444, Honolulu, Mar. 2006.
3. Masaki Hashizume, Tomomi Nishida, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Yukiya Miura :
Current Testable Design of Resistor String DACs,
The IEEE International Workshop on Electronic Design, Test and Applications, 197-200, Kuala Lumpur, Malaysia, Jan. 2006.
(DOI: 10.1109/DELTA.2006.28)
4. Tomohiko Nagashima, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
Test Generation for Scan Circuits Using Random Selection of the Operations of Scan Flip-flops,
6th Workshop on RTL and High Level Testing (WRTLT05), 79-83, Harbin, China, Jul. 2005.
5. Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Electric Field for Detecting Open Leads in CMOS Logic Circuits by Supply Current Testing,
Proc. of IEEE International Symposium on Circuits and Systems, 2995-2998, Kobe, May 2005.
(DOI: 10.1109/ISCAS.2005.1465257)
6. Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Vectorless Open Pin Detection Method for CMOS Logic Circuits,
Proc. of International Conference on Electronics Packaging, 391-396, Tokyo, Apr. 2005.
7. Takashi Sakaguchi, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Tetsuo Tada, Takeshi Koyama, Yasuhiro Miyagawa, Seiji Tanaka and Toshihiro Kayahara :
Fail-Safe Evaluation Method for Boiler Control Circuits by Circuit Simulation,
Proc. RISP International Workshop on Nonlinear Circuit and Signal Processing, 395-398, Honolulu, Mar. 2005.
8. Seiichi Nishimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Electrical Detection of Pin Shorts by Supply Current of PIC,
Proc. RISP International Workshop on Nonlinear Circuit and Signal Processing, 171-174, Honolulu, Mar. 2005.
9. Masahiro Ichimiya, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Test Equipment for CMOS Lead Open Detection Based on Supply Current under AC Electric Field Application,
Proc. of the ECWC 10 Conference, P03-5-1-P03-5-5, Anaheim, Feb. 2005.
10. Masaki Hashizume, Daisuke Yoneda, Hiroyuki Yotsuyanagi, Tetsuo Tada, Takeshi Koyama, Ikuro Morita and Takeomi Tamesada :
IDDQ Test Method Based on Wavelet Transformation for Noisy Current Measurement Environment,
Proc. of 13th Asian Test Symposium, 112-117, Kenting, Taiwan, Nov. 2004.
(DOI: 10.1109/ATS.2004.50)
11. Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Test Circuit for CMOS Lead Open Detection by Supply Current Testing under AC Electric Field Application,
Proc. of the 2004 47-th Midwest Symposium on Circuits and Systems, I-557-I-560, Hiroshima, Jul. 2004.
(DOI: 10.1109/MWSCAS.2004.1354051)
12. Takagi Masao, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Tsukimoto Isao and Takeomi Tamesada :
AC Electric Field for Detecting Pin Opens by Supply Current of CMOS ICs,
Proc. of International Conference on Electronics Packaging, 217-222, Tokyo, Apr. 2004.
13. Daisuke Ezaki, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
A Power Supply Circuit Recycling Charge in Adiabatic Dynamic CMOS Logic Circuits,
Proc. of the second IEEE International Workshop on Electronic Design, Test, and Applications, 306-311, Perth, Australia, Jan. 2004.
(DOI: 10.1109/DELTA.2004.10022)
14. Isao Tsukimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Practical Fault Coverage of Supply Current Tests for Bipolar ICs,
Proc. of the second IEEE International Workshop on Electronic Design, Test, and Applications, 189-194, Perth, Australia, Jan. 2004.
(DOI: 10.1109/DELTA.2004.10035)
15. Masaki Hashizume, Tetsuo Akita, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
CMOS Open Fault Detection by Appearance Time of Switching Supply Current,
Proc. of the second IEEE International Workshop on Electronic Design, Test, and Applications, 183-188, Perth, Australia, Jan. 2004.
(DOI: 10.1109/DELTA.2004.10036)
16. Masaki Hashizume, Teppei Takeda, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura and Kozo Kinoshita :
A BIST Circuit for IDDQ Tests,
Proc. of Twelfth Asian Test Symposium, 390-395, Xi'an, Nov. 2003.
(DOI: 10.1109/ATS.2003.1250843)
17. Masaki Hashizume, Makoto Kawajiri, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Testability of Supply Current Test in an AGC Circuit,
Proc. of 2003 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.2, 836-839, Kang-Won Do, Korea, Jul. 2003.
18. Takagi Masao, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Testability of Pin Open in Small Outline Package ICs by Supply Current Test,
Proc. of the 2003 International Technical Conference on Circuits/Systems, Computers and Communications, 832-835, Kang-Won Do, Korea, Jul. 2003.
19. Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Electric Field Application Method Effective for Pin Open Detection Based on Supply Current in CMOS Logic Circuits,
Proc. of International Conference on Electronics Packaging, 75-80, Tokyo, Apr. 2003.
20. Masaki Hashizume, Teruyoshi Matsushima, Takashi Shimamoto, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Akio Sakamoto :
Simplification of Incompletely Specified Machine Based on Genetic Algorithm Implementing Dormant Mechanism,
3rd Workshop on RTL and High Level Testing (WRTLT02), 74-78, Guam, USA, Nov. 2002.
21. Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
Test Time Reduction for IDDQ Testing by Arranging Test Vectors,
Proc. of Eleventh Asian Test Symposium, 423-428, Guam, USA, Nov. 2002.
(DOI: 10.1109/ATS.2002.1181748)
22. Masaki Hashizume, Nobuyuki Inou, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Oscillation Frequency Estimation for Detecting Feedback Bridging Faults,
Proc. of 2002International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 1980-1983, Phuket, Thailand, Jul. 2002.
23. Isao Tsukimoto, Masaki Hashizume, Yukiko Mushiaki, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Testability of Current Testing for Open Faults Undetected by Functional Testing in TTL Combinational Circuits,
Proc. of 2002International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 1972-1975, Phuket, Thailand, Jul. 2002.
24. Masaki Hashizume, Tasaka Eiji, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Toshihiro Kayahara :
Power-off Vectorless Test Method for Pin Opens in CMOS Logic Circuits,
Proc. of International Conference on Electronics Packaging, 416-420, Tokyo, Apr. 2002.
25. Masaki Hashizume, Masashi Sato, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Power Supply Circuit for High Speed Operation of Adiabatic Dynamic CMOS Logic Circuits,
Proc. of the IEEE International Workshop on Electronic Design, Test, and Applications, 459-461, Christchurch, New Zealand, Jan. 2002.
(DOI: 10.1109/DELTA.2002.994673)
26. Hiroyuki Yotsuyanagi, Masaki Hashizume, Taisuke Iwakiri, Masahiro Ichimiya and Takeomi Tamesada :
Random Pattern Testability of the Open Defect Detection Method using Application of Time-variable Electric Field,
Proc. of the IEEE International Workshop on Electronic Design, Test, and Applications, 387-391, Christchurch, New Zealand, Jan. 2002.
(DOI: 10.1109/DELTA.2002.994656)
27. Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
CMOS Open Defect Detection Based on Supply Current in Time-variable Electric Field and Supply Voltage Application,
Proc. of Tenth Asian Test Symposium, 117-122, Kyoto, Nov. 2001.
(DOI: 10.1109/ATS.2001.990269)
28. Hiroyuki Yotsuyanagi, Shinsuke Hata, Masaki Hashizume and Takeomi Tamesada :
Sequential Redundancy Removal Using Test Generation and Multiple Unreachable States,
Proc. of Tenth Asian Test Symposium, 23-28, Kyoto, Nov. 2001.
(DOI: 10.1109/ATS.2001.990253)
29. Hiroyuki Yotsuyanagi, Masaki Hashizume, Taisuke Iwakiri, Masahiro Ichimiya and Takeomi Tamesada :
Test Pattern for Supply Current Test of Open Defects by Applying Time-variable Electric Field,
Proc. of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 287-295, San Francisco, Oct. 2001.
(DOI: 10.1109/DFTVS.2001.966781,   Elsevier: Scopus)
30. Teppei Takeda, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
A High Speed IDDQ Sensor Circuit,
Proc. of 2001 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.2, 438-441, Tokushima, Jul. 2001.
31. Masaki Hashizume, Eiji Tasaka, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Toshihiro Kayahara :
Fault Simulator for Test Program Generation in Supply Current Tests of Microprocessor Based Boiler Control Circuits,
Proc. of 2001 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 446-449, Tokushima, Jul. 2001.
32. Akihiro Tsuji, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Pin Open Detection Method Based on Supply Current in Time-variable Magnetic Field,
Proc. of 2001 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 438-441, Tokushima, Jul. 2001.
33. Masaki Hashizume, Akihiro Tsuji, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Supply Current Test for Pin Opens in CMOS Logic Circuits,
Proc. of International Conference on Electronics Packaging, 363-368, Tokyo, Apr. 2001.
34. Masaki Hashizume, Masahiro Ichimiya, Hiroshi Hoshika, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
CMOS Open Defect Detection by Supply Current Test,
Proc. of Design, Automation and Test in Europe Conference 2001, 509-513, Munich, Mar. 2001.
(DOI: 10.1109/DATE.2001.915071)
35. Masaki Hashizume, Hiroyuki Yotsuyanagi, Masahiro Ichimiya, Takeomi Tamesada and Masashi Takeda :
High Speed IDDQ Test and Its Testability for Process Variation,
IEEE Asian Test Symposium, 344-349, TAIPEI TAIWAN, Dec. 2000.
(DOI: 10.1109/ATS.2000.893647,   Elsevier: Scopus)
36. Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Masashi Takeda :
Testability Analysis of IDDQ Testing with Large Threshold Value,
IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 367-375, Yamanashi Japan, Oct. 2000.
(DOI: 10.1109/DFTVS.2000.887177,   Elsevier: Scopus)
37. Masashi Sato, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Power Supply Circuits with Small Size for Adiabatic Dynamic CMOS Logic Circuits,
Proc. of 2000 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 179-182, Busan, Jul. 2000.
38. Yukiko Mushiaki, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Practical Fault Coverage of Supply Current Testing for Open Fault in TTL Combinational Circuits,
Proc. of 2000 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 383-386, Busan, Jul. 2000.
39. Takahiro Ohnishi, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
A Test Input Sequence for Test Time Reduction of IDDQ Testing,
Proc. of 2000 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 367-370, Busan, Jul. 2000.
40. Hiroshi Hoshika, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
IDDQ Testable Design of Static CMOS PLAs with Low Power Consumption,
Proc. of 2000 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 351-354, Busan, Jul. 2000.
41. Sou Yamamoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Oscillation Frequency Estimation of Feedback Bridging Faults for Test Circuit Design,
Proc. of 2000 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 343-346, Busan, Jul. 2000.
42. Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
Synthesis for Testability by Adding Transitions of Undefined States to State Transition Tables,
Proc. of 2000 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 355-358, Busan, Jul. 2000.
43. Masaki Hashizume, Hiroshi Hoshika, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
IDDQ Testable Design of Static CMOS PLAs,
IEEE International Workshop on Defect Based Testing, 70-75, Montreal, Apr. 2000.
(DOI: 10.1109/DBT.2000.843693)
44. Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Identification of Feedback Bridging Faults with Oscillation,
IEEE Eighth Asian Test Symposium, 25-30, Shanghai, Nov. 1999.
(DOI: 10.1109/ATS.1999.810725)
45. Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Eiji Tasaka and Toshihiro Kayahara :
Supply Current testing for Bridging Faults in Microprocessor Based Sequence Control Circuits,
Proc. of Electronic Circuits World Convention 8, 31-37, Tokyo, Sep. 1999.
46. Masaki Hashizume, Masashi Sato, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Power Supply Circuit for Adiabatic Dynamic CMOS Logic Circuits,
Proc. of 1999 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 162-165, Niigata, Jul. 1999.
47. Teruyoshi Matsushima, Masaki Hashizume, Takeomi Tamesada, Takashi Shimamoto and Akio Sakamoto :
State Reduction of Incompletely Specified Machines based on Genetic Approach,
The 1999 International Technical Conference on Circuits/Systems, Computers and Communications, 888-891, Sado Island, Niigata, Jul. 1999.
48. Masaki Hashizume, Yukiya Miura, Masahiro Ichimiya, Takeomi Tamesada and Kozo Kinoshita :
A High Speed IDDQ Sensor for Low Voltage ICs,
IEEE Seventh Asian Test Symposium, 327-331, Singapore, Dec. 1998.
49. Toshimasa Kuchii, Masaki Hashizume and Takeomi Tamesada :
Test Input Generation for Supply Current Testing of Bridging Faults in Bipolar Combinational Logic Circuits,
Proc. of the IEEE International Workshop on IDDQ Testing, 14-18, San Jose, Nov. 1998.
50. Masaki Hashizume, Takeomi Tamesada, Takeshi Koyama and Goor de A.J.van :
CMOS SRAM Functional Test with Quiescent Write Supply Current,
Proc. of the IEEE International Workshop on IDDQ Testing, 4-8, San Jose, Nov. 1998.
51. Toshihiro Sezaki, Masaki Hashizume, Takeomi Tamesada and Ikuro Morita :
Supply Current Measurement Circuit for Bridging Fault Detection in Microprocessor Based Circuit,
Proceedings of ITC-CSCC'97 International Technical Conference on Circuits Systems, Computers and Comunications, 935-938, Okinawa, Jul. 1997.
52. Masaki Hashizume, Takeomi Tamesada, Takashi Shimamoto and Akio Sakamoto :
Genetic Approaches to State Reduction of Incompletely Specified Machines,
The 1997 International Technical Conference on Circuits/Systems, Computers and Communications, 463-466, Okinawa, Jul. 1997.

Proceeding of Domestic Conference:

1. Seiichi Nishimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Supply Current Test Program for Pin Short Detection in Z80,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 383, Sep. 2005.
2. Tatsuya Shimizu, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Power Consumption of a Time Varying Power Supplied Dynamic CMOS Adder,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 132, Sep. 2005.
3. Hiroshi Ohmura, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
Testability Evaluation of Open Faults in Consideration of the Voltage of the Adjacent Lines,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 130, Sep. 2005.
4. Katsumi Inoue, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
Design of Scan Tree Configuration of Sequential Circuits using CAD,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 129, Sep. 2005.
5. Takashi Sakaguchi, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Yukiya Miura :
Torelance of a Built-in IDDQ Test Circuit for Process Variation,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 120, Sep. 2005.
6. Takeshi Iihara, Masaki Hashizume, Tetsuo Tada, Takeshi Koyama, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Testabillity Analysis System of IDDQ Testing Based on Wavelet Transformation,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 119, Sep. 2005.
7. Masao Takagi, Masaki Hashizume, Isao Tukimoto, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Effects on Testability of Logic Value Outputting to Faulty Line in Lead Open Detection by Supply Current Testing,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 118, Sep. 2005.
8. Tatsuya Shimizu, Daisuke Ezaki, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Power Consumption in a Time Varying Power Supplied Dynamic CMOS Timer Circuit,
Proceedings of IEICE Society Conference, 92, Sep. 2005.
9. Seiichi Nishimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
At-Speed Test for Pin Shorts in Z80 by Supply Current Testing,
Proceedings of IEICE Society Conference, 83, Sep. 2005.
10. Takashi Sakaguchi, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Tetsuo Tada, Takeshi Koyama, Yasuhiro Miyagawa, Seiji Tanaka and Toshihiro Kayahara :
Fail-safe Evaluation System for Boiler Control Circuits,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 117, Sep. 2004.
11. Seiichi Nishimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
A Supply Current Test Method for Pin Shorts in PIC ICs,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 116, Sep. 2004.
12. Tetsuo Akita, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Mitsuo Shimotani :
Detection of Open Fault Realized by Transmission Gate with IDDT Disappearance Time Detection Circuit,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 115, Sep. 2004.
13. Daisuke Ezaki, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Operating Speed of Dynamic CMOS Logic Circuit Driven by Supply Voltage of Rectangle Waveform,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 114, Sep. 2004.
14. Shintaro Nakayashiki, Masahiro Ichimiya, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
IDDQ Test Circuit with a High Speed External Current Sensor,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 112, Sep. 2004.
15. Tomomi Nishida, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Yukiya Miura :
Testability of Supply Current Testing for DA Converters of Resistor String Type,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 111, Sep. 2004.
16. Masao Takagi, Masaki Hashizume, H. Ishii, Isao Tukimoto, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Pin Open Detection in CMOS TQFP ICs of Low Supply Voltage by Measuring Supply Current under AC Electric Field,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 110, Sep. 2004.
17. Isao Tsukimoto, Masao Takagi, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Deterministic Test Vector Generation of Supply Current Test for Open Faults Undetected by Functional Tests in TTL ICs,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 109, Sep. 2004.
18. Makoto Kawajiri, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Spice Model for Deriving Fault Model of Charge Coupled Devices,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 108, Sep. 2004.
19. Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
Constructing Scan Trees based on a Circuit Structure,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 156, Oct. 2003.
20. Hirokazu Sano, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
Test Generation for Sequential Circuits using Structure Based Partitioning,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 155, Oct. 2003.
21. Daisuke Ezaki, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
A Power Supply Circuit for Dynamic CMOS Logic Circuits,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 139, Oct. 2003.
22. Kenji Kaishita, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Low Power Dynamic CMOS Logic Circuits,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 138, Oct. 2003.
23. Tetsuo Akita, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Mitsuo Shimotani :
IDDT Test Circuit for Detecting Open Faults in CMOS ICs,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 137, Oct. 2003.
24. Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Tetsuo Tada, Takeshi Koyama, Yasuhiro Miyagawa, Seiji Tanaka and Toshihiro Kayahara :
Fail-safe Analysis for a Breaker Valve Circuit in a Boiler Control Circuit,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 136, Oct. 2003.
25. Masao Takagi, Isao Tukimoto, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Pin Open Detection for CMOS Logic ICs of TQFP Package by Measuring Supply Current under AC Electric Field,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 134, Oct. 2003.
26. Daisuke Yoneda, Masaki Hashizume, Tetsuo Tada, Takeshi Koyama, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
IDDQ Testing with Wavelet Transformation Technique,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 133, Oct. 2003.
27. Isao Tsukimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi, Masao Takagi and Takeomi Tamesada :
Practical Fault Coverage of Supply Current Tests for TTL ICs,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 132, Oct. 2003.
28. Makoto Kawajiri, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Testability of Current Tests in an AGC Circuit,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 131, Oct. 2003.
29. Satoshi Matsuda, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
Bridging Faults for Oscillation Frequency to be Estimated for the Fault Detection,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 130, Oct. 2003.
30. Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
Finding Invalid States Using Strongly Unreachable States,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 149, Oct. 2002.
31. Yoshihide Shoji, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
An Improvement of Generating Test Sequence for Test Time Reduction of Current Testing,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 148, Oct. 2002.
32. Hirokazu Sano, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
Reduction of Test Vectors by Focusing on the Number of Detection of Stuck-at Faults in Combinational Circuits,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 147, Oct. 2002.
33. Taisuke Iwakiri, Hiroyuki Yotsuyanagi, Masaki Hashizume, Masahiro Ichimiya and Takeomi Tamesada :
Test Set Compaction for Supply Current Test of Open Defects in CMOS ICs,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 146, Oct. 2002.
34. Daisuke Yoneda, Masaki Hashizume, Takeshi Koyama, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Noise Removal for IDDQ Testing by Wavelet Transformation,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 143, Oct. 2002.
35. Teppei Takeda, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Feasibility of IDDQ Test Time Reduction by Changing Test Input Application Interval,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 142, Oct. 2002.
36. Takao Minami, Masaki Hashizume, Eiji Tasaka, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Toshihiro Kayahara :
A Power-off Test Method for IC Pin Opens,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 141, Oct. 2002.
37. Naoki Maeda, Masahiro Ichimiya, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Feasibility of Pin Open Detection in BGA ICs by Supply Current Test under AC Magnetic Field,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 140, Oct. 2002.
38. Masao Takagi, Isao Tsukimoto, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Pin Open Detection for CMOS Logic ICs of PLCC Package by Measuring Supply Current under AC Electric Field,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 139, Oct. 2002.
39. Isao Tsukimoto, Masaki Hashizume, Yukiko Mushiaki, Hiroyuki Yotsuyanagi, Masao Takagi and Takeomi Tamesada :
Effectivity of Current Testing for Open Faults Undetected by Functional Testing in TTL Combinational Circuits,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 138, Oct. 2002.
40. Takahiro Ohnishi, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
Logic Simulator for Test Input Sequence Evaluation for IDDQ Testing,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 151, Sep. 2001.
41. Taisuke Iwakiri, Hiroyuki Yotsuyanagi, Masaki Hashizume, Masahiro Ichimiya and Takeomi Tamesada :
Evaluation of Stuck-at Pattern and Random Pattern in Supply Current Test of Open Defects,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 150, Sep. 2001.
42. Shinsuke Hata, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
Sequential Redundancy Removal Based on Multiple Unreachable States,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 145, Sep. 2001.
43. Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
Finding Unreachable States with Reducing Search Space,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 144, Sep. 2001.
44. Masaki Hashizume, Masashi Sato, Hiroyuki Yotsuyanagi, Masahiro Ichimiya and Takeomi Tamesada :
Power Consumption in High Speed ADCL Circuits,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 143, Sep. 2001.
45. Akihiro Tsuji, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Experimental Evaluation of Pin Open Detection Method with Time-variable Magnetic Field,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 141, Sep. 2001.
46. Naoki Maeda, Masahiro Ichimiya, 谷 俊一, Masaki Hashizume and Takeomi Tamesada :
Preventive Saturation Amplifier of Electrical Diagnostic System for Entrapment Neuropathy,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 138, Sep. 2001.
47. Yukiko Mushiaki, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Fault Coverages of Supply Current Testing for Open Faults in TTL Circuits,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, No.10-10, 150, Oct. 2000.
48. Akihiro Tsuji, Masahiro Ichimiya, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
A Solder Floating Test by Current Testing with AC Electric Field Applied,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, No.10-9, 149, Oct. 2000.
49. Tomonari Matsuo, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Eiji Tasaka and Toshihiro Kayahara :
Functional Fault Simulator for Bridging Faults in Boiler Control Microcomputer,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, No.10-8, 148, Oct. 2000.
50. Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
Synthesis for Testability by Adding State Transitions and Redundancy Removal,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, No.10-7, 147, Oct. 2000.
51. Takahiro Ohnishi, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
A Test Input Sequence for Test Time Reduction of IDDQ Testing,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, No.10-6, 146, Oct. 2000.
52. Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Open Fault Detection Based on Supply Current in CMOS ICs,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, No.10-5, 145, Oct. 2000.
53. Sou Yamamoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Oscillation Frequency Estimation Method of Feedback Bridging Faults,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, No.9-5, 133, Oct. 2000.
54. Hiroshi Hoshika, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Improvement of IDDQ Testable Design for Static CMOS PLAs,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, No.9-4, 132, Oct. 2000.
55. Kouichi Sugimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
High Speed Current Test Circuit for CMOS Logic Circuits,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, No.9-3, 131, Oct. 2000.
56. Masashi Sato, Masaki Hashizume, Hiroyuki Yotsuyanagi, Masahiro Ichimiya and Takeomi Tamesada :
Power Supply Circuit for High Speed ADCL Circuits,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, No.9-2, 130, Oct. 2000.

Et cetera, Workshop:

1. Seiichi Nishimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
At-Speed Current Test Method of Open and Short Defects at Buses in Microcomputers,
第54回FTC研究会資料, Jan. 2006.
2. Takeshi Iihara, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
On Configuring Scan Trees for Multiple-core Design Based on Circuit Structure,
第54回FTC研究会資料, Jan. 2006.
3. Tomohiko Nagashima, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
On Test Generation for Sequential Circuits Using Limited Scan Operation Considering Initial States,
第52回FTC研究会資料, Jan. 2005.
4. Yoshiteru Fujimoto, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
Extraction of Fault Candidate Areas with Layout Information,
IEICE Technical Report, Vol.104, No.478, 79-84, Dec. 2004.
(CiNii: 110003204332)
5. Daisuke Yoneda, Masaki Hashizume, Hiroyuki Yotsuyanagi, Tetsuo Tada, Takeshi Koyama and Takeomi Tamesada :
IDDQ Testing Based on Wavelet Transform,
第50回FTC研究会資料, Jan. 2004.
6. Hirokazu Sano, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
Test Generation for Sequential Circuits by Logic Simulation using State Partitioning,
IEICE Technical Report, No.DC2003-34, 1-6, Nov. 2003.
(CiNii: 110003173628)
7. Tetsuo Akita, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Built-in Supply Current Sensor Circuit for Detecting Open Faults in CMOS ICs,
第49回FTC研究会資料, Jul. 2003.
8. Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
AC Electric Field Application Method in Supply Current Tests for IC Pin Open Detection,
第48回FTC研究会資料, Jan. 2003.
9. Nobuyuki Inoo, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Oscillation Frequency Estimation for Detecting Feedback Bridging Faults,
第47回FTC研究会資料, Jul. 2002.
10. Takahiro Ohnishi, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
A Test Input Sequence for Test Time Reduction of IDDQ Testing,
第46回FTC研究会資料, Jan. 2002.
11. Akihiro Tsuji, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Pin Open Detection Method Based on Supply Current in Time-variable Magnetic Field,
第45回FTC研究会資料, Jul. 2001.
12. Hiroyuki Yotsuyanagi, Masaki Hashizume, Takeomi Tamesada and Masahiro Ichimiya :
On Detecting CMOS Open Defect by Applying Electric Field and Generating Its Test Pattern,
第44回FTC研究会資料, Jan. 2001.
13. Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
Adding Transitions of Undefined States to State Transition Tables for Testability Enhancement,
Workshop on RTL ATPG & DFT (WRTLT00), Sep. 2000.
14. Masaki Hashizume, Masashi Sato, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Power Supply Circuit for Adiabatic Dymanic CMOS Circuits,
IEICE Technical Report, No.FTS99-6, 1-6, Apr. 1999.
(CiNii: 110003194288)
15. Hiroyuki Yotsuyanagi, Masaki Hashizume, Takeomi Tamesada and Kozo Kinoshita :
A Method for Removing Sequentially Redundant Lines Simultaneously Based on Unreachable States,
IEICE Technical Report, No.FTS98-124, 9-16, Feb. 1999.
(CiNii: 110003194227)
16. Masaki Hashizume, Takeomi Tamesada and Ikuro Morita :
上肢切断者のための顔面方位による計算機への入力キー選択法,
第14回バイオメカニカルシンポジウム, 175-184, Jul. 1995.
17. 山田 和浩, Masaki Hashizume, Takeomi Tamesada and 河上 正明 :
電源電流による組合せ回路の故障検出法,
IEICE Technical Report, Vol.VLD-88, No.55, 1-8, 1988.
18. H. Y. Kawai, Masaki Hashizume and Takeomi Tamesada :
A Tr-Amplifier Design Utilizing a Circuit Simulator,
IEICE Technical Report, Vol.CAS-88, No.69, 67-73, 1988.
19. 井下 順功, Masaki Hashizume and Takeomi Tamesada :
回路モジュールのタイミングチャートを利用した論理シミュレータ,
IEICE Technical Report, Vol.VLD-87, No.103, 45-52, 1987.
20. 桝田 真喜夫, 山田 和浩, Masaki Hashizume and Takeomi Tamesada :
電源電流波形による論理回路の故障診断法,
IEICE Technical Report, Vol.FTS-87, No.16, 5-10, 1987.
21. 平野 収三, Masaki Hashizume and Takeomi Tamesada :
マイクロコンピュータの編集設計システムの試作,
情報処理学会設計自動化研究会, Vol.DA-34, No.5, 1-8, 1986.
22. Masaki Hashizume, 山本 博資, Takeomi Tamesada and 埴渕 敏明 :
内容検索メモリの性能評価,
IEICE Technical Report, Vol.EC84, No.50, 1-11, 1985.
23. 竹内 成和, 山本 博資 and Takeomi Tamesada :
リープフロッグ形SCF構成法に関する一検討,
CAS, Vol.82, No.13, 65-72, May 1982.

Patent:

1. 古川 靖夫, Masahiro Ichimiya, Masaki Hashizume and Takeomi Tamesada : LSI試験装置, 401987 (Dec. 2000), .
2. 古川 靖夫, Masaki Hashizume, Masahiro Ichimiya and Takeomi Tamesada : IDDQ試験装置, (Sep. 1999), .
3. Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, 茅原 敏広 and 田坂 英司 : ディジタル電子計算機回路の故障検査方法, 009177 (Jan. 1999), .
4. Masaki Hashizume, Takeomi Tamesada, 田坂 英司 and 茅原 敏広 : シーケンス制御機器の故障検査法, 313569 (Oct. 1991), 19533 (Jan. 1994), 2611892 (Feb. 1997).