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Tokushima University > Graduate School of Advanced Technology and Science > Systems Innovation Engineering > Electrical and Electronic Engineering > Intelligent Networks and Computer Science >
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Tokushima University > Research Clusters > Research Clusters (Registered) > 1804009 人工知能を用いた海水養殖支援システムの開発 >
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Research Activity

Field of Study

Computer Engineering

Subject of Study

順序回路の検査容易化に関する研究, 順序論理回路の簡単化に関する研究, 回路設計用CADに関する研究 (Test Technology, VLSI, fault tolerant computing, design automation)

Book / Paper

Book:

1.Kazuo Kondo, Morihiro Kada, Kenji Takahashi, Hiroshi Takahashi, Senling Wang, Shuichi Kameyama, Yoshinobu Higami, Hiroyuki Yotsuyanagi, Masaki Hashizume, Shyue-Kung Lu, Zvi Roth and et .al :
Three-Dimensional Integration of Semiconductors --- Processing, Materials, and Applications, --- Trends in 3D Integrated Circuit (3D-IC) Testing Technology ---,
Springer, Dec. 2015.
(DOI: 10.1007/978-3-319-18675-7_8,   Elsevier: Scopus)
2.LSIテスティング学会, Masaki Hashizume and Hiroyuki Yotsuyanagi :
LSIテスティングハンドブック,
Ohmsha, Ltd., Nov. 2008.

Academic Paper (Judged Full Paper):

1.ASHIKIN Fara, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung LU and Zvi ROTH :
A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs,
IEICE Transactions on Information and Systems, Vol.E101-D, No.8, 2053-2063, 2018.
(DOI: 10.1587/transinf.2018EDP7093,   Elsevier: Scopus)
2.Hiroyuki Yotsuyanagi, Kotaro Ise, Masaki Hashizume, Yoshinobu Higami and Hiroshi Takahashi :
Discrimination of a Resistive Open Using Anomaly Detection of Delay Variation Induced by Transitions on Adjacent Lines,
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E100-A, No.12, 2842-2850, 2017.
(DOI: 10.1587/transfun.E100.A.2842,   CiNii: 130006236547)
3.Fara Alia Ashikin, Akihiro Odoriba, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu :
Electrical Tests for Capacitive Open Defects in Assembled PCBs,
Journal of Telecommunication, Electronic and Computer Engineering, Vol.9, No.3-2, 49-52, 2017.
(Elsevier: Scopus)
4.Masaki Hashizume, Yudai Shiraishi, Hiroyuki Yotsuyanagi, Hiroshi Yokoyama, Tetsuo Tada and Shyue-Kung Lu :
Electrical Test of Resistive and Capacitive Open Defects at Data Bus in 3D Memory IC,
Journal of Telecommunication, Electronic and Computer Engineering, Vol.9, No.3-2, 39-42, 2017.
(Elsevier: Scopus)
5.Zheng-Hong Cai, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Modified PRPG for Test Data Reduction Using BAST Structure,
Journal of Signal Processing, Vol.21, No.4, 125-128, 2017.
(DOI: 10.2299/jsp.21.125)
6.(名) Widiant, Masaki Hashizume, Shohei Suenaga, Hiroyuki Yotsuyanagi, Akira Ono, Shyue-Kung Lu and Zvi Roth :
A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs,
IEICE Transactions on Information and Systems, Vol.E99-D, No.11, 2723-2733, 2016.
(DOI: 10.1587/transinf.2015EDP7273,   CiNii: 130005268125)
7.Masaki Hashizume, Yuki Ikiri, Konishi Tomoaki, Hiroyuki Yotsuyanagi and Shyue-Kung Lu :
Electrical Interconnect Test of Solder Joint Part with Boudary Scan Flip Flops and a Built-in Test Circuit,
Journal of Japan Institute of Electronics Packaging, Vol.19, No.3, 161-165, 2016.
8.Jun Yamashita, Hiroyuki Yotsuyanagi, Masaki Hashizume and Kozo Kinoshita :
SAT-Based Test Generation for Open Faults Using Fault Excitation Caused by Effect of Adjacent Lines,
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E96-A, No.12, 2561-2567, 2013.
(DOI: 10.1587/transfun.E96.A.2561,   CiNii: 130003385309)
9.Masaki Hashizume, Tomoaki Konishi and Hiroyuki Yotsuyanagi :
Electrical Testable Design for Open Defects at Logic Signal Lines between Dies in 3D ICs,
The Transactions of the Institute of Electronics, Information and Communication Engineers C, Vol.J96-C, No.11, 361-370, 2013.
(CiNii: 110009674644)
10.Hiroyuki Yotsuyanagi, Hiroyuki Makimoto, Takanobu Nimiya and Masaki Hashizume :
On Detecting Delay Faults Using Time-to-Digital Converter Embedded in Boundary Scan,
IEICE Transactions on Information and Systems, Vol.E96-D, No.9, 1986-1993, 2013.
(DOI: 10.1587/transinf.E96.D.1986,   CiNii: 130003370987)
11.Tomoaki Konishi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Electrical Test Method for Interconnect Open Defects in 3D ICs,
Transactions of The Japan Institute of Electronics Packaging, Vol.5, No.1, 26-33, 2012.
(DOI: 10.5104/jiepeng.5.26)
12.Masaki Hashizume, Kenji Kato and Hiroyuki Yotsuyanagi :
Electrical Testing of Open Defects between IEEE1149.1 Compliant ICs,
Journal of Japan Institute of Electronics Packaging, Vol.14, No.2, 99-102, 2011.
(DOI: 10.5104/jiep.14.99,   CiNii: 10028107475,   Elsevier: Scopus)
13.Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Hiroyuki Yotsuyanagi, Masaki Hashizume and Yuzo Takamatsu :
A Method for Locating Open Faults by Using a Fault Extraction Function,
The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.J93-D, No.11, 2416-2425, 2010.
(CiNii: 110007880364)
14.Hiroyuki Yotsuyanagi, Masaki Hashizume and Masayuki Yamamoto :
Scan Chain Ordering to Reduce Test Data for BIST-Aided Scan Test Using Compatible Scan Flip-Flops,
IEICE Transactions on Information and Systems, Vol.E93-D, No.1, 10-16, 2010.
(DOI: 10.1587/transinf.E93.D.10,   CiNii: 10026812956,   Elsevier: Scopus)
15.小野 安季良, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, 高木 正夫 and Masaki Hashizume :
Open lead detection method by sensing the switching current of CMOS gate on sensing probe,
Journal of Japan Institute of Electronics Packaging, Vol.12, No.2, 137-143, 2009.
(DOI: 10.5104/jiep.12.137,   CiNii: 110007122653,   Elsevier: Scopus)
16.高木 正夫, Masaki Hashizume, Masahiro Ichimiya and Hiroyuki Yotsuyanagi :
Applied AC Voltage for Detecting Open Leads of CMOS LSI by Monitoring Supply Current under AC Electric Field,
Journal of Japan Institute of Electronics Packaging, Vol.10, No.3, 219-228, 2007.
(DOI: 10.5104/jiep.10.219,   CiNii: 110006249330)
17.Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume and Kozo Kinoshita :
Reducing Scan Shifts Using Configurations of Compatible and Folding Scan Trees,
Journal of Electronic Testing - Theory and Applications, Vol.21, No.6, 613-620, 2005.
(DOI: 10.1007/s10836-005-2719-2)
18.月本 功, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
ばらつきを有するICで構成したTTL回路の電源電流による統計的断線故障検出法,
Journal of Japan Institute of Electronics Packaging, Vol.8, No.3, 199-207, 2005.
(DOI: 10.5104/jiep.8.199,   CiNii: 10015530074)
19.Masaki Hashizume, Teruyoshi Matsushima, Takashi Shimamoto, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Akio Sakamoto :
Genetic State Reduction Method of Incompletely Specified Machines,
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E87-A, No.6, 1555-1563, 2004.
(CiNii: 110003213072,   Elsevier: Scopus)
20.Masao Takagi, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Lead Open Detection Based on Supply Current of CMOS LSIs,
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E87-A, No.6, 1330-1337, 2004.
(CiNii: 110003213039,   Elsevier: Scopus)
21.Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
Test Sequence Generation for Test Time Reduction of IDDQ Testing,
IEICE Transactions on Information and Systems, Vol.E87-D, No.3, 537-543, 2004.
(CiNii: 110003213908,   Elsevier: Scopus)
22.Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Identification and Frequency Estimation of Feedback Bridging Faults Generating Logical Oscillation in CMOS Circuits,
IEICE Transactions on Information and Systems, Vol.E87-D, No.3, 571-579, 2004.
(CiNii: 110003213913,   Elsevier: Scopus)
23.Hiroyuki Yotsuyanagi, Taisuke Iwakiri, Masaki Hashizume and Takeomi Tamesada :
Test Pattern Generation for CMOS Open Defect Detection by Supply Current Testing under AC Electric Field,
IEICE Transactions on Information and Systems, Vol.E86-D, No.12, 2666-2673, 2003.
(CiNii: 110003213691,   Elsevier: Scopus)
24.Masaki Hashizume, 田坂 英司, Hiroyuki Yotsuyanagi, Takeomi Tamesada, 茅原 敏広, Ikuro Morita and Takahiro Oie :
CMOSマイクロコンピュータ回路の電源電流によるブリッジ故障検出法,
Journal of Japan Institute of Electronics Packaging, Vol.6, No.7, 564-572, 2003.
(DOI: 10.5104/jiep.6.564,   CiNii: 10013959093)
25.Masahiro Ichimiya, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
A Test Circuit for Pin Shorts Generating Oscillation in CMOS Logic Circuits,
The Transactions of the Institute of Electronics, Information and Communication Engineers D-I, Vol.J86-D-I, No.6, 402-411, 2003.
(CiNii: 110003206846)
26.Masahiro Ichimiya, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Pin Open Detection for CMOS Logic ICs by Measuring Supply Current under AC Electric Field,
Journal of Japan Institute of Electronics Packaging, Vol.6, No.2, 140-146, 2003.
(DOI: 10.5104/jiep.6.140,   CiNii: 10013958458)
27.Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
CMOS Open Defect Detection by Supply Current Measurement under Time-Variable Electric Field Supply,
IEICE Transactions on Information and Systems, Vol.E85-D, No.10, 1542-1550, 2002.
(CiNii: 110006376584,   Elsevier: Scopus)
28.Masaki Hashizume, Teppei Takeda, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Yukiya Miura and Kozo Kinoshita :
IDDQ Test Time Reduction by High Speed Charging of Load Capacitors of CMOS Logic Gates,
IEICE Transactions on Information and Systems, Vol.E85-D, No.10, 1534-1541, 2002.
(CiNii: 110006376583,   Elsevier: Scopus)
29.Masaki Hashizume, Hiroshi Hoshika, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Testable Static CMOS PLA for IDDQ Testing,
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E84-A, No.6, 1488-1495, 2001.
(CiNii: 110003208959,   Elsevier: Scopus)
30.Hiroyuki Yotsuyanagi and Kozo Kinoshita :
Finding Unreachable States of Sequential Circuits,
Technology Reports of the Osaka University, Vol.49, No.2344, 49-55, 1999.
31.Hiroyuki Yotsuyanagi, Seiji Kajihara and Kozo Kinoshita :
A Redundancy Removal Method for Sequential Circuits Based on Unreachable States,
The Transactions of the Institute of Electronics, Information and Communication Engineers D-I, Vol.J81-D-I, No.2, 204-212, 1998.
(CiNii: 110003315676)
32.Hiroyuki Yotsuyanagi, Seiji Kajihara and Kozo Kinoshita :
Synthesis of Sequential Circuits by Redundancy Removal and Retiming,
Journal of Electronic Testing - Theory and Applications, Vol.11, No.1, 81-92, 1997.
(DOI: 10.1023/A:1008251901959)
33.Hiroyuki Yotsuyanagi, Seiji Kajihara and Kozo Kinoshita :
Retiming for Sequential Circuits with a Specified Initial State and Its Application to Testability Enhancement,
IEICE Transactions on Information and Systems, Vol.E78-D, No.7, 861-867, 1995.
(CiNii: 110003209548)

Academic Paper (Unrefereed Paper):

1.Hiroyuki Yotsuyanagi and Masaki Hashizume :
On testing of open faults in multi-layered wiring LSIs,
Bulletin of Institute of Technology and Science, The University of Tokushima, No.53, 16-20, 2008.
(Tokushima University Institutional Repository: 59703,   CiNii: 110006863178)

Academic Letter:

1.Shohei Kondo, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Propagation Delay Analysis of a Soft Open Defect inside a TSV,
Transactions of The Japan Institute of Electronics Packaging, Vol.4, No.1, 119-126, 2011.
(DOI: 10.5104/jiepeng.4.119,   CiNii: 130002136664)
2.Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
Sequential Redundancy Removal Using Test Generation and Multiple Strongly Unreachable States,
IEICE Transactions on Information and Systems, Vol.E85-D, No.10, 1605-1608, 2002.
(CiNii: 110006376593,   Elsevier: Scopus)

Review, Commentary:

1.Hiroyuki Yotsuyanagi :
VLSI設計教育用設備の導入について,
広報, Vol.15, 41-42, Dec. 2008.
2.Masaki Hashizume and Hiroyuki Yotsuyanagi :
東京大学VDECのICツールを用いたICの設計と試作,
広報, Vol.13, 30-32, Dec. 2006.

Proceeding of International Conference:

1.Michiya Kanda, Daisuke Yabui, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu :
Stand-by Mode Test Method of Interconnects between Dies in 3D ICs with IEEE 1149.1 Test Circuits,
Proc. of IEEE CPMT Symposium Japan 2018, 189-192, Kyoto, Nov. 2018.
2.Yuta Matsumoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu :
Resistive Open Defect Detection in SoCs by a Test Method Based on Injected Charge Volume after Test Input Application,
Proc. of IEEE CPMT Symposium Japan 2018, 141-142, Kyoto, Nov. 2018.
(DOI: 10.1109/ICSJ.2018.8602818,   Elsevier: Scopus)
3.Satoshi Hirai, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Test Time Reduction on Testing Delay Faults in 3D ICs Using Boundary Scan Design,
Proc.of IEEE 27th Asian Test Symposium, 7-12, Hefei, Oct. 2018.
(DOI: 10.1109/ATS.2018.00013,   Elsevier: Scopus)
4.Ishihara Ken, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu :
Resistive Open Defects in 3D Stacked ICs Detected by Electrical Interconnect Testing with a Charge Injector Made of MOS Capacitors,
Proc. of 33rd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2018), 114-117, Bangkok, Jul. 2018.
5.Jumpei Kawano, Hiroyuki Yotsuyanagi and Masaki Hashizume :
On Design and Evaluation of a TDC Cell Embedded in the Boundary Scan Circuit for Delay Fault Testing of 3D ICs,
Proc. of 33rd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2018), 110-113, Bangkok, Jul. 2018.
6.Toshinori Hosokawa, Morito Niseki, Masayoshi Yoshimura, Hiroshi Yamazaki, Masayuki Arai, Hiroyuki Yotsuyanagi and Masaki Hashizume :
A Sequentially Untestable Fault Identification Method Based on n-Bit State Cube Justification,
24th IEEE International Symposium on On-Line Testing and Robust System Design, Spain, Jul. 2018.
(DOI: 10.1109/IOLTS.2018.8474268,   Elsevier: Scopus)
7.Jumpei Kawano, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Effect of Routing in Testing a TSV Array Using Boundary Scan Circuit with Embedded TDC,
Proc. of International Forum on Advanced Technologies 2018, P1-13-1-P1-13-3, Tokushima, Japan, Mar. 2018.
8.Alia Ashikin Fara, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu :
Electrical Tests for Capacitive Open Defects in Assembled PCBs,
Proc. of International Forum on Advanced Technologies 2018, P1-12-1-P1-12-3, Tokushima, Japan, Mar. 2018.
9.Michiya Kanda, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu :
Resistive Open Defect Detection in 3D ICs with a Comparator of Offset Cancellation Type under Process Variation,
Proc. of International Forum on Advanced Technologies 2018, P1-11-1-P1-11-3, Tokushima, Japan, Mar. 2018.
10.Miyatake Noriko, Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Yokoyama and Tetsuo Tada :
Oscillation Frequency Estimation of Ring Oscillator for Interconnect Tests in 3D Stacked ICs,
Proc. of 2018 RISP International Workshop on Nonlinear Circuits, Communications, 659-662, Mar. 2018.
11.Hanna Soneda, Michiya Kanda, Masaki Hashizume, Hiroyuki Yotsuyanagi and Kung Shyue LU :
Detectable Resistive Open Defects in 3D ICs with Electrical Interconnect Test Circuit Made of Diodes,
Proc. of 2018 RISP International Workshop on Nonlinear Circuits, Communications, 655-658, Mar. 2018.
12.Morito Niseki, Toshinori Hosokawa, Masayoshi Yoshimura, Hiroshi Yamazaki, Masayuki Arai, Hiroyuki Yotsuyanagi and Masaki Hashizume :
A Sequentially Untestable Fault Identification Method Based on State Cube Justification,
the 18th IEEE Workshop on RTL and High Level Testing, 43-46, Taipei, Dec. 2017.
13.Satoshi Hirai, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Reordering Delay Elements in Boundary Scan Circuit with Embedded TDC,
the 18th IEEE Workshop on RTL and High Level Testing, Taipei, Dec. 2017.
14.Shyue-Kung Lu, Shu-Chi Yu, Masaki Hashizume and Hiroyuki Yotsuyanagi :
Fault-Aware Page Address Remapping Techniques for Enhancing Yield and Reliability of Flash Memories,
Proc.of IEEE 26th Asian Test Symposium, 249-254, Taipei, Nov. 2017.
(DOI: 10.1109/ATS.2017.55,   Elsevier: Scopus)
15.Ayumu Kambara, Hiroyuki Yotsuyanagi, Daichi Miyoshi, Masaki Hashizume and Shyue-Kung Lu :
Open Defect Detection with a Built-in Test Circuit by IDDT Appearance Time in CMOS ICs,
Proc.of IEEE 26th Asian Test Symposium, 237-242, Taipei, Nov. 2017.
(DOI: 10.1109/ATS.2017.53,   Elsevier: Scopus)
16.Kouhei Ohtani, Naho Osato, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu :
Resistive Open Defects Detected by Interconnect Testing Based on Charge Volume Injected to 3D ICs,
Proc. of IEEE CPMT Symposium Japan 2017, 231-234, Kyoto, Nov. 2017.
(DOI: 10.1109/ICSJ.2017.8240124,   Elsevier: Scopus)
17.Michiya Kanda, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu :
A Built-in Current Sensor Made of a Comparator of Offset Cancellation Type for Electrical Interconnect Tests of 3D ICs,
Proc. of IEEE CPMT Symposium Japan 2017, 137-138, Kyoto, Nov. 2017.
(DOI: 10.1109/ICSJ.2017.8240131,   Elsevier: Scopus)
18.Michiya Kanda, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu :
A Defective Level Monitor of Open Defects in 3D ICs with a Comparator of Offset Cancellation Type,
2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 1-4, Cambridge, Oct. 2017.
(DOI: 10.1109/DFT.2017.8244446,   Elsevier: Scopus)
19.Yuuya Ohama, Masaki Hashizume, Hiroyuki Yotsuyanagi, Yoshinobu Higami and Hiroshi Takahashi :
On Selection of Adjacent Lines in Test Pattern Generation for Delay Faults Considering Crosstalk Effects,
Proc. of 17th International Symposium on Communications and Information Technologies, 96-100, Cairns, Sep. 2017.
(DOI: 10.1109/ISCIT.2017.8261186,   Elsevier: Scopus)
20.Kouhei Ohtani, Naho Osato, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu :
A Defect Level Monitor of Resistive Open Defect at Interconnects in 3D ICs by Injected Charge Volume,
Proc. of 17th International Symposium on Communications and Information Technologies, 46-50, Cairns, Sep. 2017.
(DOI: 10.1109/ISCIT.2017.8261176,   Elsevier: Scopus)
21.Michiya Kanda, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu :
Capacitive Open Detection in 3D ICs with A Built-in Comparator of Offset Cancellation Type,
IEEE 2017 Taiwan and Japan Conference on Circuits and Systems, Okayama, Aug. 2017.
22.Michiya Kanda, Masaki Hashizume, Akihiro Odoriba, Yohei Kakee, Hiroyuki Yotsuyanagi and Shyue-Kung Lu :
A Built-in Test Circuit Using A Comparator of Offset Cancel Type for Electrical Interconnect Tests of 3D Stacked ICs,
Proc. of International Forum on Advanced Technologies 2017, 233-235, Hualien, Taiwan, Mar. 2017.
23.Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Yokoyama, Tetsuo Tada and Shyue-Kung Lu :
Test Input Vectors for Detecting Stuck-at Faults at Address and Data Buses in 3D Stacked Memory ICs,
Proc. of International Forum on Advanced Technologies 2017, 127-129, Hualien, Taiwan, Mar. 2017.
24.Zheng-Hong Cai, Hiroyuki Yotsuyanagi and Masaki Hashizume :
A Modified PRPG for Test Data Reduction Using BAST Structure,
Proc. RISP International Workshop on Nonlinear Circuit and Signal Processing, 441-444, Guam, Mar. 2017.
25.Fara Ashikin Binti Ali, Yuki Ikiri, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu :
Capacitive Open Defect Detection by Electrical Interconnect Test of 3D ICs without Boundary Scan Flip Flops,
Proc. of the 17th IEEE Workshop on RTL and High Level Testing, 1-2-1-1-2-6, Hiroshima, Nov. 2016.
26.Takumi Kawaguchi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
On Control Circuit and Observation Conditions for Testing Multiple TSVs Using Boundary Scan Circuit with Embedded TDC,
Proc. of the 17th IEEE Workshop on RTL and High Level Testing, 1-3-1-1-3-6, Hiroshima, Nov. 2016.
27.Ali Ashikin Binti Fara, Masaki Hashizume, Yuki Ikiri, Hiroyuki Yotsuyanagi and Shyue-Kung Lu :
Testability for Resistive Open Defects by Electrical Interconnect Test of 3D ICs without Boundary Scan Flip Flops,
Proc. of IEEE CPMT Symposium Japan 2016, 137-138, Kyoto, Nov. 2016.
(DOI: 10.1109/ICSJ.2016.7801302,   Elsevier: Scopus)
28.Kouhei Ohtani, Masaki Hashizume, Daisuke Suga, Hiroyuki Yotsuyanagi and Shyue-Kung Lu :
A Power Supply Circuit for Interconnect Tests Based on Injected Charge Volume of 3D IC,
Proc. of IEEE CPMT Symposium Japan 2016, 139-140, Kyoto, Nov. 2016.
(DOI: 10.1109/ICSJ.2016.7801303,   Elsevier: Scopus)
29.Masaki Hashizume, Akihiro Odoriba, Hiroyuki Yotsuyanagi and Shyue-Kung Lu :
A Built-in Defective Level Monitor of Resistive Open Defects in 3D ICs with Logic Gates,
Proc. of IEEE CPMT Symposium Japan 2016, 99-102, Kyoto, Nov. 2016.
(DOI: 10.1109/ICSJ.2016.7801299,   Elsevier: Scopus)
30.Fara Binti Ali Ashikin, Akihiro Odoriba, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu :
Electrical Tests for Capacitive Open Defects in Assembled PCBs,
Proc. of International Design and Concurrent Engineering Conference 2016, Langkawi, Sep. 2016.
31.Masaki Hashizume, Yudai Shiraishi, Hiroyuki Yotsuyanagi, Hiroshi Yokiyama, Tetsuo Tada and Shyue-Kung Lu :
Electrical Test of Resistive and Capacitive Open Defects at Data Bus in 3D Memory IC,
Proc. of International Design and Concurrent Engineering Conference 2016, Langkawi, Sep. 2016.
32.Kouhei Ohtani, Daisuke Suga, Hiroyuki Yotsuyanagi and Masaki Hashizume :
A Built-in Test Circuit for Injected Charge Tests of Open Defects in CMOS ICs,
Proc. of International Technical Conference on Circuits/Systems, Computers and Communications 2016, 291-294, Okinawa, Jul. 2016.
33.Masashi Okamoto, Akihiro Odoriba, Hiroyuki Yotsuyanagi, Masaki Hashizume and Shyue-Kung Lu :
A Built-in Test Circuit to Monitor Changing Process of Resistive Open Defects in 3D ICs,
Proc. of International Technical Conference on Circuits/Systems, Computers and Communications 2016, 295-298, Okinawa, Jul. 2016.
34.Takumi Miyabe, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu and Zvi Roth :
A Built-in Electrical Test Circuit for Detecting Open Leads in Assembled PCB Circuits with RC Integrator,
Proceedings of International Conference on Electronics Packaging 2016, 451-455, Sapporo, Apr. 2016.
35.Ali Ashikin Binti Fara, Akihiro Odoriba, Masaki Hashizume, Shoichi Umezu, Hiroyuki Yotsuyanagi and Shyue-Kung Lu :
Electrical Tests of Capacitive Open Defects at BGA ICs in Assembled PCB,
Proc. of International Forum on Advanced Technologies 2016, 229-231, Tokushima, Mar. 2016.
36.Yuki Ikiri, Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Yokoyama, Tetsuo Tada and Shyue-Kung Lu :
Die Design for Cost reduction of 3F Stacked Memory ICs,
Proc. of International Forum on Advanced Technologies 2016, 79-80, Tokushima, Mar. 2016.
37.Masaki Hashizume, Yuki Ikiri, Shoichi Umezu, Ali Ashikin Binti Fara, Hiroyuki Yotsuyanagi and Shyue-Kung Lu :
Feasibility of Electrical Test for Open Defects at Address Bus in 3D Memory IC,
Proc. of International Forum on Advanced Technologies 2016, 51-53, Tokushima, Mar. 2016.
38.Masaki Hashizume, Shoichi Umezu, Yuki Ikiri, Hiroyuki Yotsuyanagi and Shyue-Kung Lu :
Test Circuit for Electrical Interconnect Tests of 3D ICs without Boundary Scan Flip Flops,
Proc. of the 16th IEEE Workshop on RTL and High Level Testing, 23-28, Mumbai, Nov. 2015.
39.Masaki Hashizume, Shoichi Umezu, Yuki Ikiri, Ali Ashikin Binti Fara, Hiroyuki Yotsuyanagi and Shyue-Kung Lu :
Electrical Interconnect Test Method of 3D ICs without Boundary Scan Flip Flops,
Proc. of IEEE CPMT Symposium Japan 2015, 136-139, Kyoto, Nov. 2015.
(DOI: 10.1109/ICSJ.2015.7357381,   Elsevier: Scopus)
40.Akihiro Odoriba, Masaki Hashizume, Shoichi Umezu and Hiroyuki Yotsuyanagi :
A Design for Testability with nMOS Switches to Detect Open pins in Assembled PCBs,
Proc. of International Design and Concurrent Engineering Conference 2015, 31-1-31-6, Tokushima, Sep. 2015.
41.Hiroyuki Yotsuyanagi, Akihiro Fujiwara and Masaki Hashizume :
On TSV Array Defect Detection Method Using Two Ring-oscillators Considering Signal Transitions at Adjacent TSVs,
Proc. of IEEE 3D System Integration Conference 2015, TS8.24.1-TS8.24.4, Sep. 2015.
(DOI: 10.1109/3DIC.2015.7334594,   Elsevier: Scopus)
42.Daisuke Suga, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu :
Electrical Interconnect Test Method of 3D ICs by Injected Charge Volume,
Proc. of IEEE 3D System Integration Conference 2015, TS8.19.1-TS8.19.5, Sendai, Sep. 2015.
(DOI: 10.1109/3DIC.2015.7334588,   Elsevier: Scopus)
43.Kosuke Nanbara, Akihiro Odoriba, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu :
Electrical Interconnect Test of 3D ICs Made of Dies without ESD Protection Circuits with a Built-in Test Circuit,
Proc. of IEEE 3D System Integration Conference 2015, TS8.22.1-TS8.22.5, Sendai, Sep. 2015.
(DOI: 10.1109/3DIC.2015.7334592,   Elsevier: Scopus)
44.Masaki Hashizume, Singo Saijyo and Hiroyuki Yotsuyanagi :
Electrically Testable CMOS Image Pixel Circuit,
Proc. of IEEE 2015 European Conference on Circuit Theory and Design, 1-4, Trondheim, Aug. 2015.
(DOI: 10.1109/ECCTD.2015.7300000)
45.Daisuke Suga, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Electrical Test for Open Defects in CMOS ICs by Injected Charge,
Proc. of International Technical Conference on Circuits/Systems, Computers and Communications 2015, 653-656, Seoul, Jun. 2015.
46.Yuki Ikiri, Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Yokoyama, Tetsuo Tada and Shyue-Kung Lu :
Repair Circuit of TSVs in a 3D Stacked Memory IC,
Proc. of International Technical Conference on Circuits/Systems, Computers and Communications 2015, 431-434, Seoul, Jun. 2015.
47.Akihiro Odoriba, Shoichi Umezu, Masaki Hashizume, Hiroyuki Yotsuyanagi, Ali Ashikin Binti Fara and Shyue-Kung Lu :
A Testable Design for Electrical Interconnect Tests of 3D ICs,
Proceedings of 2015 International Conference on Electronics Packaging and iMAPS All Asia Conference, 718-722, Kyoto, Japan, Apr. 2015.
48.Yuki Ikiri, Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Yokoyama, Tetsuo Tada and Shyue-Kung Lu :
Switch Circuit for Repairing Defective TSVs in a 3D Stacked Memory IC,
Proc. of International Forum on Advanced Technologies 2015, 160-161, Tokushima, Mar. 2015.
49.Masaki Hashizume, Shoichi Umezu, Hiroyuki Yotsuyanagi and Shyue-Kung Lu :
A Built-in Supply Current Test Circuit for Electrical Interconnect Tests of 3D ICs,
Proc. of IEEE 3D System Integration Conference 2014, O7-1-O7-6, Kinsdale, Ireland, Dec. 2014.
(DOI: 10.1109/3DIC.2014.7152148)
50.Chih-Chan Fang, Hiroyuki Yotsuyanagi and Masaki Hashizume :
A Test Pattern Matching Method on BAST Architecture for Test Data Reduction by Controlling Scan Shift,
Proc. of the 15th IEEE Workshop on RTL and High Level Testing, 130-134, Nov. 2014.
51.Jun Yamashita, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yoshinobu Higami and Hiroshi Takahashi :
On SAT-based Test Generation for Resistive Open Using Delay Variation Caused by Effect of Adjacent Lines,
Proc. of the 15th IEEE Workshop on RTL and High Level Testing, 49-53, Nov. 2014.
52.Masaki Hashizume, Yudai Shiraishi, Hiroyuki Yotsuyanagi, Hiroshi Yokoyama, Tetsuo Tada and Shyue-Kung Lu :
Threshold Setting of Electrical Test Method for Open Defects at Data Bus in 3D SRAM IC,
Proc. of the 15th IEEE Workshop on RTL and High Level Testing, 64-68, Nov. 2014.
53.Kousuke Nambara, Shoichi Umezu, Hiroyuki Yotsuyanagi, Masaki Hashizume and Shyue-Kung Lu :
Threshold Value Estimation of Electrical Interconnect,
Proc. of IEEE CPMT Symposium Japan 2014, 158-161, Nov. 2014.
(DOI: 10.1109/ICSJ.2014.7009634,   Elsevier: Scopus)
54.Hiroyuki Yotsuyanagi, Hiroki Sakurai and Masaki Hashizume :
Delay Line Embedded in Boundary Scan for Testing TSVs,
Fifth IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, Seattle, Oct. 2014.
55.Masaki Hashizume, Shohei Suenaga and Hiroyuki Yotsuyanagi :
A Built-in Test Circuit for Detecting Open Defects by IDDT Appearance Time in CMOS ICs,
Proc. of the 3rd International Conference on Design and Concurrent Engineering, Sep. 2014.
56.Yudai Shiraishi, Masaki Hashizume, Hiroyuki Yotsuyanagi, Tetsuo Tada and Shyue-Kung Lu :
Electrical Test Method of Open Defects at Data Buses in 3D SRAM IC,
Proc. of International Conference on Electronics Packaging 2014, 235-238, Apr. 2014.
(DOI: 10.1109/ICEP.2014.6826696,   Elsevier: Scopus)
57.Shoichi Umezu, Masaki Hashizume and Hiroyuki Yotsuyanagi :
A Built-in Supply Current Test Circuit for Pin Opens in Assembled PCBs,
Proceedings of International Conference on Electronics Packaging 2014, 227-230, Toyama, Apr. 2014.
(DOI: 10.1109/ICEP.2014.6826694,   Elsevier: Scopus)
58.Akira Ono, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Pin Open Detection of BGA IC by Supply Current Testing,
Proceedings of International Conference on Electronics Packaging 2014, 231-234, Toyama, Japan, Apr. 2014.
(DOI: 10.1109/ICEP.2014.6826695,   Elsevier: Scopus)
59.Shohei Suenaga, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu and Zvi Roth :
DFT for Supply Current Testing to Detect Open Defects at Interconnects in 3D ICs,
Proc. of IEEE Electrical Design of Advanced Packaging & Systems (EDAPS) Symposium, 60-63, Nara, Dec. 2013.
(DOI: 10.1109/EDAPS.2013.6724389)
60.Jun Yamashita, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yoshinobu Higami and Hiroshi Takahashi :
On SAT-based Test Generation for Observing Delay Variation Caused by a Resistive Open Fault and Its Adjacent Lines,
Digest of Papers of the 14-th IEEE Workshop on RTL and High Level Testing, IV.2.F-1-IV.2.F-6, Yilan,Taiwan, Nov. 2013.
61.Akira Ono, Masao Takagi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Supply Current Test Method for Pin Open Defects in Assembled PCB Circuits,
Digest of Papers of the 14-th IEEE Workshop on RTL and High Level Testing, I.3.S-1-I.3.S-4, Yilan,Taiwan, Nov. 2013.
62.Shoichi Umezu, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu and Zvi Roth :
Feasibility of Interconnect Tests of Open Defects in a 3D IC with a Built-in Supply Current Test Circuit,
Digest of Papers of the 14-th IEEE Workshop on RTL and High Level Testing, I.1.F-1-I.1.F-5, Yilan,Taiwan, Nov. 2013.
63.Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Hiroyuki Yotsuyanagi, Masaki Hashizume and K. Kewal Saluja :
Diagnosing Resistive Open Faults Using Small Delay Fault Simulation,
Proc.of IEEE 22th Asian Test Symposium, 79-84, Yilan,Taiwan, Nov. 2013.
(DOI: 10.1109/ATS.2013.23)
64.Masaki Hashizume, Tomoaki Konishi, Hiroyuki Yotsuyanagi and Shyue-Kung Lu :
Testable Design for Electrical Testing of Open Defects at Interconnects in 3D ICs,
Proc.of IEEE 22th Asian Test Symposium, 13-18, Yilan,Taiwan, Nov. 2013.
(DOI: 10.1109/ATS.2013.13)
65.Ei Haraguchi, Masaki Hashizume, Katsuya Manabe, Hiroyuki Yotsuyanagi, Tetsuo Tada, Shyue-Kung Lu and Zvi Roth :
Reduction Method of Number of Electromagnetic Simulation Times for Estimating Output Voltage at Hard Open TSV in 3D IC,
Proc. of IEEE CPMT Symposium Japan(ICSJ2013), 251-254, Kyoto, Nov. 2013.
(DOI: 10.1109/ICSJ.2013.6756128,   Elsevier: Scopus)
66.Shohei Suenaga, Masaki Hashizume, Hiroyuki Yotsuyanagi, Tetsuo Tada and Shyue-Kung Lu :
Built-in IDDT Appearance Time Sensor for Detecting Open Faults in 3D IC,
Proc. of IEEE CPMT Symposium Japan(ICSJ2013), 247-250, Kyoto, Nov. 2013.
(DOI: 10.1109/ICSJ.2013.6756127,   Elsevier: Scopus)
67.Hiroki Sakurai, Hiroyuki Yotsuyanagi, Masanori Nakamura and Masaki Hashizume :
Time-to-Digital Converter Embedded in Boundary-Scan Circuit and Its Application to 3D iC Testing,
International Test Conference 2013, PO30, Anaheim, Sep. 2013.
68.Shoichi Umezu, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu :
Testability of Open Defects at Interconnections in 3D ICs with a Built-in Test Circuit for Supply Current Testing,
International Test Conference 2013, PO29, Anaheim, Sep. 2013.
69.Akira Ono, Hiroyuki Yotsuyanagi, Masao Takagi and Masaki Hashizume :
Open Defect Detection in Assembled PCBs by Supply Current Testing with Electrodes Embedded inside ICs,
Proceedings of ICEP2013, 451-456, Osaka, Japan, Apr. 2013.
70.Masaki Hashizume, Masatake Akutagawa, Shyue-Kung Lu and Hiroyuki Yotsuyanagi :
Electrical Test Method of Open Defects at Bi-directional Interconnects in 3D ICs,
Proceedings of ICEP2013, 13-18, Osaka, Japan, Apr. 2013.
71.(名) Widianto, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Size Reduction of a Built-in Test Circuit for Locating Open Interconnects in 3D ICs,
Proc. of International Conference on Electronics, Information and Communication, 302-303, Bali, Indonesia, Feb. 2013.
72.(名) Widianto, Hiroyuki Yotsuyanagi, Akira Ono, Masao Takagi, Zvi Roth and Masaki Hashizume :
A Built-in Electrical Test Circuit for Interconnect tests in Assembled PCBs,
Proc. of IEEE CPMT Symposium Japan 2012, 201-204, Kyoto, Dec. 2012.
(DOI: 10.1109/ICSJ.2012.6523422)
73.Jun Yamashita, Hiroyuki Yotsuyanagi, Masaki Hashizume and Kozo Kinoshita :
On Detectability Analysis of Open Faults Using SAT-based Test Pattern Generation Considering Adjacent Lines,
Digest of Papers of the 13-th IEEE Workshop on RTL and High Level Testing, 2.1.1-2.1.6, Niigata, Nov. 2012.
74.Masaki Hashizume, Shohei Kondo, Ei Haraguchi, Hiroyuki Yotsuyanagi, Tetsuo Tada and Zvi Roth :
Output Voltage Estimation Method of Hard Open TSV in 3D ICs,
Digest of Papers of the 13-th IEEE Workshop on RTL and High Level Testing, 6.1.1-6.1.5, Niigata, Nov. 2012.
75.Masaki Hashizume, Tomoaki Konishi and Hiroyuki Yotsuyanagi :
Electrical Interconnect Testing of Open Defects in Assembled PCBs Utilizing IEEE 1149.1 Test Mechanism,
International Test Conference 2012, PO1, Anaheim, Nov. 2012.
76.Tomoaki Konishi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
A Built-in Test Circuit for Supply Current Testing of Open Defects at Interconnects in 3D ICs,
Proc. of 4-th Electronics System Integration Technologies Conference(ESTC 2012), PA21.1_1-PA21.1_6, Amsterdam, Sep. 2012.
(DOI: 10.1109/ESTC.2012.6542127)
77.Takahashi Hiroshi, Higami Yoshinobu, Yamazaki Koji, Tsutsumi Toshiyuki, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Test Generation for Resistive Open Faults with Considering Adjacent Lines,
Proc. of 2012 International Technical Conference on Circuits/Systems, Computers and Communications, P-T2-06-1-P-T2-06-4, Sapporo, Jul. 2012.
78.Shohei Suenaga, Hiroyuki Yotsuyanagi and Masaki Hashizume :
A Built-in Sensor for IDDT Testing of CMOS ICs,
Proc. of 2012 International Technical Conference on Circuits/Systems, Computers and Communications, E-M2-05-1-E-M2-05-4, Sapporo, Jul. 2012.
79.Shingo Saijo, Hiroyuki Yotsuyanagi, Masaki Hashizume and Kozo Kinoshita :
Testable Design of CMOS Image Pixel Circuits for Electrical Testing,
Proc. of 2012 International Technical Conference on Circuits/Systems, Computers and Communications, D-W2-04-1-D-W2-04-4, Sapporo, Jul. 2012.
80.Tomoaki Konishi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
An Electrical Test Circuit for Detecting Interconnect Open Defects in 3D ICs,
Proceedings of ICEP2012, 88-93, Tokyo, Japan, Apr. 2012.
81.Ei Haraguchi, Shohei Kondo, Katsuya Manabe, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Output Voltage of a Floating Metal Line Caused by a Neighboring Metal Line Bending at a Right Angle,
Proc. RISP International Workshop on Nonlinear Circuit and Signal Processing, 233-236, Honolulu, Mar. 2012.
82.Yasuhiko Okada, Hiroyuki Yotsuyanagi and Masaki Hashizume :
The Test Vector Compaction Considering Compatible Flip-Flops for BIST-Aided Scan Test,
Proc. RISP International Workshop on Nonlinear Circuit and Signal Processing, 449-452, Honolulu, Mar. 2012.
83.Hiroyuki Makimoto, Hiroyuki Yotsuyanagi and Masaki Hashizume :
On Measuring Timing Slack Using Boundary Scan with Time-to-Digital Converter for Detecting Delay Faults,
Proc. RISP International Workshop on Nonlinear Circuit and Signal Processing, 445-448, Honolulu, Mar. 2012.
84.Tomoaki Konishi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Supply Current Testing of Open Defects at Interconnects in 3D ICs with IEEE 1149.1 Architecture,
International 3D System Integration Conference, 8-2-1-8-2-6, Osaka, Feb. 2012.
(DOI: 10.1109/3DIC.2012.6262968,   Elsevier: Scopus)
85.(名) Widianto, Hiroyuki Yotsuyanagi, Akira Ono, Masao Takagi and Masaki Hashizume :
A Built-in Test Circuit for Open Defects at Interconnects between Dies in 3D ICs,
International 3D System Integration Conference, P-2-31-1-P-2-31-5, Osaka, Feb. 2012.
(DOI: 10.1109/3DIC.2012.6263041,   Elsevier: Scopus)
86.Hiroyuki Yotsuyanagi, Hiroyuki Makimoto and Masaki Hashizume :
A Boundary Scan Circuit with Time-to-Digital Converter for Delay Testing,
Proc. 20th Asian Test Symposium, 539-544, New Delhi, Nov. 2011.
(DOI: 10.1109/ATS.2011.63,   Elsevier: Scopus)
87.Masaki Hashizume, Yutaka Hata, Hiroyuki Yotsuyanagi and Yukiya Miura :
A Supply Current Testable Register String DAC of Decoder Type,
Proc. of 11th International Symposium on Communications and Information Technologies, 58-63, China, Hangzhou, Oct. 2011.
(DOI: 10.1109/ISCIT.2011.6092183)
88.Lee Heejin, Hiroyuki Yotsuyanagi, Sohn Kyungrak and Masaki Hashizume :
Feasibility of Operating Point Estimation in Lighting Circuit with Measured I-V Characteristics of LEDs,
Proc. of 2011 International Technical Conference on Circuits/Systems, Computers and Communications, 1026-1029, Gyeongju, Korea, Jun. 2011.
89.Yoshihiko Miyamori, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Practical Testability of Supply Current Testable DACs of Resistor Type,
Proc. of 2011 International Technical Conference on Circuits/Systems, Computers and Communications, 1015-1018, Gyeongju, Korea, Jun. 2011.
90.Tomoaki Konishi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Feasibility of Electrical Testing for Lead Opens of QFP ICs,
Proc. of 2011 International Technical Conference on Circuits/Systems, Computers and Communications, 688-691, Gyeongju, Korea, Jun. 2011.
91.Shohei Kondo, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Faulty Effect of Soft Open Defect in TSV Caused by Logic Values of Neighboring TSVs,
Proc. of 2011 International Technical Conference on Circuits/Systems, Computers and Communications, 692-695, Gyeongju, Korea, Jun. 2011.
92.Katsuya Manabe, Hiroyuki Yotsuyanagi, Toshiyuki Tsutsumi, Koji Yamazaki, Yoshinobu Higami, Hiroshi Takahashi, Yuzo Takamatsu and Masaki Hashizume :
Estimation of Faulty Effects Caused by a Clack at an Interconnect Line in 90nm ICs,
Proceedings of ICEP2011, 737-742, Nara, Japan, Apr. 2011.
93.Shohei Kondo, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Fault Analysis of Soft Open Defects in TSVs with Electromagnetic Simulator,
Proceedings of ICEP2011, 727-731, Nara, Japan, Apr. 2011.
94.Masaki Hashizume, Yutaka Hata, Hiroyuki Yotsuyanagi and Yukiya Miura :
A Supply Current Testable DAC of Resistor String Type,
Proc. RISP International Workshop on Nonlinear Circuit and Signal Processing, 13-16, TianJin,China, Mar. 2011.
95.Masashi Ishikawa, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Test Data Reduction for BIST-aided Scan Test Using Compatible Flip-flops and Shifting Inverter Code,
Proc. of 19th Asian Test Symposium, 163-166, Shanghai, Dec. 2010.
(DOI: 10.1109/ATS.2010.37)
96.Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
A Method for Diagnosing Resistive Open Faults with Considering Adjacent Lines,
Proc. of 10th International Symposium on Communications and Information Technologies, 609-614, Tokyo, Oct. 2010.
(DOI: 10.1109/ISCIT.2010.5665061)
97.Katsuya Manabe, Yuichi Yamada, Hiroyuki Yotsuyanagi, Toshiyuki Tsutsumi, Koji Yamazaki, Yoshinobu Higami, Hiroshi Takahashi, Yuzo Takamatsu and Masaki Hashizume :
Output Voltage Estimation of a Floating Interconnect Line Caused by a Hard Open in 90nm ICs,
Proc. of 10th International Symposium on Communications and Information Technologies, 603-608, Tokyo, Oct. 2010.
(DOI: 10.1109/ISCIT.2010.5665062)
98.Lee Heejin, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Lighting Circuit Analysis Method with Measured I-V Characteristics of LEDs,
Proc. of 2010 International Technical Conference on Circuits/Systems, Computers and Communications, 1262-1265, Pattaya,Thailand, Jul. 2010.
99.Masaki Hashizume, Shohei Kondo and Hiroyuki Yotsuyanagi :
Possibility of Logical Error Caused by Open Defects in TSVs,
Proc. of 2010 International Technical Conference on Circuits/Systems, Computers and Communications, 907-910, Pattaya,Thailand, Jul. 2010.
100.Masaki Hashizume, Kazuya Nakaminami, Hiroyuki Yotsuyanagi, Yukunori Nakajima and Kozo Kinoshita :
Current-Based Testable Design of Level Shifters in Liquid Crystal Display Drivers,
Proc. of 2010 15th European Test Symposium, 262, Prague, May 2010.
(DOI: 10.1109/ETSYM.2010.5512731)
101.Masaki Hashizume, Kenichi Uchikura, Akira Ono, Hiroyuki Yotsuyanagi and Masao Takagi :
Built-in Test Circuit for Opens at Interconnects between Dies inside SiPs,
Proceedings of ICEP2010, 705-710, Sapporo, Japan, Apr. 2010.
102.Shohei Kondo, Katsuya Manabe, Masao Takagi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Faulty Effects on Logic Signal of a Hard Open Via from Adjacent Ones,
Proceedings of ICEP2010, 711-715, Sapporo, Japan, Apr. 2010.
103.Ryota Kuribayashi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Test Generation for Open Faults Considering the Effects of Adjacent Lines,
10th IEEE Workshop on RTL and High Level Testing (WRTLT09), 61-66, Hong Kong, Nov. 2009.
104.Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
New Class of Tests for Open Faults with Considering Adjacent Lines,
Proc. of 18th Asian Test Symposium, 305-310, Taichung, Taiwan, Nov. 2009.
(DOI: 10.1109/ATS.2009.39)
105.Isao Tsukimoto, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Feasibility of IDDQ Tests for Shorts in Deep Submicron ICs,
Proc. of 2009 International Technical Conference on Circuits/Systems, Computers and Communications, 794-796, Jeju,Korea, Jul. 2009.
106.Toshiyuki Tsutsumi, Yasuyuki Kariya, Masaki Hashizume, Hiroyuki Yotsuyanagi, Koji Yamazaki, Yoshinobu Higami, Hiroshi Takahashi and Yuzo Takamatsu :
Preliminary Analysis of Interconnect Full Open Faults using TEG chips,
Proc. of 2009 International Technical Conference on Circuits/Systems, Computers and Communications, 679-682, Jeju, Korea, Jul. 2009.
107.Masaki Hashizume, Yutaka Hata, Hiroyuki Yotsuyanagi and Yukiya Miura :
Current Testable Design of Resistor String DACs for Short Defects,
Proc. of 2009 International Technical Conference on Circuits/Systems, Computers and Communications, 428-431, Jeju,Korea, Jul. 2009.
108.Akira Ono, Hiroyuki Yotsuyanagi, Masao Takagi and Masaki Hashizume :
Open Lead Detection of QFP ICs Using Logic Gates as Open Sensors,
Proc. of 2009 International Conference on Electronics Packaging, 434-439, Kyoto,Japan, Apr. 2009.
109.Hiroyuki Yotsuyanagi, Masaki Hashizume, Toshiyuki Tsutsumi, Koji Yamazaki, Takashi Aikyo, Yoshinobu Higami, Hiroshi Takahashi and Yuzo Takamatsu :
Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC,
Proc. of 22nd International Conference on VLSI Design, 91-96, New Delhi, India, Jan. 2009.
(DOI: 10.1109/VLSI.Design.2009.60)
110.Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi and Masaki Hashizume :
A Novel Approach for Improving the Quality of Open Fault Diagnosis,
Proc. of 22nd International Conference on VLSI Design, 85-90, New Delhi, India, Jan. 2009.
(DOI: 10.1109/VLSI.Design.2009.53)
111.Masayuki Yamamoto, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Scan Chain Configuration for BIST-aided Scan Test using Compatible Scan Flip-flops,
9th Workshop on RTL and High Level Testing (WRTLT08), 99-104, Sapporo, Nov. 2008.
112.Masaki Hashizume, Akihito Shimoura, Masahiro Ichimiya and Hiroyuki Yotsuyanagi :
Test Circuit for Locating Open Leads of QFP ICs,
IEEE 7-th International Board Test Workshop, Fort Collins, USA, Sep. 2008.
113.Yutaka Hata, Masaki Hashizume, Hiroyuki Yotsuyanagi and Yukiya Miura :
Current Testble Design of Resistor String DACs for Open Defects,
Proc. of 2008 International Technical Conference on Circuits/Systems, Computers and Communications, 1533-1536, Shimonoseki, Japan, Jul. 2008.
114.Akira Ono, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Masao Takagi and Masaki Hashizume :
Open Lead Detection Based on Logical Change Caused by AC Voltage Signal Stimulus,
Proc. of 2008 International Technical Conference on Circuits/Systems, Computers and Communications, 241-244, Shimonoseki,Japan, Jul. 2008.
115.Masaki Hashizume, Yuichi Yamada, Hiroyuki Yotsuyanagi, Toshiyuki Tsutsumi, Koji Yamazaki, Yoshinobu Higami, Hiroshi Takahashi and Yuzo Takamatsu :
Fault Analysis of Interconnect Opens in 90nm ICs with Device Simulator,
Proc. of 2008 International Technical Conference on Circuits/Systems, Computers and Communications, 249-252, Shimonoseki, Japan, Jul. 2008.
116.Akira Ono, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Masao Takagi and Masaki Hashizume :
Test Method for DetectingOpen Leads of Low Voltage LSIs,
Proceedings of ICEP2008, 457-462, Tokyo, Jun. 2008.
117.Masaki Hashizume, Masahiro Ichimiya, Akira Ono and Hiroyuki Yotsuyanagi :
Test Circuit for Vectorless Open Lead Detection of CMOS ICs,
IEEE 6-th International Board Test Workshop, Fort Collins, Oct. 2007.
118.Masaki Hashizume, Yuuki Ogata, Mitsuru Tojo, Masahiro Ichimiya and Hiroyuki Yotsuyanagi :
Interconnect Open Detection by Supply Current Testing under AC Electric Field Application,
IEEE International Workshop on Current and Defect Based Testing, 25-29, Santa Clara, Oct. 2007.
119.Hiroyuki Yotsuyanagi, Takeshi Iihara and Masaki Hashizume :
On SoC Testing Using Multiple Scan Chains with Scan Tree Configurations,
8th Workshop on RTL and High Level Testing (WRTLT07), 151-156, Beijing, Oct. 2007.
120.Masaki Hashizume, Yutaka Hata, Tomomi Nishida, Hiroyuki Yotsuyanagi and Yukiya Miura :
Current Testable Design of Resistor String DACs,
Proc. of 16th Asian Test Symposium, 399-403, Beijing, Oct. 2007.
(DOI: 10.1109/ATS.2007.94)
121.Hiroshi Takahashi, Yoshinobu Higami, Shuhei Kadoyama, Takashi Aikyo, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Clues for Modeling and Diagnosing Open Faults with Considering Adjacent Lines,
Proc. of 16th Asian Test Symposium, 39-44, Beijing, Oct. 2007.
122.Hiroshi Takahashi, Yoshinobu Higami, Toru Kikkawa, Takashi Aikyo, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines,
IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, 243-251, Rome, Italy, Sep. 2007.
(DOI: 10.1109/DFT.2007.11)
123.Ono Akira, Masaki Hashizume, Masahiro Ichimiya and Hiroyuki Yotsuyanagi :
Open Lead Detection of CMOS Logic Circuits by Low Pressure Probing,
Proceedings of ICEP2007, 359-364, Tokyo, Apr. 2007.
124.Eiji Tasaka, Masaki Hashizume, Seiichi Nishimoto, Hiroyuki Yotsuyanagi, Takahiro Oie, Ikuro Morita and Toshihiro Kayahara :
At Speed Testing of Bus Interconnects in Microcomputers,
7th Workshop on RTL and High Level Testing (WRTLT06), 123-127, Fukuoka, Nov. 2006.
125.Hiroyuki Yotsuyanagi, Tomohiko Nagashima and Masaki Hashizume :
Test Time Reduction for Scan Circuits by Selection of a Flip-flop with Hold Operation,
7th Workshop on RTL and High Level Testing (WRTLT06), 81-85, Fukuoka, Nov. 2006.
126.Masato Nakanishi, Masaki Hashizume, Hiroyuki Yotsuyanagi and Yukiya Miura :
A BIC Sensor Capable of Adjusting IDDQ Limit in Tests,
Proc. of 15th Asian Test Symposium, 69-74, Fukuoka, Nov. 2006.
(DOI: 10.1109/ATS.2006.260995)
127.Tojo Mitsuru, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Current Testing of Interconnect Opens between CMOS LSIs Having Scan Cells,
IEEE International Workshop on Current and Defect Based Testing, 39-42, Santa Clara, Oct. 2006.
128.Masaki Hashizume and Hiroyuki Yotsuyanagi :
Test Circuit for Open Lead Detection of CMOS ICs Based on Supply Current,
the IEEE European Board Test Workshop, Southampton, UK, May 2006.
129.Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Open Lead Detection Based on Supply Current of CMOS Logic Circuits by AC Voltage Signal Application,
Proceedings of ICEP2006, 147-152, Tokyo, Apr. 2006.
130.Tomohiko Nagashima, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
Test Time Reduction Method for Scan Design with Clock-Control DFT,
Proc. RISP International Workshop on Nonlinear Circuit and Signal Processing, 441-444, Honolulu, Mar. 2006.
131.Masaki Hashizume, Tomomi Nishida, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Yukiya Miura :
Current Testable Design of Resistor String DACs,
The IEEE International Workshop on Electronic Design, Test and Applications, 197-200, Kuala Lumpur, Malaysia, Jan. 2006.
(DOI: 10.1109/DELTA.2006.28)
132.Tomohiko Nagashima, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
Test Generation for Scan Circuits Using Random Selection of the Operations of Scan Flip-flops,
6th Workshop on RTL and High Level Testing (WRTLT05), 79-83, Harbin, China, Jul. 2005.
133.Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Electric Field for Detecting Open Leads in CMOS Logic Circuits by Supply Current Testing,
Proc. of IEEE International Symposium on Circuits and Systems, 2995-2998, Kobe, May 2005.
(DOI: 10.1109/ISCAS.2005.1465257)
134.Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Vectorless Open Pin Detection Method for CMOS Logic Circuits,
Proc. of International Conference on Electronics Packaging, 391-396, Tokyo, Apr. 2005.
135.Takashi Sakaguchi, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Tetsuo Tada, Takeshi Koyama, Yasuhiro Miyagawa, Seiji Tanaka and Toshihiro Kayahara :
Fail-Safe Evaluation Method for Boiler Control Circuits by Circuit Simulation,
Proc. RISP International Workshop on Nonlinear Circuit and Signal Processing, 395-398, Honolulu, Mar. 2005.
136.Seiichi Nishimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Electrical Detection of Pin Shorts by Supply Current of PIC,
Proc. RISP International Workshop on Nonlinear Circuit and Signal Processing, 171-174, Honolulu, Mar. 2005.
137.Masahiro Ichimiya, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Test Equipment for CMOS Lead Open Detection Based on Supply Current under AC Electric Field Application,
Proc. of the ECWC 10 Conference, P03-5-1-P03-5-5, Anaheim, Feb. 2005.
138.Masaki Hashizume, Daisuke Yoneda, Hiroyuki Yotsuyanagi, Tetsuo Tada, Takeshi Koyama, Ikuro Morita and Takeomi Tamesada :
IDDQ Test Method Based on Wavelet Transformation for Noisy Current Measurement Environment,
Proc. of 13th Asian Test Symposium, 112-117, Kenting, Taiwan, Nov. 2004.
(DOI: 10.1109/ATS.2004.50)
139.Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Test Circuit for CMOS Lead Open Detection by Supply Current Testing under AC Electric Field Application,
Proc. of the 2004 47-th Midwest Symposium on Circuits and Systems, I-557-I-560, Hiroshima, Jul. 2004.
(DOI: 10.1109/MWSCAS.2004.1354051)
140.Takagi Masao, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Tsukimoto Isao and Takeomi Tamesada :
AC Electric Field for Detecting Pin Opens by Supply Current of CMOS ICs,
Proc. of International Conference on Electronics Packaging, 217-222, Tokyo, Apr. 2004.
141.Daisuke Ezaki, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
A Power Supply Circuit Recycling Charge in Adiabatic Dynamic CMOS Logic Circuits,
Proc. of the second IEEE International Workshop on Electronic Design, Test, and Applications, 306-311, Perth, Australia, Jan. 2004.
(DOI: 10.1109/DELTA.2004.10022)
142.Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume and Kozo Kinoshita :
On Configuring Scan Trees to Reduce Scan Shifts based on a Circuit Structure,
Proc. of the second IEEE International Workshop on Electronic Design, Test, and Applications, 269-274, Perth, Australia, Jan. 2004.
(DOI: 10.1109/DELTA.2004.10014)
143.Isao Tsukimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Practical Fault Coverage of Supply Current Tests for Bipolar ICs,
Proc. of the second IEEE International Workshop on Electronic Design, Test, and Applications, 189-194, Perth, Australia, Jan. 2004.
(DOI: 10.1109/DELTA.2004.10035)
144.Masaki Hashizume, Tetsuo Akita, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
CMOS Open Fault Detection by Appearance Time of Switching Supply Current,
Proc. of the second IEEE International Workshop on Electronic Design, Test, and Applications, 183-188, Perth, Australia, Jan. 2004.
(DOI: 10.1109/DELTA.2004.10036)
145.Masaki Hashizume, Teppei Takeda, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura and Kozo Kinoshita :
A BIST Circuit for IDDQ Tests,
Proc. of Twelfth Asian Test Symposium, 390-395, Xi'an, Nov. 2003.
(DOI: 10.1109/ATS.2003.1250843)
146.Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume and Kozo Kinoshita :
Reducing Scan Shifts using Folding Scan Trees,
Proc. of Twelfth Asian Test Symposium, 6-11, Xi'an, Nov. 2003.
(DOI: 10.1109/ATS.2003.1250772)
147.Masaki Hashizume, Makoto Kawajiri, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Testability of Supply Current Test in an AGC Circuit,
Proc. of 2003 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.2, 836-839, Kang-Won Do, Korea, Jul. 2003.
148.Takagi Masao, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Testability of Pin Open in Small Outline Package ICs by Supply Current Test,
Proc. of the 2003 International Technical Conference on Circuits/Systems, Computers and Communications, 832-835, Kang-Won Do, Korea, Jul. 2003.
149.Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Electric Field Application Method Effective for Pin Open Detection Based on Supply Current in CMOS Logic Circuits,
Proc. of International Conference on Electronics Packaging, 75-80, Tokyo, Apr. 2003.
150.Masaki Hashizume, Teruyoshi Matsushima, Takashi Shimamoto, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Akio Sakamoto :
Simplification of Incompletely Specified Machine Based on Genetic Algorithm Implementing Dormant Mechanism,
3rd Workshop on RTL and High Level Testing (WRTLT02), 74-78, Guam, USA, Nov. 2002.
151.Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
Test Time Reduction for IDDQ Testing by Arranging Test Vectors,
Proc. of Eleventh Asian Test Symposium, 423-428, Guam, USA, Nov. 2002.
(DOI: 10.1109/ATS.2002.1181748)
152.Masaki Hashizume, Nobuyuki Inou, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Oscillation Frequency Estimation for Detecting Feedback Bridging Faults,
Proc. of 2002International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 1980-1983, Phuket, Thailand, Jul. 2002.
153.Isao Tsukimoto, Masaki Hashizume, Yukiko Mushiaki, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Testability of Current Testing for Open Faults Undetected by Functional Testing in TTL Combinational Circuits,
Proc. of 2002International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 1972-1975, Phuket, Thailand, Jul. 2002.
154.Masaki Hashizume, Tasaka Eiji, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Toshihiro Kayahara :
Power-off Vectorless Test Method for Pin Opens in CMOS Logic Circuits,
Proc. of International Conference on Electronics Packaging, 416-420, Tokyo, Apr. 2002.
155.Masaki Hashizume, Masashi Sato, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Power Supply Circuit for High Speed Operation of Adiabatic Dynamic CMOS Logic Circuits,
Proc. of the IEEE International Workshop on Electronic Design, Test, and Applications, 459-461, Christchurch, New Zealand, Jan. 2002.
(DOI: 10.1109/DELTA.2002.994673)
156.Hiroyuki Yotsuyanagi, Masaki Hashizume, Taisuke Iwakiri, Masahiro Ichimiya and Takeomi Tamesada :
Random Pattern Testability of the Open Defect Detection Method using Application of Time-variable Electric Field,
Proc. of the IEEE International Workshop on Electronic Design, Test, and Applications, 387-391, Christchurch, New Zealand, Jan. 2002.
(DOI: 10.1109/DELTA.2002.994656)
157.Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
CMOS Open Defect Detection Based on Supply Current in Time-variable Electric Field and Supply Voltage Application,
Proc. of Tenth Asian Test Symposium, 117-122, Kyoto, Nov. 2001.
(DOI: 10.1109/ATS.2001.990269)
158.Teppei Takeda, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Yukiya Miura and Kozo Kinoshita :
IDDQ Sensing Technique for High Speed IDDQ Testing,
Proc. of Tenth Asian Test Symposium, 111-116, Kyoto, Nov. 2001.
(DOI: 10.1109/ATS.2001.990268)
159.Hiroyuki Yotsuyanagi, Shinsuke Hata, Masaki Hashizume and Takeomi Tamesada :
Sequential Redundancy Removal Using Test Generation and Multiple Unreachable States,
Proc. of Tenth Asian Test Symposium, 23-28, Kyoto, Nov. 2001.
(DOI: 10.1109/ATS.2001.990253)
160.Hiroyuki Yotsuyanagi, Masaki Hashizume, Taisuke Iwakiri, Masahiro Ichimiya and Takeomi Tamesada :
Test Pattern for Supply Current Test of Open Defects by Applying Time-variable Electric Field,
Proc. of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 287-295, San Francisco, Oct. 2001.
(DOI: 10.1109/DFTVS.2001.966781,   Elsevier: Scopus)
161.Teppei Takeda, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
A High Speed IDDQ Sensor Circuit,
Proc. of 2001 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.2, 438-441, Tokushima, Jul. 2001.
162.Masaki Hashizume, Eiji Tasaka, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Toshihiro Kayahara :
Fault Simulator for Test Program Generation in Supply Current Tests of Microprocessor Based Boiler Control Circuits,
Proc. of 2001 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 446-449, Tokushima, Jul. 2001.
163.Akihiro Tsuji, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Pin Open Detection Method Based on Supply Current in Time-variable Magnetic Field,
Proc. of 2001 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 438-441, Tokushima, Jul. 2001.
164.Masaki Hashizume, Akihiro Tsuji, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Supply Current Test for Pin Opens in CMOS Logic Circuits,
Proc. of International Conference on Electronics Packaging, 363-368, Tokyo, Apr. 2001.
165.Masaki Hashizume, Masahiro Ichimiya, Hiroshi Hoshika, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
CMOS Open Defect Detection by Supply Current Test,
Proc. of Design, Automation and Test in Europe Conference 2001, 509-513, Munich, Mar. 2001.
(DOI: 10.1109/DATE.2001.915071)
166.Masaki Hashizume, Hiroyuki Yotsuyanagi, Masahiro Ichimiya, Takeomi Tamesada and Masashi Takeda :
High Speed IDDQ Test and Its Testability for Process Variation,
IEEE Asian Test Symposium, 344-349, TAIPEI TAIWAN, Dec. 2000.
(DOI: 10.1109/ATS.2000.893647,   Elsevier: Scopus)
167.Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Masashi Takeda :
Testability Analysis of IDDQ Testing with Large Threshold Value,
IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 367-375, Yamanashi Japan, Oct. 2000.
(DOI: 10.1109/DFTVS.2000.887177,   Elsevier: Scopus)
168.Masashi Sato, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Power Supply Circuits with Small Size for Adiabatic Dynamic CMOS Logic Circuits,
Proc. of 2000 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 179-182, Busan, Jul. 2000.
169.Yukiko Mushiaki, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Practical Fault Coverage of Supply Current Testing for Open Fault in TTL Combinational Circuits,
Proc. of 2000 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 383-386, Busan, Jul. 2000.
170.Takahiro Ohnishi, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
A Test Input Sequence for Test Time Reduction of IDDQ Testing,
Proc. of 2000 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 367-370, Busan, Jul. 2000.
171.Hiroshi Hoshika, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
IDDQ Testable Design of Static CMOS PLAs with Low Power Consumption,
Proc. of 2000 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 351-354, Busan, Jul. 2000.
172.Sou Yamamoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Oscillation Frequency Estimation of Feedback Bridging Faults for Test Circuit Design,
Proc. of 2000 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 343-346, Busan, Jul. 2000.
173.Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
Synthesis for Testability by Adding Transitions of Undefined States to State Transition Tables,
Proc. of 2000 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 355-358, Busan, Jul. 2000.
174.Masaki Hashizume, Hiroshi Hoshika, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
IDDQ Testable Design of Static CMOS PLAs,
IEEE International Workshop on Defect Based Testing, 70-75, Montreal, Apr. 2000.
(DOI: 10.1109/DBT.2000.843693)
175.Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Identification of Feedback Bridging Faults with Oscillation,
IEEE Eighth Asian Test Symposium, 25-30, Shanghai, Nov. 1999.
(DOI: 10.1109/ATS.1999.810725)
176.Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Eiji Tasaka and Toshihiro Kayahara :
Supply Current testing for Bridging Faults in Microprocessor Based Sequence Control Circuits,
Proc. of Electronic Circuits World Convention 8, 31-37, Tokyo, Sep. 1999.
177.Masaki Hashizume, Masashi Sato, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Power Supply Circuit for Adiabatic Dynamic CMOS Logic Circuits,
Proc. of 1999 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 162-165, Niigata, Jul. 1999.
178.Hiroyuki Yotsuyanagi and Kozo Kinoshita :
Undetectable Fault Removal of Sequential Circuits Based on Unreachable States,
Proc. of 16th IEEE VLSI Test Symposium, 176-181, Monterey, Apr. 1998.
(DOI: 10.1109/VTEST.1998.670866)
179.Hiroyuki Yotsuyanagi, Seiji Kajihara and Kozo Kinoshita :
Synthesis for Testability by Redundancy Removal Using Retiming,
Proc. 25th International Symposium on Fault-Tolerant Computing, 33-40, Pasadena, California, USA, Jun. 1995.
(DOI: 10.1109/FTCS.1995.466981)
180.Hiroyuki Yotsuyanagi, Seiji Kajihara and Kozo Kinoshita :
Resynthesis for Sequential Circuits Designed with a Specified Initial State,
Proc. 13th IEEE VLSI Test Symposium, 152-157, Princeton, New Jersey, USA, May 1995.
(DOI: 10.1109/VTEST.1995.512630)

Proceeding of Domestic Conference:

1.Ryoya Ohtsuka, Hiroyuki Yotsuyanagi, Masaki Hashizume and Chia-Yu Yao :
A study on applying a PLL circuit to detect delay faults,
電子情報通信学会総合大会講演論文集, 44, Mar. 2019.
2.Shuya Kikuchi, Soma Shinkai, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Evaluation of the effect of delay variations on small delay testing using boundary scan circuits with embedded TDC,
第33回エレクトロニクス実装学会春季講演大会, 12D1-03-1-12D1-03-3, Mar. 2019.
3.Kosuke Ikeuchi, Michiya Kanda, Satoshi Hirai, Hiroyuki Yotsuyanagi and Masaki Hashizume :
A Test Access Port Controller for Stand-by Mode Electrical Testing with Boundary Scan Flip Flops,
第33回エレクトロニクス実装学会春季講演大会, 12D1-01-1-12D1-01-4, Mar. 2019.
4.Satoshi Hirai, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Test Time Reduction by Separating Delay Lines in Boundary Scan Circuit with Embedded TDC,
IEICE Technical Report, Vol.118, No.335, 119-124, Dec. 2018.
5.Yuta Matsumoto, Hiroyuki Yotsuyanagi, Masaki Hashizume and Shyue-Kung Lu :
Effects of Injection Timing on Open Defect Detectability in Charge Injection Tests of SoCs,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 83, Sep. 2018.
6.Hanna Soneda, Michiya Kanda, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu :
Detectability of Resistive Open Defects in 3D ICs with an Electrical Interconnect Test Circuit Made of Diodes under Process Variation,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 82, Sep. 2018.
7.Shunsuke Shibata, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yoshinobu Higami and Hiroshi Takahashi :
On the effectiveness of the discrimination method for resistive open using signal transitions on adjacent lines against temperature,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 80, Sep. 2018.
8.Noriko Miyatake, Hiroyuki Yotsuyanagi, Hiroshi Yokoyama, Masaki Hashizume and Tetsuo Tada :
Effect of Process Variation on Oscillation Frequency in Interconnect Tests of 3D ICs with a Ring Oscillator,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 81, Sep. 2018.
9.Michiya Kanda, Hiroyuki Yotsuyanagi and Masaki Hashizume :
実装基板回路内抵抗断線のバウンダリスキャンテストによる出荷後検出能力評価,
第28回マイクロエレクトロニクスシンポジウム講演論文集, 185-188, Sep. 2018.
10.Satoshi Hirai, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Reduction of Wire Length by Reordering Delay Elements in Boundary Scan Circuit with Embedded TDC,
IEICE Technical Report, Vol.117, No.444, 13-18, Feb. 2018.
11.Ayumu Kambara, Kouhei Ohtani, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Design of TDC Embedded in Scan FFs for Testing Small Delay Faults,
IEICE Technical Report, Vol.117, No.274, 125-130, Nov. 2017.
12.Michiya Kanda, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu :
Feasibility of Defective Level Monitoring of Open Defects in 3D ICs with a Comparator of Offset Cancellation Type,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 82, Sep. 2017.
13.Masashi Okamoto, Hiroyuki Yotsuyanagi, Masaki Hashizume and Shyue-Kung Lu :
Effect of Process Variation in a Built-in Test Circuit Based on Quiescent Current Flowing through Interconnects of 3D ICs,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 81, Sep. 2017.
14.Noriko Miyatake, Hiroyuki Yotsuyanagi, Hiroshi Yokoyama, Masaki Hashizume and Tetsuo Tada :
Temperature Dependence of Ocsillation Frequency in Interconnect Tests of 3D ICs with a Ring Oscillator,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 80, Sep. 2017.
15.須崎 晴登, Isao Tsukimoto, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Evaluation of Detectability for Soldered LSI with Resistive Open Fault by Supply Current Test Method,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 79, Sep. 2017.
16.Tomohiro Katayama, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yoshinobu Higami and Hiroshi Takahashi :
Evaluation of the Feasibility of Resistive Open Fault Detection by Difference of Path Delay Ranking,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 86, Sep. 2017.
17.Daisuke Yabui, Hiroyuki Yotsuyanagi and Masaki Hashizume :
BC1タイプのバウンダリスキャンテスト回路を用いた実装基板のオンライン配線検査法,
第27回マイクロエレクトロニクスシンポジウム講演論文集, 351-354, Aug. 2017.
18.Ayumu Kambara, Hiroyuki Yotsuyanagi and Masaki Hashizume :
On Fault Coverage by Low Transition Pattern for IDDT-based Open Fault Testing,
電子情報通信学会総合大会講演論文集, 139, Mar. 2017.
19.Kouhei Ohtani, Daisuke Suga, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Test Circuit for Interconnect Tests Based on The Number of Charging Times,
第31回エレクトロニクス実装学会春季講演大会, 62-65, Mar. 2017.
20.Daisuke Yabui, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Online Interconnect Test Method of Assembled PCB Circuits with IEEE 1149.1 Test Circuits,
第31回エレクトロニクス実装学会春季講演大会, 58-61, Mar. 2017.
21.Morito Niseki, Toshinori Hosokawa, Masayoshi Yoshimura, Masayuki Arai, Hiroyuki Yotsuyanagi and Masaki Hashizume :
An Untestable Fault Identification Method for Sequential Circuits Based on SAT Using Unreachable States,
IEICE Technical Report, Vol.116, No.466, 29-34, Feb. 2017.
22.Shingo Kawatsuka, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Design of TDC Embedded in Scan FFs for Testing Small Delay Faults,
IEICE Technical Report, Vol.116, No.331, 105-110, Nov. 2016.
23.Ryosuke Mori, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Calibration of inter-chip delay variation using TDC-embedded boundary scan,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 96, Sep. 2016.
24.Daichi Miyoshi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
An investigation on the effectiveness of detecting un-propagatable open faults using IDDT appearance time sensor,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 95, Sep. 2016.
25.Kazui Fujitani, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Effects of the selection of adjacent lines for assigning logic value and threshold value for fault excitation on open fault test pattern generation time,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 94, Sep. 2016.
26.Kotaro Ise, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yoshinobu Higami and Hiroshi Takahashi :
Effectiveness of discrimination method for resistive open using signal transitions on adjacent lines against defect site at the fault line,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 93, Sep. 2016.
27.Shingo Kawatsuka, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Investigation on effect of variations for delay resolution of scan FFs with embedded TDC,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 92, Sep. 2016.
28.Yohei Kakee, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Experimental Feasibility Analysis of Open Defect Detection with Built-in IDDT Appearance Time Sensor,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 88, Sep. 2016.
29.Kouhei Ohtani, Daisuke Suga, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Open Defect Detection with Electrical Test Circuit Based on Injected Charge Volume,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 87, Sep. 2016.
30.Seiya Tanaka, Isao Tsukimoto, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Voltage for Applying AC Electric Filed from Adjacent Trace to Detect Output Lead Open by Supply Current Test,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 86, Sep. 2016.
31.Akihiro Odoriba, Hiroyuki Yotsuyanagi, Masaki Hashizume and Shyue-Kung Lu :
Feasibilty of Changing Process Monitoring of Capacitive Open Defects in 3D ICs with a Built-in Electrical Test Circuit,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 85, Sep. 2016.
32.Masashi Okamoto, Akihiro Odoriba, Fara Binti Ali Ashikin, Hiroyuki Yotsuyanagi, Masaki Hashizume and Shyue-Kung Lu :
Feasibility of Capacitive Open Defect Detection with a Built-in Electrical Test Circuit Made of Diodes and nMOS Switches,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 84, Sep. 2016.
33.Yuki Ikiri, Kousuke Nanbara, Hiroyuki Yotsuyanagi, Masaki Hashizume and Shyue-Kung Lu :
Threshold Values of Electrical Interconnect Tests with Built-in Test Circuit Made of nMOS Diodes,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 83, Sep. 2016.
34.Fara Ashikin Binti Ali, Shoichi Umizu, Yuki Ikiri, Hiroyuki Yotsuyanagi, Masaki Hashizume and Lu Shyue-Kung :
Electrical Interconnect Test Method of Assembled PCBs without Boundary Scan Flip Flops,
第30回エレクトロニクス実装学会春季講演大会, 195-197, Mar. 2016.
35.Takumi Miyabe, Hiroyuki Yotsuyanagi, Masaki Hashizume and Roth Zvi :
Feasibility of Electrical Test of Opened Leads in Assembled PCBs with Built-in Test Circuit by DC Stimulus,
第30回エレクトロニクス実装学会春季講演大会, 198-200, Mar. 2016.
36.Kazui Fujitani, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yoshinobu Higami and Hiroshi Takahashi :
Reduction of open fault test pattern generation time by selection of adjacent lines for assigning logic value,
IEICE Technical Report, Vol.115, No.449, 13-18, Feb. 2016.
37.Kotaro Ise, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yoshinobu Higami and Hiroshi Takahashi :
On discrimination method of a resistive open using delay variation induced by signal transitions on adjacent lines,
IEICE Technical Report, Vol.115, No.339, 31-36, Dec. 2015.
38.Ryosuke Mori, Hiroyuki Yotsuyanagi and Masaki Hashizume :
A study on multiple path selection conditions in delay testing using design-for-testability circuit,
IEICE Technical Report, Vol.115, No.339, 25-30, Dec. 2015.
39.Seiya Tanaka, Isao Tsukimoto, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Comparison of IDDQ Flowing Time by Voltage Wave-Form for Applying AC Electric Filed on Supply Current Test,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 104, Sep. 2015.
40.Takumi Miyabe, Hiroyuki Yotsuyanagi, Masaki Hashizume and Zvi Roth :
Feasibility of Electrical Interconnect Tests of Hard Open Defects with Built-in Test Circuit by a Triangle Waveform Stimulus,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 103, Sep. 2015.
41.Kousuke Nanbara, Hiroyuki Yotsuyanagi, Masaki Hashizume and Shyue-Kung Lu :
Threshold Values in Electrical Interconnect Tests with Built-in Electrical Test Circuit Made of nMOS Switches,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 102, Sep. 2015.
42.Shunsuke Kajitani, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Testability Analysis of Defects in CMOS Pixel Circuits by Circuit Simulation,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 101, Sep. 2015.
43.Yuki Ikiri, Hiroyuki Yotsuyanagi, Masaki Hashizume, Hiroshi Yokoyama, Tetsuo Tada and Shyue-Kung Lu :
Propagation Delay of TSV Repair Circuit in a 3D Stacked Memory IC,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 100, Sep. 2015.
44.Akihiro Odoriba, Hiroyuki Yotsuyanagi, Masaki Hashizume and Shyue-Kung Lu :
Feasibility of Electrical Tests for Capacitive Interconnect Open Defects in 3D ICs by a Built-in Test Circuit with Diodes,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 99, Sep. 2015.
45.Daisuke Suga, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Feasibility of Supply Current Tests by Amount of Charge Injected into Interconnects between ICs,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 96, Sep. 2015.
46.Daichi Miyoshi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
A study on test pattern ordering for detecting open faults using IDDT appearance time,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 121, Sep. 2015.
47.Motoki Usui, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Test Data Reduction by BAST Architecture using PRPG Feedback Loop Control and Reseeding Circuit,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 120, Sep. 2015.
48.Ryosuke Mori, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Experimental Evaluation of two-path delay measurement using TDC-embedded boundary scan,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 118, Sep. 2015.
49.Takayuki Ishiba, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Improvement of the delay element in delay measurement circuit for testing small delay faults,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 117, Sep. 2015.
50.Kotaro Ise, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yoshinobu Higami and Hiroshi Takahashi :
On the detectability of a resistive open by multivariate analysis using signal transitions on adjacent lines,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 114, Sep. 2015.
51.Kazui Fujitani, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Reduction of candidate adjacent lines for assigning logic value considering parallel length in open fault testing,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 113, Sep. 2015.
52.Youhei Miyamoto, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Evaluation of delay detection capability of VDL in TSV fault detection circuit,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 112, Sep. 2015.
53.Keigo Hamada, Hiroyuki Yotsuyanagi and Masaki Hashizume :
On Fault Detection of TSV by Boundary-Scan for delay faults,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 111, Sep. 2015.
54.Masaki Hashizume, Akihiro Odoriba, Shoichi Umezu, Ashikin Ali Fara Binti, Hiroyuki Yotsuyanagi and Lu Shyue-Kung :
An Electrical Interconnect Test Circuit for Detecting Resistive Open Defects in 3D ICs,
第29回エレクトロニクス実装学会講演大会, 431-432, Mar. 2015.
55.Yudai Shiraishi, Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Yokoyama, Tetsuo Tada and Lu Shyue-Kung :
Threshold Setting Method of Electrical Test Method for Open Defects at a Data Bus in SRAM Circuit,
第29回エレクトロニクス実装学会講演大会, 433-434, Mar. 2015.
56.Youhei Miyamoto, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Investigation of the area reduction of control part and observation part in TSV fault detection circuit,
IEICE Technical Report, Vol.114, No.329, 3-8, Nov. 2014.
57.Shoichi Umezu, Hiroyuki Yotsuyanagi and Masaki Hashizume :
A Built-in Electrical Test Circuit for Soft Open Defects at Interconnects between Dies in 3D ICs,
Proceedings of the Society Conference of IEICE, 85, Sep. 2014.
58.Akihiro Fujiwara, Hiroyuki Yotsuyanagi and Masaki Hashizume :
On defecting a fault in TSV away using double ring oscillators,
Proceedings of the Society Conference of IEICE, 47, Sep. 2014.
59.Hiroki Sakurai, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Verification of Measured Timing Slack Using Time-to-Digital Converter Embedded in Boundary Scan,
Proceedings of the Society Conference of IEICE, 46, Sep. 2014.
60.Ryota Mori, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Test Data Reduction Method for BIST-Aided Scan Test by Controlling Scan Shift,
Proceedings of the Society Conference of IEICE, 45, Sep. 2014.
61.Fang Chih-Chan, Hiroyuki Yotsuyanagi and Masaki Hashizume :
A Test Pattern Matching Method on BAST Architecture to Reduce Bit-flipping and Skipping of Random Patterns,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 114, Sep. 2014.
62.Motoki Usui, Hiroyuki Yotsuyanagi and Masaki Hashizume :
On BAST Scheme Using Loop Control of PRPG for Test Data Reduction,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 113, Sep. 2014.
63.Keigo Hamada, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Design of timing slack measurement circuit for delay fault testing,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 112, Sep. 2014.
64.Takayuki Ishiba, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Delay measurement circuit for testing small delay faults on paths in sequential circuits,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 111, Sep. 2014.
65.Takuma Matsuda, Hiroyuki Yotsuyanagi and Masaki Hashizume :
On Feasibility of Diagnosis Using Test Pattern Generation Method for Via Open Faults by Preventing the Overlap of Assignment to Adjacent Lines,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 110, Sep. 2014.
66.Yuki Himeo, Masatake Akutagawa, Hiroyuki Yotsuyanagi, Masaki Hashizume and Shyue-Kung Lu :
Test Input Reduction of Electrical Tests for Open Defects at Bi-directional Interconnects in PCB circuits,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 103, Sep. 2014.
67.Kousuke Nanbara, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Threshold Values in Electrical Interconnect Tests with Testable Designed ESD Input Protection Circuits,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 102, Sep. 2014.
68.Daisuke Suga, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Feasibility of Supply Current Tests by Amount of Charge Injected into ICs,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 101, Sep. 2014.
69.Shoichi Umezu, Hiroyuki Yotsuyanagi and Masaki Hashizume :
組み込み型電気検査回路によるICのピン浮き検査可能性実験,
第24回マイクロエレクトロニクスシンポジウム論文集, 375-378, Sep. 2014.
70.Shoichi Umezu, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Tests of Capacitive Open Defects between ICs with a Built-in Electrical Test Circuit,
2014 年電子情報通信学会総合大会情報・システム講演論文集1, 125, Mar. 2014.
71.Shoichi Umezu, Hiroyuki Yotsuyanagi and Masaki Hashizume :
A Built-in Current Sensor for Supply Current Tests of Pin Opens in Assembled PCBs,
第28回エレクトロニクス実装学会講演大会, 239-240, Mar. 2014.
72.Masaki Hashizume, Yudai Shiraishi, Hiroyuki Yotsuyanagi and Lu Shyue-Kung :
Electrical Test Method of Open Defects at a Data Bus in SRAM ICs,
第28回エレクトロニクス実装学会講演大会, 237-238, Mar. 2014.
73.Ryota Mori, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Test Data Reduction Method for BIST-Aided Scan Test by Controlling Scan Shift and Partial Reset of Inverter Code,
IEICE Technical Report, Vol.113, No.430, 55-60, Feb. 2014.
74.Hiroki Sakurai, Hiroyuki Yotsuyanagi and Masaki Hashizume :
On Feasibility of Delay Detection by Time-to-Digital Converter Embedded in Boundary-Scan,
IEICE Technical Report, Vol.113, No.430, 7-12, Feb. 2014.
75.Ryo Ando, 月本 功, Masao Takagi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Detection of Open Faults in Solder Ball of BGA LSI by Supply Current Test under AC Electric Field,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 100, Sep. 2013.
76.Shohei Matsukawa, Hiroshi Takahashi, Yoshinobu Higami, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Generating diagnostic tests for resistive open faults,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 125, Sep. 2013.
77.Hiroto Ohguri, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Analysis of Delay Caused by a Resistive Open Considering Signal Direction of Adjacent Lines,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 129, Sep. 2013.
78.Seiki Hanabusa, Masaki Hashizume and Hiroyuki Yotsuyanagi :
Test Data Reduction Method of BIST-Aided Scan Test by Scan Chain Replacement with Design Constraints Scan Chains,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 128, Sep. 2013.
79.Ryota Mori, Masaki Hashizume and Hiroyuki Yotsuyanagi :
Test Data Reduction Method by BIST-Aided Scan Test Using Partial Reset of Inverter Code,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 127, Sep. 2013.
80.Jun Yamashita, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yoshinobu Higami and Hiroshi Takahashi :
A Study on SAT-based Test Generation for Detecting Small Delay Faults Considering Effect of Adjacent Lines,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 126, Sep. 2013.
81.Shoichi Umezu, Masaki Hashizume and Hiroyuki Yotsuyanagi :
Feasibility of Electrical Interconnect Testing with Testable Designed Circuit Preventing from ESD Protection Capability Reduction,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 114, Sep. 2013.
82.Yuki Himeo, Masatake Akutagawa, Hiroyuki Yotsuyanagi, Masaki Hashizume and Shyue-Kung Lu :
Experimental Evaluation of Electrical Test Method for Open Defects at Bi-directional Interconnects,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 113, Sep. 2013.
83.Shohei Suenaga, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Built-in IDDT Appearance Time Sensor Design for Experimental Evaluation,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 112, Sep. 2013.
84.Shingo Saijo, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Feasibility of Electrical Testing for Layout Designed CMOS Sensor Circuit,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 111, Sep. 2013.
85.Takanobu Nimiya, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Delay Test Method Considering Process Variations Using Time-to-Digital Converter Embedded in Boundary Scan,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 106, Sep. 2013.
86.Daisuke Ikeji, Hiroyuki Yotsuyanagi and Masaki Hashizume :
On Feasibility of Delay Test for Multiple Paths Using the Delay-Testable Circuit,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 105, Sep. 2013.
87.Masanori Nakamura, Hiroyuki Yotsuyanagi and Masaki Hashizume :
On Fault Detection of TSV for Control Signal of TSV Test Circuit,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 104, Sep. 2013.
88.Akihiro Fujiwara, Hiroyuki Yotsuyanagi and Masaki Hashizume :
On the proposal and evaluation of ring-oscillator for TSV fault detection considering the effect of adjacent TSVs,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 103, Sep. 2013.
89.Ei Haraguchi, Hiroyuki Yotsuyanagi, Tetsuo Tada, Shyue-Kung Lu, Zvi Roth and Masaki Hashizume :
High Precision Estimation Method of Output Voltage at Hard Opened TSV from Electromagnetic Simulation Results,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 102, Sep. 2013.
90.Takao Kusaka, Hiroyuki Yotsuyanagi and Masaki Hashizume :
On Feasibility of Diagnosis Method of Via-Open Defects on the Same Line using the Coupling Effects,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 101, Sep. 2013.
91.Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Yotsuyanagi, Masaki Hashizume, Koji Yamazaki and Toshiyuki Tsutsumi :
3次元LSIにおけるTSVの故障検査および特性評価に関する研究,
STARCワークショップ2013, Sep. 2013.
92.小野 安季良, 高木 正夫, Hiroyuki Yotsuyanagi and Masaki Hashizume :
パッケージ内に電極を内蔵したICの入力部断線の交流電界印加時の電流テスト,
第27回エレクトロニクス実装学会講演大会, 53-54, Mar. 2013.
93.Masaki Hashizume, Masatake Akutagawa, Lu Shyue-Kung and Hiroyuki Yotsuyanagi :
Electrical Testing of Bidirectional Interconnects with IEEE1149.1 Architecture,
第27回エレクトロニクス実装学会講演大会, 55-56, Mar. 2013.
94.Masanori Nakamura, Hiroyuki Yotsuyanagi and Masaki Hashizume :
On Fault detection method considering adjacent TSVs for a delay fault in TSV,
IEICE Technical Report, Vol.112, No.429, 31-36, Feb. 2013.
95.Hiroto Ohguri, Hiroyuki Yotsuyanagi, Masaki Hashizume, Toshiyuki Tsutsumi, Koji Yamazaki, Yoshinobu Higami and Hiroshi Takahashi :
Characteristic Analysis of Signal Delay for Resistive Open Fault Detection,
IEICE Technical Report, Vol.112, No.429, 25-30, Feb. 2013.
96.Takao Kusaka, Hiroyuki Yotsuyanagi and Masaki Hashizume :
On Identification of Via-Open Defects Using the Coupling Effects of Adjacent Lines,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 153, Sep. 2012.
97.Jun Yamashita, Hiroyuki Yotsuyanagi, Masaki Hashizume and Kozo Kinoshita :
On Test Detectability Analysis Using SAT Solver for Detecting Open Faults Considering Adjacent Line Effects,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 151, Sep. 2012.
98.Daisuke Ikeji, Yuuki Suenobu, Hiroyuki Makimoto, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Derivation of the Additional Delay Required for the Design for Delay Fault Testing Using a STA,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 149, Sep. 2012.
99.Yasuhiko Okada, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Test Data Reduction Method by BIST-Aided Scan Test Using Controlling the Number of Shifting Inverter Code,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 148, Sep. 2012.
100.Shingo Saijo, Hiroyuki Yotsuyanagi, Masaki Hashizume and Kozo Kinoshita :
Feasibility of Electrical Testing for Functional Faults in CMOS Pixel Circuits,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 127, Sep. 2012.
101.Shohei Suenaga, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Necessary Condition of Detecting Open Fault by Built-in Sensor for IDDT Testing,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 129, Sep. 2012.
102.Yoshihiko Miyamori, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Testability by TR Analysis of Supply Current Testable DACs of Resistor String Type,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 130, Sep. 2012.
103.Ei Haraguchi, Shohei Kondo, Hiroyuki Yotsuyanagi, Tetsuo Tada and Masaki Hashizume :
An Estimation Method for Output Voltage of Hard Opened TSV,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 138, Sep. 2012.
104.Hiroto Ohguri, Hiroyuki Yotsuyanagi and Masaki Hashizume :
An Analysis of the Delay Caused by Resistive Open Fault in Congested Routing,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 139, Sep. 2012.
105.Masanori Nakamura, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Fault Analysis of an Open Defect in TSV Array,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 140, Sep. 2012.
106.Takeshi Okumura, 小西 朝陽, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Feasibility of Electrical Testing for Open Defects at Fan-out Branch in PCB Circuits,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 141, Sep. 2012.
107.Masamune Fuji, Hiroyuki Yotsuyanagi, Masaki Hashizume and Tomoaki Konishi :
Testability of Resistive Open Interconnects between ICs by Electrical Testing,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 142, Sep. 2012.
108.Tomoaki Konishi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Experimental Evaluation of Electrical Test Circuit for Open Defects between ICs,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 143, Sep. 2012.
109.Hiroshi Takahashi, Yoshinobu Higami, Toshiyuki Tsutsumi, Koji Yamazaki, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Empirical study for signal integrity-defects,
IEICE Technical Report, Vol.112, No.102, 21-26, Jun. 2012.
110.Jun Yamashita, Kozo Kinoshita, Hiroyuki Yotsuyanagi and Masaki Hashizume :
隣接線を考慮したパターン併合によるオープン故障用テストパターン生成,
電子情報通信学会総合大会講演論文集, D-10-3, Mar. 2012.
111.Tomoaki Konishi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
ESD入力保護能力を低下させないIC間断線の電気的検査用回路,
電子情報通信学会総合大会講演論文集, D-10-4, Mar. 2012.
112.小野 安季良, Hiroyuki Yotsuyanagi, 高木 正夫 and Masaki Hashizume :
QFP ICの半断線故障に対する電流テスト検査法,
第26回エレクトロニクス実装学会講演大会, 168-169, Mar. 2012.
113.Tomoaki Konishi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
IC接続部断線の電気的検査を可能にする組み込み型検査用回路,
第26回エレクトロニクス実装学会講演大会, 166-167, Mar. 2012.
114.Yasuhiko Okada, Hiroyuki Yotsuyanagi and Masaki Hashizume :
A BIST-Aided Scan Test using Shifting Inverter Code and a TPG Method for Test Data Reduction,
IEICE Technical Report, Vol.111, No.325, 133-138, Nov. 2011.
115.Hiroyuki Makimoto, Hiroyuki Yotsuyanagi and Masaki Hashizume :
On the design for testability method using Time to Digital Converter for detecting delay faults,
IEICE Technical Report, Vol.111, No.325, 185-190, Nov. 2011.
116.Takafumi Amo, Hiroyuki Yotsuyanagi and Masaki Hashizume :
X-Filling Method for Reducing Localized IR Drop using Weighted Switching Estimation at Flip-flops,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 143, Sep. 2011.
117.Kenji Gouda, 奥山 奨太郎, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Test Patern Generation for Via-Open Defects Considering Fanout Branches and the Coupling Effects of Adjacent Lines,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 142, Sep. 2011.
118.Takeshi Murakami, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Testability of Capacitive Open Defects in Current Testable Level Shifter by Current Testing,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 141, Sep. 2011.
119.Ryosuke Saeki, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Test Pattern Generation by Focusing on the Number of Don't Cares for Reducing Pattern-dependent Deviation of IDDQ,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 140, Sep. 2011.
120.Katsuya Manabe, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Estimation Model of Output Voltage on a Hard Opened Metal Wire in ICs,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 138, Sep. 2011.
121.西川 大樹, 富田 泰基, 月本 功, Masao Takagi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Affect of Reducing Current Draw on Supply Current Test for Detecting Lead Opens of CMOS LSI,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 130, Sep. 2011.
122.(名) Widianto, Akira Ono, Hiroyuki Yotsuyanagi, Masao Takagi and Masaki Hashizume :
Feasibility of Open Lead Detection with Built-in Current Sensor,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 119, Sep. 2011.
123.Masaki Hashizume, Yutaka Hata, Hiroyuki Yotsuyanagi and 三浦 幸也 :
A Supply Current Testable DAC of Decoder Type,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 118, Sep. 2011.
124.Shohei Kondo, Hiroyuki Yotsuyanagi, Tetsuo Tada and Masaki Hashizume :
Output Voltage of Completely Opened TSV by Electromagnetic Simulation,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 116, Sep. 2011.
125.Tomoaki Konishi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Feasibility of Electrical Testing for Lead Short of QFP ICs,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 117, Sep. 2011.
126.Masaki Hashizume, Yutaka Hata, Hiroyuki Yotsuyanagi and 三浦 幸也 :
抵抗ラダー型DAC 内MOS 短絡の電流テスト容易化設計,
2011年電子情報通信学会総合大会, 121, Mar. 2011.
127.Shohei Kondo, Hiroyuki Yotsuyanagi and Masaki Hashizume :
電磁界シミュレータによるTSVの半断線で生じる故障動作解析,
第25回エレクトロニクス実装学会講演大会, 205-206, Mar. 2011.
128.Masaki Hashizume, Tomoaki Konishi and Hiroyuki Yotsuyanagi :
バウンダリスキャンテスト機構を流用する部品実装基板の電気的テストとその可能性,
第25回エレクトロニクス実装学会講演大会, 201-204, Mar. 2011.
129.Masashi Ishikawa, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Test Data Reduction method for BIST-aided Scan Test Using Shifting Inverter Code,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 102, Sep. 2010.
130.Ryosuke Saeki, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Test Pattern Generation to Reduce the Variations in IDDQ due to Vector Dependencies,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 101, Sep. 2010.
131.Takeshi Murakami, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Testability of Capacitive Open Defects in Level Shifter,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 100, Sep. 2010.
132.Yuichi Ihokura, Hiroyuki Yotsuyanagi, Masaki Hashizume and Kozo Kinoshita :
Feasibility of Electrical Testing for CMOS Pixel Circuits in Prototyped ICs,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 99, Sep. 2010.
133.Shohei Kondo, Hiroyuki Yotsuyanagi, Tetsuo Tada and Masaki Hashizume :
Fault Analysis of Hard Open Vias in ICs by Electromagnetic Simulation,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 98, Sep. 2010.
134.Satoru Okada, Hiroyuki Yotsuyanagi, Masaki Hashizume, Toshiyuki Tsutsumi, Koji Yamazaki, Yoshinobu Higami and Hiroshi Takahashi :
An Analysis of the Signal Delay Caused by a Resistive Open Fault in Interconnect Lines,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 97, Sep. 2010.
135.T. Tomida, Isao Tukimoto, Masao Takagi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Quiescent Supply Current of Deep Submicron Process FPGAs with Lead Open,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 81, Sep. 2010.
136.Shingo Harada, Ogawa Shintaro, Hiroyuki Yotsuyanagi, Hiroyoshi Sei and Masaki Hashizume :
An LED Lighting Control Circuit to Measure Light Wavelength Dependence on Circadian Rhythm in Mice,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 80, Sep. 2010.
137.Masaki Hashizume, 内倉 健一, 小野 安季良, Hiroyuki Yotsuyanagi and 高木 正夫 :
IC内組込型インターコネクトオープン検出回路,
第24回エレクトロニクス実装学会講演大会, 48-49, Mar. 2010.
138.Toshiyuki Tsutsumi, Yasuyuki Kariya, Koji Yamazaki, Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Takahashi, Yoshinobu Higami and Yuzo Takamatsu :
Consideration of Open Faults Model Based on Digital Measurement of TEG Chip,
IEICE Technical Report, Vol.109, No.416, 75-80, Feb. 2010.
139.Hiroshi Takahashi, Yoshinobu Higami, Yuta Shudo, Yuji Takamune, Yuzo Takamatsu, Toshiyuki Tsutsumi, Koji Yamazaki, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Modeling resistive open faults and generating their tests,
IEICE Technical Report, Vol.109, No.416, 19-24, Feb. 2010.
140.Takaaki Nakano, Hiroyuki Yotsuyanagi and Masaki Hashizume :
On multiple scan chains considering localized IR-drop,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 134, Sep. 2009.
141.Ryota Kuribayashi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Test Generation for Open Faults Considering Parallel Wire Lengths of Adjacent Lines,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 133, Sep. 2009.
142.Hiroshi Tarumi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
On Testability Evaluation of Open-via Defects Using Test Pattern for Stuck-at Faults,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 132, Sep. 2009.
143.Katsuya Manabe, Yuichi Yamada, Takuya Yoshida, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Effects on Opened Interconnection Line by Logic Signal in the Layer,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 131, Sep. 2009.
144.Yuichi Yamada, Takuya Yoshida, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Effects on Signal Propagation at Opened Interconnection Line by Shape of Open Defect,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 130, Sep. 2009.
145.Isao Tukimoto, T. Tomida, Masao Takagi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Mesurement of Quiescent Supply Current of 90nm FPGA with Lead Open under AC Electric Field,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 115, Sep. 2009.
146.Kenichi Uchikura, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Masaki Hashizume, Mitsuo Shimotani, Tetsuo Tada and Takeshi Koyama :
Test Probe for Detecting Open Leads of QFP ICs by Current Testing,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 114, Sep. 2009.
147.Yuichi Ihokura, Hiroyuki Yotsuyanagi, Masaki Hashizume, K. Shimada and Kozo Kinoshita :
Feasibility of Electrical Tests for Opens in CMOS Pixel Circuits,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 113, Sep. 2009.
148.Shingo Harada, Tomoyuki Kuroyama, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Current Testability of Opens and Shorts in Operational Amplifier,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 112, Sep. 2009.
149.Kazuya Nakaminami, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yukinori Nakajima and Kozi Kinoshita :
DFT for Current Testing of Level Shifters,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 111, Sep. 2009.
150.Masaki Hashizume, Yutaka Hata, Hiroyuki Yotsuyanagi and Yukiya Miura :
A Current Testable Design of Resistor Ladder DACs,
電子情報通信学会総合大会講演論文集, 155, Mar. 2009.
151.Ryota Kuribayashi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Test Generation for Open Faults with Assignment of the Logic Value to Adjacent Lines,
電子情報通信学会総合大会講演論文集, 157, Mar. 2009.
152.Hiroshi Tarumi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
On Via-open Defects Corresponding to Multiple Stuck-at Faults and Test Generation for These Defects,
電子情報通信学会総合大会講演論文集, 156, Mar. 2009.
153.Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, 小野 安季良 and 高木 正夫 :
QFP ICのリード浮きの電気的検出用回路,
第23回エレクトロニクス実装学会講演大会, 75-77, Mar. 2009.
154.小野 安季良, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, 高木 正夫 and Masaki Hashizume :
Open Lead Detection of Power Supply Leads by Measuring Supply Current of Test Circuit,
Proceedings of the 23rd JIEP Annual Meeting, 79-80, Mar. 2009.
155.Tetsuya Watanabe, Hiroshi Takahashi, Yoshinobu Higami, Toshiyuki Tsutsumi, Koji Yamazaki, Hiroyuki Yotsuyanagi, Masaki Hashizume and Yuzo Takamatsu :
On Tests to Detect Open faults with Considering Adjacent Lines,
IEICE Technical Report, Vol.108, No.431, 37-42, Feb. 2009.
156.Toshiyuki Tsutsumi, Yasuyuki Kariya, Koji Yamazaki, Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Takahashi, Yoshinobu Higami and Yuzo Takamatsu :
Analysis of Open Fault using TEG Chip,
IEICE Technical Report, Vol.108, No.298, 19-24, Nov. 2008.
157.Hiroshi Tarumi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Extraction of open-via defects for test generation,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 129, Sep. 2008.
158.Masayuki Yamamoto, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Test Time Reduction method for BAST Architecture by keeping Inversion Signal,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 128, Sep. 2008.
159.Takaaki Nakano, Hiroyuki Yotsuyanagi and Masaki Hashizume :
On the transitions caused by scan testing considering localized IR-drop,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 127, Sep. 2008.
160.Tatsuya Shimamoto, Eiji Tasaka, Toshihiro Kayahara, Hiroyuki Yotsuyanagi and Masaki Hashizume :
At-Speed Test Program for Bus Faults in PIC16F84A,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 126, Sep. 2008.
161.Keisuke Nishita, Masaki Hashizume and Hiroyuki Yotsuyanagi :
Self-Biased IDDT Appearance Time Sensor,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 111, Sep. 2008.
162.Yutaka Hata, Hiroyuki Yotsuyanagi, Masaki Hashizume and Yukiya Miura :
Testability of A Current Testable DAC,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 110, Sep. 2008.
163.Kazuya Nakaminami, Hiroyuki Yotsuyanagi, Masaki Hashizume and Kozi Kinoshita :
Testability of High Resistive Faults in Level Shifter by Delay Testing,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 109, Sep. 2008.
164.Yuuki Ogata, Hiroyuki Yotsuyanagi and Masaki Hashizume :
An analysis of the signal delay caused by a resistive open defect using TCAD,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 108, Sep. 2008.
165.Yuichi Yamada, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Effects on Signal Integrity by High Resisistive Open on Interconnects,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 107, Sep. 2008.
166.Yuuya Oyamada, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Identification of adjacent lines that cause logic error with an open fault,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 105, Sep. 2008.
167.Kenji Kato, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Faulty Effect of Interconnect Open in 0.35 CMOS IC,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 104, Sep. 2008.
168.Isao Tukimoto, Tohru Ikegami, Masao Takagi, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Effects of Voltage of Nearby Wiring on AC Applied Voltage Needed for Lead Opens Detection of CMOS IC by Supply Current Test under AC Electric Field,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 103, Sep. 2008.
169.M Matsuo, Akira Ono, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Masao Takagi and Masaki Hashizume :
Test Speed of Open Lead Detection Method Based on Output Logical Change of CMOS Logic IC,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 102, Sep. 2008.
170.Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Mitsuo Shimotani, Tetsuo Tada and Takeshi Koyama :
Supply Current Test Circuit for Locating Open Leads of QFP ICs,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 101, Sep. 2008.
171.Kenichi Uchikura, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Prototyping of the Circuit to Detect Lead Open,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 100, Sep. 2008.
172.Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Hiroyuki Yotsuyanagi, Masaki Hashizume and Yuzo Takamatsu :
Improving the Diagnostic Quality of Open Faults,
IEICE Technical Report, Vol.108, No.99, 29-34, Jun. 2008.
173.Akira Ono, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Masao Takagi and Masaki Hashizume :
Open Lead Detection of QFP CPLD IC by Current Testing,
第22回エレクトロニクス実装学会講演大会, 143-144, Mar. 2008.
174.Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Syuhei Kadoyama, Tetsuya Watanabe, Yuzo Takamatsu, Toshiyuki Tsutsumi, Koji Yamazaki, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Fault Diagnosis for Dyinamic Open Faults with Considering Adjacent Lines,
IEICE Technical Report, Vol.107, No.482, 7-12, Feb. 2008.
175.Hiroyuki Yotsuyanagi :
テスト容易化設計/テスト容易化論理合成,
第27回STARCアドバンスト講座テスト技術セミナー, 41-61, Dec. 2007.
176.Yuuki Ogata, Hiroyuki Yotsuyanagi and Masaki Hashizume :
An Analysis of the Voltage at a Floating Line Caused by an Open Defect Using Layout Information,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 108, Sep. 2007.
177.Yuuya Oyamada, Hiroyuki Yotsuyanagi and Masaki Hashizume :
On Test Pattern Generation for Open Fault Detection Using Effects of Multiple Adjacent Signal Lines,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 107, Sep. 2007.
178.Masayuki Yamamoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Kozo Kinoshita :
Testability of Opens in Level Shifter,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 103, Sep. 2007.
179.Yutaka Hata, Junichi Iino, Hiroyuki Yotsuyanagi, Masaki Hashizume and Yukiya Miura :
DFT for Current Testing of Resistor String DACs,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 102, Sep. 2007.
180.Keisuke Nishita, Masaki Hashizume, Hiroyuki Yotsuyanagi and Tetsuo Akita :
A Built-in IDDT Sensor,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 101, Sep. 2007.
181.Tatsuya Shimamoto, Eiji Tasaka, Toshihiro Kayahara, Hiroyuki Yotsuyanagi, Takahiro Oie and Masaki Hashizume :
At-Speed Test Program for Stuck-at Faults at Buses in Z80,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 100, Sep. 2007.
182.Yusaku Kubota, Masaki Hashizume and Hiroyuki Yotsuyanagi :
Analysis of Voltage Change of Open Line Caused by Adjacent Signal Change with TCAD,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 98, Sep. 2007.
183.Tohru Ikegami, Isao Tukimoto, Masao Takagi, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Supply Current of CPLD with Lead Open on 4 Layers Printed Circuit Board with Ground Layer,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 86, Sep. 2007.
184.Kohjiro Yano, Masao Takagi, Isao Tukimoto, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Detecting Output Lead Opens of CMOS LSIs by Supply Current - Change of Voltage Applied to Electrode by Printed Pattern Length,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 85, Sep. 2007.
185.Akihito Onishi, Akira Ono, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Masaki Hashizume and Masao Takagi :
Testability of Supply Current Test Method for Open Lead Detection of QFP CMOS CPLD IC,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 84, Sep. 2007.
186.Tokurou Takigawa, Mitsuru Tojo, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Open Lead Detection of A CMOS IC of 0.35um CMOS process,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 83, Sep. 2007.
187.Mitsuru Tojo, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Open Detection in a CMOS IC by Supply Current Testing under AC Electric Field Application,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 82, Sep. 2007.
188.Masaki Hashizume, Masato Nakanishi, Takeshi Iihara, Hiroyuki Yotsuyanagi, Tetsuo Tada and Takeshi Koyama :
Testabillity of IDDQ Test Method Based on Wavelet Transformation,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 81, Sep. 2007.
189.Masato Nakanishi, Masaki Hashizume, Hiroyuki Yotsuyanagi and Yukiya Miura :
Evaluation of BIC Sensor for Variation of Vth,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 80, Sep. 2007.
190.Akira Ono, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Masaki Hashizume, Isao Tsukimoto and Masao Takagi :
Testability of Supply Current Test Method for Resistive Open Lead Detection,
マイクロエレクトロニクスシンポジウム, 195-198, Sep. 2007.
(CiNii: 40015750812)
191.Masaki Hashizume, Masahiro Ichimiya and Hiroyuki Yotsuyanagi :
Electrical Testing for Open Leads of CMOS QFP ICs,
Proc. of Academic Facilities & Laboratories Poster Program, 41-46, Jun. 2007.
192.Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Yuzo Takamatsu, Masaki Hashizume and Hiroyuki Yotsuyanagi :
A method of locating open faults with considering adjacent nets,
LSIテスティングシンポジウム, 187-192, Nov. 2006.
193.Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Masaki Hashizume and Hiroyuki Yotsuyanagi :
A proposal of a fault model for an open fault and its fault diagnosis,
LSIテスティングシンポジウム, 181-186, Nov. 2006.
194.Yohsuke Misaki, Hiroyuki Yotsuyanagi and Masaki Hashizume :
On Arranging Flip-flops in Scan Trees for Reducing During Test Transitions,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 87, Sep. 2006.
195.Koji Ike, Hiroyuki Yotsuyanagi and Masaki Hashizume :
On the Scan Tree Configuration Method with Routing Constraint,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 86, Sep. 2006.
196.Takeshi Iihara, Hiroyuki Yotsuyanagi and Masaki Hashizume :
On Reducing Testing Time of Multiple-core for Scan Trees,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 85, Sep. 2006.
197.Mitsuru Tojo, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Test Equipment for Supply Current Testing with AC Electric Field Applied,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 72, Sep. 2006.
198.Kohjiro Yano, Masao Takagi, Isao Tukimoto, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Masaki Hashizume :
AC Voltage for Generating Electric Field to Detect Output Lead Opens of CMOS LSIs by Supply Current,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 71, Sep. 2006.
199.Tohru Ikegami, Isao Tukimoto, Masao Takagi, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Effects of Ground Layer on Testability of Lead Open Detection by Supply Current Test under AC Electric Field,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 70, Sep. 2006.
200.Masato Nakanishi, Hiroyuki Yotsuyanagi, Masaki Hashizume and Yukiya Miura :
BIC Sensor Capable of Adjusting IDDQ Limit,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 69, Sep. 2006.
201.Tatsuya Shimizu, Daisuke Ezaki, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Power Saving by Block Partitioning in Dynamic Stop Watch Circuit,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 76, Sep. 2006.
202.Seiichi Nishimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Supply Current Test Program for Pin Short Detection in Z80,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 383, Sep. 2005.
203.Tatsuya Shimizu, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Power Consumption of a Time Varying Power Supplied Dynamic CMOS Adder,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 132, Sep. 2005.
204.Hiroshi Ohmura, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
Testability Evaluation of Open Faults in Consideration of the Voltage of the Adjacent Lines,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 130, Sep. 2005.
205.Katsumi Inoue, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
Design of Scan Tree Configuration of Sequential Circuits using CAD,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 129, Sep. 2005.
206.Koji Ike, Hiroyuki Yotsuyanagi, Masaki Hashizume and Kozo Kinoshita :
On the Arrangement of Flip-Flops in Scan Trees Based on the Fault Effects,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 128, Sep. 2005.
207.Takashi Sakaguchi, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Yukiya Miura :
Torelance of a Built-in IDDQ Test Circuit for Process Variation,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 120, Sep. 2005.
208.Takeshi Iihara, Masaki Hashizume, Tetsuo Tada, Takeshi Koyama, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Testabillity Analysis System of IDDQ Testing Based on Wavelet Transformation,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 119, Sep. 2005.
209.Masao Takagi, Masaki Hashizume, Isao Tukimoto, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Effects on Testability of Logic Value Outputting to Faulty Line in Lead Open Detection by Supply Current Testing,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 118, Sep. 2005.
210.Tatsuya Shimizu, Daisuke Ezaki, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Power Consumption in a Time Varying Power Supplied Dynamic CMOS Timer Circuit,
Proceedings of IEICE Society Conference, 92, Sep. 2005.
211.Seiichi Nishimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
At-Speed Test for Pin Shorts in Z80 by Supply Current Testing,
Proceedings of IEICE Society Conference, 83, Sep. 2005.
212.Takashi Sakaguchi, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Tetsuo Tada, Takeshi Koyama, Yasuhiro Miyagawa, Seiji Tanaka and Toshihiro Kayahara :
Fail-safe Evaluation System for Boiler Control Circuits,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 117, Sep. 2004.
213.Seiichi Nishimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
A Supply Current Test Method for Pin Shorts in PIC ICs,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 116, Sep. 2004.
214.Tetsuo Akita, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Mitsuo Shimotani :
Detection of Open Fault Realized by Transmission Gate with IDDT Disappearance Time Detection Circuit,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 115, Sep. 2004.
215.Daisuke Ezaki, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Operating Speed of Dynamic CMOS Logic Circuit Driven by Supply Voltage of Rectangle Waveform,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 114, Sep. 2004.
216.Junji Murakami, Hiroyuki Yotsuyanagi, Masaki Hashizume and Kozo Kinoshita :
On Reducing the Length of Scan Trees based on the Structure of Circuit,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 113, Sep. 2004.
217.Shintaro Nakayashiki, Masahiro Ichimiya, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
IDDQ Test Circuit with a High Speed External Current Sensor,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 112, Sep. 2004.
218.Tomomi Nishida, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Yukiya Miura :
Testability of Supply Current Testing for DA Converters of Resistor String Type,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 111, Sep. 2004.
219.Masao Takagi, Masaki Hashizume, H. Ishii, Isao Tukimoto, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Pin Open Detection in CMOS TQFP ICs of Low Supply Voltage by Measuring Supply Current under AC Electric Field,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 110, Sep. 2004.
220.Isao Tsukimoto, Masao Takagi, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Deterministic Test Vector Generation of Supply Current Test for Open Faults Undetected by Functional Tests in TTL ICs,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 109, Sep. 2004.
221.Makoto Kawajiri, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Spice Model for Deriving Fault Model of Charge Coupled Devices,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 108, Sep. 2004.
222.Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
Constructing Scan Trees based on a Circuit Structure,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 156, Oct. 2003.
223.Hirokazu Sano, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
Test Generation for Sequential Circuits using Structure Based Partitioning,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 155, Oct. 2003.
224.Daisuke Ezaki, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
A Power Supply Circuit for Dynamic CMOS Logic Circuits,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 139, Oct. 2003.
225.Kenji Kaishita, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Low Power Dynamic CMOS Logic Circuits,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 138, Oct. 2003.
226.Tetsuo Akita, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Mitsuo Shimotani :
IDDT Test Circuit for Detecting Open Faults in CMOS ICs,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 137, Oct. 2003.
227.Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Tetsuo Tada, Takeshi Koyama, Yasuhiro Miyagawa, Seiji Tanaka and Toshihiro Kayahara :
Fail-safe Analysis for a Breaker Valve Circuit in a Boiler Control Circuit,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 136, Oct. 2003.
228.Masao Takagi, Isao Tukimoto, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Pin Open Detection for CMOS Logic ICs of TQFP Package by Measuring Supply Current under AC Electric Field,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 134, Oct. 2003.
229.Daisuke Yoneda, Masaki Hashizume, Tetsuo Tada, Takeshi Koyama, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
IDDQ Testing with Wavelet Transformation Technique,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 133, Oct. 2003.
230.Isao Tsukimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi, Masao Takagi and Takeomi Tamesada :
Practical Fault Coverage of Supply Current Tests for TTL ICs,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 132, Oct. 2003.
231.Makoto Kawajiri, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Testability of Current Tests in an AGC Circuit,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 131, Oct. 2003.
232.Satoshi Matsuda, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
Bridging Faults for Oscillation Frequency to be Estimated for the Fault Detection,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 130, Oct. 2003.
233.Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
Finding Invalid States Using Strongly Unreachable States,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 149, Oct. 2002.
234.Yoshihide Shoji, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
An Improvement of Generating Test Sequence for Test Time Reduction of Current Testing,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 148, Oct. 2002.
235.Hirokazu Sano, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
Reduction of Test Vectors by Focusing on the Number of Detection of Stuck-at Faults in Combinational Circuits,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 147, Oct. 2002.
236.Taisuke Iwakiri, Hiroyuki Yotsuyanagi, Masaki Hashizume, Masahiro Ichimiya and Takeomi Tamesada :
Test Set Compaction for Supply Current Test of Open Defects in CMOS ICs,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 146, Oct. 2002.
237.Daisuke Yoneda, Masaki Hashizume, Takeshi Koyama, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Noise Removal for IDDQ Testing by Wavelet Transformation,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 143, Oct. 2002.
238.Teppei Takeda, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Feasibility of IDDQ Test Time Reduction by Changing Test Input Application Interval,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 142, Oct. 2002.
239.Takao Minami, Masaki Hashizume, Eiji Tasaka, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Toshihiro Kayahara :
A Power-off Test Method for IC Pin Opens,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 141, Oct. 2002.
240.Naoki Maeda, Masahiro Ichimiya, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Feasibility of Pin Open Detection in BGA ICs by Supply Current Test under AC Magnetic Field,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 140, Oct. 2002.
241.Masao Takagi, Isao Tsukimoto, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Pin Open Detection for CMOS Logic ICs of PLCC Package by Measuring Supply Current under AC Electric Field,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 139, Oct. 2002.
242.Isao Tsukimoto, Masaki Hashizume, Yukiko Mushiaki, Hiroyuki Yotsuyanagi, Masao Takagi and Takeomi Tamesada :
Effectivity of Current Testing for Open Faults Undetected by Functional Testing in TTL Combinational Circuits,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 138, Oct. 2002.
243.Takahiro Ohnishi, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
Logic Simulator for Test Input Sequence Evaluation for IDDQ Testing,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 151, Sep. 2001.
244.Taisuke Iwakiri, Hiroyuki Yotsuyanagi, Masaki Hashizume, Masahiro Ichimiya and Takeomi Tamesada :
Evaluation of Stuck-at Pattern and Random Pattern in Supply Current Test of Open Defects,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 150, Sep. 2001.
245.Shinsuke Hata, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
Sequential Redundancy Removal Based on Multiple Unreachable States,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 145, Sep. 2001.
246.Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
Finding Unreachable States with Reducing Search Space,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 144, Sep. 2001.
247.Masaki Hashizume, Masashi Sato, Hiroyuki Yotsuyanagi, Masahiro Ichimiya and Takeomi Tamesada :
Power Consumption in High Speed ADCL Circuits,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 143, Sep. 2001.
248.Teppei Takeda, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Yukiya Miura and Kozo Kinoshita :
IDDQ Test Time Reduction by High Speed Charge for Load Capacitors of Gates,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 142, Sep. 2001.
249.Akihiro Tsuji, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Experimental Evaluation of Pin Open Detection Method with Time-variable Magnetic Field,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 141, Sep. 2001.
250.Yukiko Mushiaki, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Fault Coverages of Supply Current Testing for Open Faults in TTL Circuits,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, No.10-10, 150, Oct. 2000.
251.Akihiro Tsuji, Masahiro Ichimiya, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
A Solder Floating Test by Current Testing with AC Electric Field Applied,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, No.10-9, 149, Oct. 2000.
252.Tomonari Matsuo, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Eiji Tasaka and Toshihiro Kayahara :
Functional Fault Simulator for Bridging Faults in Boiler Control Microcomputer,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, No.10-8, 148, Oct. 2000.
253.Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
Synthesis for Testability by Adding State Transitions and Redundancy Removal,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, No.10-7, 147, Oct. 2000.
254.Takahiro Ohnishi, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
A Test Input Sequence for Test Time Reduction of IDDQ Testing,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, No.10-6, 146, Oct. 2000.
255.Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Open Fault Detection Based on Supply Current in CMOS ICs,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, No.10-5, 145, Oct. 2000.
256.Sou Yamamoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Oscillation Frequency Estimation Method of Feedback Bridging Faults,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, No.9-5, 133, Oct. 2000.
257.Hiroshi Hoshika, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Improvement of IDDQ Testable Design for Static CMOS PLAs,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, No.9-4, 132, Oct. 2000.
258.Kouichi Sugimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
High Speed Current Test Circuit for CMOS Logic Circuits,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, No.9-3, 131, Oct. 2000.
259.Masashi Sato, Masaki Hashizume, Hiroyuki Yotsuyanagi, Masahiro Ichimiya and Takeomi Tamesada :
Power Supply Circuit for High Speed ADCL Circuits,
Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, No.9-2, 130, Oct. 2000.

Et cetera, Workshop:

1.Kohki Taniguchi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Study on the Applicability of ATPG Pattern for DFT Circuit,
IEICE Technical Report, Vol.118, No.335, 131-136, Dec. 2018.
2.Takuto Nishikawa, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Effects of Signal Transition Timing on the Resistive Open Fault Detection by Path Delay Comparison,
DAシンポジウム2018, 154-159, Aug. 2018.
3.Toshiaki Satoh, Hiroyuki Yotsuyanagi and Masaki Hashizume :
On the Effectiveness of ATPG Pattern for Testing Multiple Paths using Delay Fault Testable Scan Design,
第79回FTC研究会資料, Jul. 2018.
4.Tomohiro Katayama, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yoshinobu Higami and Hiroshi Takahashi :
Evaluation of the Feasibility of Resistive Open Fault Detection by Difference of Path Delay Ranking Considering Process Variation,
第78回FTC研究会資料, Jan. 2018.
5.Shunsuke Shibata, Hiroyuki Yotsuyanagi and Masaki Hashizume :
A Study on Line Length and Temperature Dependencies on Discrimination of Resistive Opens using Transition on Adjacent Lines,
第78回FTC研究会資料, Jan. 2018.
6.Soma Shinkai, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Delay Detection Evaluation for Delay Element in Scan Design with Embedded TDC,
第78回FTC研究会資料, Jan. 2018.
7.Kohki Taniguchi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Two-path delay testing by experimental design-for-testability circuit,
第64回機能集積情報システム研究会, Oct. 2017.
8.Shunsuke Shibata, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Delay Analysis of Microbump Defect in 3-D IC,
第64回機能集積情報システム研究会, Oct. 2017.
9.Soma Shinkai, Hiroyuki Yotsuyanagi and Masaki Hashizume :
On Design of Delay Fault Detection Circuit for Design For Testability,
第64回機能集積情報システム研究会, Oct. 2017.
10.Morito Niseki, Toshinori Hosokawa, Masayoshi Yoshimura, Hiroshi Yamazaki, Masayuki Arai, Hiroyuki Yotsuyanagi and Masaki Hashizume :
An Untestable Fault Identification Method for Sequential Circuits Using Unreachable States by Justification of State Cubes,
DAシンポジウム2017, 186-191, Sep. 2017.
11.Shingo Kawatsuka, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Evaluation of Small Delay Fault Detection by TDC Embedded in Scan FFs,
DAシンポジウム2017, 21-26, Aug. 2017.
12.Takumi Kawaguchi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Design of a Control Circuit for Testing TSVs Using Boundary Scan Circuit with Embedded TDC,
DAシンポジウム2017, 15-20, Aug. 2017.
13.Satoshi Hirai, Hiroyuki Yotsuyanagi and Masaki Hashizume :
On design for reducing delay variation in design-for-testability circuit for delay fault,
2017 Taiwan and Japan Conference on Circuits and Systems, Aug. 2017.
14.Makoto Nishikiori, Hiroshi Yamazaki, Toshinori Hosokawa, Masayoshi Yoshimura, Masayuki Arai, Hiroyuki Yotsuyanagi and Masaki Hashizume :
抵抗性オープン故障のテスト生成法の評価,
第76回FTC研究会資料, Jan. 2017.
15.Zheng-Hong Cai, Hiroyuki Yotsuyanagi and Masaki Hashizume :
A Modified PRPG for Test Pattern Generation using BAST structure,
2016 Taiwan and Japan Conference on Circuits and Systems, Aug. 2016.
16.Takumi Kawaguchi, Hiroyuki Yotsuyanagi and Masaki Hashizume :
On test signal generation and observation for testing multiple TSVs using Boundary scan circuit with embedded TDC,
第75回FTC研究会資料, Jul. 2016.
17.Yuuya Ohama, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yoshinobu Higami and Hiroshi Takahashi :
On reduction of signal assignments of adjacent lines for resistive open defect detection based on timing information of signal transition,
第75回FTC研究会資料, Jul. 2016.
18.Kosuke Nanbara, Shoichi Umezu, Hiroyuki Yotsuyanagi, Masaki Hashizume and Shyue-Kung Lu :
Threshold Value Estimation Method for Electrical Interconnect Tests of 3D ICs,
IEEE CASS Shikoku and Malaysia Chapters Joint Seminar, Oct. 2015.
19.Kotaro Ise, Jun Yamashita, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yoshinobu Higami and Hiroshi Takahashi :
On detectability analysis of delay variation caused by a resistive open using signal transitions on adjacent lines,
第72回FTC研究会資料, Jan. 2015.
20.Motoki Usui, Hiroyuki Yotsuyanagi and Masaki Hashizume :
On BAST Code Generation Method by Controlling Feedback in PRPG,
第72回FTC研究会資料, Jan. 2015.
21.Hiroki Sakurai, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Measured Delay Evaluation by Time-to-Digital Converter Embedded in Boundary-scan,
第70回FTC研究会資料, Jan. 2014.
22.Akihiro Fujiwara, Hiroyuki Yotsuyanagi and Masaki Hashizume :
On ring-oscillator structures for TSV fault detection considering the effect of adjacent TSVs,
第70回FTC研究会資料, Jan. 2014.
23.Takanobu Nimiya, Hiroyuki Makimoto, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Multiple path test for detecting delay faults using boundary scan with time-to-digital converter,
第67回FTC研究会資料, Jul. 2012.
24.Hiroyuki Makimoto, Hiroyuki Yotsuyanagi and Masaki Hashizume :
On the design for testability method for detecting delay faults using delay detection circuit,
第65回FTC研究会資料, Jul. 2011.
25.Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Hiroyuki Yotsuyanagi, Masaki Hashizume and Yuzo Takamatsu :
しきい値関数を利用したファンナウト中のオープン故障の診断法,
第63回FTC研究会資料, Jul. 2010.
26.Kenji Gouda, Hiroyuki Yotsuyanagi and Masaki Hashizume :
On Detectability Evaluation of Via-Open Defects Considering the Defect Location and the Coupling Effects of Adjacent Lines,
第63回FTC研究会資料, Jul. 2010.
27.Kenji Katou, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Supply Current Testing of Interconnects Between ICs,
第62回FTC研究会資料, Jan. 2010.
28.Yuuya Oyamada, Hiroyuki Yotsuyanagi and Masaki Hashizume :
On Estimation of Open Fault Effects Considering the Feedback between Adjacent lines,
第58回FTC研究会資料, Jan. 2008.
29.Mitsuru Tojo, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Masaki Hashizume :
Open Detection in CMOS ISs of 0.35μm Process by Supply Current Testing under AS Electric Field Application,
第57回FTC研究会資料, Jul. 2007.
30.Masato Nakanishi, Hiroyuki Yotsuyanagi, Masaki Hashizume and Yukiya Miura :
IDDQ Test Method with a BIC Sensor Tolerating for Process Variations,
第55回FTC研究会資料, Jul. 2006.
31.Seiichi Nishimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
At-Speed Current Test Method of Open and Short Defects at Buses in Microcomputers,
第54回FTC研究会資料, Jan. 2006.
32.Takeshi Iihara, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
On Configuring Scan Trees for Multiple-core Design Based on Circuit Structure,
第54回FTC研究会資料, Jan. 2006.
33.Tomohiko Nagashima, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
On Test Generation for Sequential Circuits Using Limited Scan Operation Considering Initial States,
第52回FTC研究会資料, Jan. 2005.
34.Yoshiteru Fujimoto, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
Extraction of Fault Candidate Areas with Layout Information,
IEICE Technical Report, Vol.104, No.478, 79-84, Dec. 2004.
(CiNii: 110003204332)
35.Junji Murakami, Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume and Kozo Kinoshita :
Configuration of Scan Trees Based on the Structure of Circuit without Test pattern,
第51回FTC研究会資料, Jul. 2004.
36.Daisuke Yoneda, Masaki Hashizume, Hiroyuki Yotsuyanagi, Tetsuo Tada, Takeshi Koyama and Takeomi Tamesada :
IDDQ Testing Based on Wavelet Transform,
第50回FTC研究会資料, Jan. 2004.
37.Hirokazu Sano, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
Test Generation for Sequential Circuits by Logic Simulation using State Partitioning,
IEICE Technical Report, No.DC2003-34, 1-6, Nov. 2003.
(CiNii: 110003173628)
38.Tetsuo Akita, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Built-in Supply Current Sensor Circuit for Detecting Open Faults in CMOS ICs,
第49回FTC研究会資料, Jul. 2003.
39.Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
AC Electric Field Application Method in Supply Current Tests for IC Pin Open Detection,
第48回FTC研究会資料, Jan. 2003.
40.Nobuyuki Inoo, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Oscillation Frequency Estimation for Detecting Feedback Bridging Faults,
第47回FTC研究会資料, Jul. 2002.
41.Takahiro Ohnishi, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
A Test Input Sequence for Test Time Reduction of IDDQ Testing,
第46回FTC研究会資料, Jan. 2002.
42.Akihiro Tsuji, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Pin Open Detection Method Based on Supply Current in Time-variable Magnetic Field,
第45回FTC研究会資料, Jul. 2001.
43.Hiroyuki Yotsuyanagi, Masaki Hashizume, Takeomi Tamesada and Masahiro Ichimiya :
On Detecting CMOS Open Defect by Applying Electric Field and Generating Its Test Pattern,
第44回FTC研究会資料, Jan. 2001.
44.Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada :
Adding Transitions of Undefined States to State Transition Tables for Testability Enhancement,
Workshop on RTL ATPG & DFT (WRTLT00), Sep. 2000.
45.Masaki Hashizume, Masashi Sato, Hiroyuki Yotsuyanagi and Takeomi Tamesada :
Power Supply Circuit for Adiabatic Dymanic CMOS Circuits,
IEICE Technical Report, No.FTS99-6, 1-6, Apr. 1999.
(CiNii: 110003194288)
46.Hiroyuki Yotsuyanagi, Masaki Hashizume, Takeomi Tamesada and Kozo Kinoshita :
A Method for Removing Sequentially Redundant Lines Simultaneously Based on Unreachable States,
IEICE Technical Report, No.FTS98-124, 9-16, Feb. 1999.
(CiNii: 110003194227)

Patent:

1.矢崎 徹, 植松 裕, 池田 康浩, Masaki Hashizume, Hiroyuki Yotsuyanagi and Yuki Ikiri : 半導体装置,及び半導体集積回路, 2017-107547 (May 2017), 2018-206829 (Dec. 2018), 2017-107547 (Dec. 2018).
2.Masaki Hashizume, Masahiro Ichimiya and Hiroyuki Yotsuyanagi : 電子回路の断線故障検査法とその検査容易化回路, 2006-309430 (Nov. 2006), 2008-122338 (May 2008), .
3.口井 敏匡 and Hiroyuki Yotsuyanagi : 半導体集積回路,スキャン回路設計方法,テストパターン生成方法,および,スキャンテスト方法, 2004-225962 (Aug. 2004), 2006-047013 (Feb. 2006), .
4.Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, 茅原 敏広 and 田坂 英司 : ディジタル電子計算機回路の故障検査方法, 009177 (Jan. 1999), .

Grants-in-Aid for Scientific Research (KAKEN Grants Database @ NII.ac.jp)

  • 積層チップ間の故障テスト用信号生成・供給回路設計手法の開発 (Project/Area Number: 18K11218 )
  • ICチップの入出力信号線の弛張発振回路を用いた破断予兆検出法に関する研究 (Project/Area Number: 17H01715 )
  • Design-for-testability circuit for detecting delay faults at interconnects in 3D stacked ICs (Project/Area Number: 15K00079 )
  • Timing failure diagnosis using pre-silicon test and post-silicon test (Project/Area Number: 25330063 )
  • Design and evaluation of design-for-testability circuits for delay faults using built-in time-to-digital converter (Project/Area Number: 24500067 )
  • Search by Researcher Number (90304550)