Tokushima University / Educator and Researcher Directory --- Yotsuyanagi, Hiroyuki

Personal Web Page

https://researchmap.jp/read0054346 (researchmap)

Field of Study

○	Computer Engineering

Subject of Study

○	順序回路の検査容易化に関する研究, 順序論理回路の簡単化に関する研究, 回路設計用CADに関する研究 (Test Technology, VLSI, fault tolerant computing, design automation)

Book / Paper

Book:

1.	浅川毅, Hiroyuki Yotsuyanagi and 土屋秀和 : Verilog HDLで学ぶコンピュータアーキテクチャ, CORONA PUBLISHING CO.,LTD, Feb. 2024.
2.	Kazuo Kondo, Morihiro Kada, Kenji Takahashi, Hiroshi Takahashi, Senling Wang, Shuichi Kameyama, Yoshinobu Higami, Hiroyuki Yotsuyanagi, Masaki Hashizume, Shyue-Kung Lu, Zvi Roth and et .al : Three-Dimensional Integration of Semiconductors --- Processing, Materials, and Applications, --- Trends in 3D Integrated Circuit (3D-IC) Testing Technology ---, Springer, Dec. 2015. (Summary) 低消費電力・高速画像処理などの集積回路に用いられる3次元積層集積回路の製造・テスト・応用についてまとめている． (Link to Publication Site) ● Publication site (DOI): 10.1007/978-3-319-18675-7_8 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-85006710917 (DOI: 10.1007/978-3-319-18675-7_8, Elsevier: Scopus)
3.	LSIテスティング学会, Masaki Hashizume and Hiroyuki Yotsuyanagi : LSIテスティングハンドブック, Ohmsha, Ltd., Nov. 2008. (Summary) LSIの高密度化にともない重要となっているLSIテスティングに関する技術全般を整理して体系化したハンドブック．

Academic Paper (Judged Full Paper):

1.	Hiroyuki Yotsuyanagi : Test Techniques for 3D-ICs, Journal of Japan Institute of Electronics Packaging, Vol.26, No.7, 669-674, 2023. (Link to Publication Site) ● Publication site (DOI): 10.5104/jiep.26.669 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.5104/jiep.26.669 (DOI: 10.5104/jiep.26.669)
2.	Hiroyuki Yotsuyanagi : Design for Testability Methods for Detecting Resistive Opens at Chip Interconnects, Journal of Japan Institute of Electronics Packaging, Vol.26, No.2, 198-202, 2023. (Link to Publication Site) ● Publication site (DOI): 10.5104/jiep.26.198 (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1390013795251431680 ● Search Scopus @ Elsevier (DOI): 10.5104/jiep.26.198 (DOI: 10.5104/jiep.26.198, CiNii: 1390013795251431680)
3.	Hiroyuki Yotsuyanagi and Masaki Hashizume : Delay Testable Design Using Modified Boundary Scan, Journal of Japan Institute of Electronics Packaging, Vol.24, No.7, 663-667, 2021. (Link to Publication Site) ● Publication site (DOI): 10.5104/jiep.24.663 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.5104/jiep.24.663 (DOI: 10.5104/jiep.24.663)
4.	Yuki Ikiri, Fumiya Sako, Masaki Hashizume, Hiroyuki Yotsuyanagi, Lu Shyue-Kung, Yazaki Toru, Ikeda Yasuhiro and Uematsu Yutaka : Open Defect Detection in Assembled Circuit Boards with Built-In Relaxation Oscillators, IEEE Transactions on Components, Packaging, and Manufacturing Technology, Vol.11, No.6, 931-943, 2021. (Summary) In this article, we propose two kinds of electrical interconnect test methods for production tests and field ones of assembled circuit boards, which are performed prior to and after shipping to market, respectively. For these tests, we also propose a built-in test circuit. The methods we followed are based on the oscillation frequency of a relaxation oscillator (ROsc) embedded in integrated circuits (ICs). The frequency is measured as the number of pulse signals within a specified test time. Using the test methods, open defects at the interconnects between IC pins and a printed circuit board (PCB) are detected that are modeled as a resistor, a capacitor, and an open-circuit fault. We examined the detectability of open defects using the process variations afforded by SPICE simulation. The simulation results show that open defects were detected, modeled as a resistor of 45.8 Ω or above, along with open defects modeled as a capacitor and an open-circuit fault using the production test method. In addition, a resistance increase of 1.2 Ω at defect-free interconnects occurred after shipping to market was detected using the field test method. We also prototyped ICs with embedded ROscs and built an experimental circuit made of the ICs on PCBs. Moreover, we experimentally examined whether open defects could be detected. The results show that with the production test method, open defects modeled as a resistor of 10 Ω or above and modeled as a capacitor and an open-circuit fault can be detected. (Link to Publication Site) ● Publication site (DOI): 10.1109/TCPMT.2021.3079159 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-85105881928 (DOI: 10.1109/TCPMT.2021.3079159, Elsevier: Scopus)
5.	Kanda Michiya, Masaki Hashizume, Ali Ashikin Binti Fara, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Open Defect Detection Not Utilizing Boundary Scan Flip-Flops in Assembled Circuit Boards, IEEE Transactions on Components, Packaging, and Manufacturing Technology, Vol.10, No.5, 895-907, 2020. (Summary) An electrical interconnect test method is proposed to detect and locate open defects occurring at interconnects between integrated circuits (ICs) and a printed circuit board. The test method does not utilize boundary scan flip-flops. It is based on a quiescent supply current that is made to flow through an interconnect under test by embedding a test circuit into the ICs. The circuit consists of MOS switches for each input pin of the ICs and its switch control circuit. SPICE simulations are used to examine whether open defects at the interconnects can be detected using this method. The simulation results indicate that the following defective interconnects are detected in addition to defective ones modeled as an open-circuit fault at a test speed of 25 MHz: defective interconnects modeled as a resistor of 150 Ω generating an additional propagation delay of 482 psec and as a capacitor of 4 pF generating an additional propagation delay of 128 psec and no logical changes. Testability of open defects using this test method is also examined experimentally by prototyping an IC in which the test circuit is embedded. The experiments indicate that a resistive interconnect of 150 Ω and a defective one modeled as a capacitor of 2.2 nF can be detected by the test method at a test speed of 0.5 MHz. (Link to Publication Site) ● Publication site (DOI): 10.1109/TCPMT.2020.2973182 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-85084840092 (DOI: 10.1109/TCPMT.2020.2973182, Elsevier: Scopus)
6.	Shyue-Kung Lu, Shu-Chi Yu, Chun-Lung Hsu, Chi-Tien Sun, Masaki Hashizume and Hiroyuki Yotsuyanagi : Fault-Aware Dependability Enhancement Techniques for Flash Memories, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.28, No.3, 634-645, 2020. (Summary) By analyzing the fault behaviors of conventional flash memory fault models, two new concise fault types are proposed: the 1-safe fault and the 0-safe fault. For a 1(0)-safe fault, if logic 1(0) is programmed into the faulty cell, the effect of the fault can be masked. Data shaping (DS) and the page address remapping (PAR) techniques are used to increase the masking probability. DS manipulates the data patterns so that they can be written into the flash pages safely. PAR scrambles the logical-to-physical address mapping for data words and buffer words. Since the effect of a fault is masked for a large proportion of faulty cells, the burden on the error-correction code (ECC) is reduced, as is the number of incorporated redundancies. A novel test-and-repair flow is proposed that uses DS and PAR and corresponding hardware architectures are also developed. A simulator is used to evaluate the hardware overhead, the repair rate, the yield, and the reliability. The experimental results show that these measures are significantly improved with an almost negligible hardware overhead. (Link to Publication Site) ● Publication site (DOI): 10.1109/TVLSI.2019.2957830 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/TVLSI.2019.2957830 (DOI: 10.1109/TVLSI.2019.2957830)
7.	ASHIKIN Fara, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung LU and Zvi ROTH : A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs, IEICE Transactions on Information and Systems, Vol.E101-D, No.8, 2053-2063, 2018. (Summary) A design-for-testability method and an electrical interconnect test method are proposed to detect open defects occurring at interconnects among dies and input/output pins in 3D stacked ICs. As part of the design method, an nMOS and a diode are added to each input interconnect. The test method is based on measuring the quiescent current that is made to flow through an interconnect to be tested. The testability is examined both by SPICE simulation and by experimentation. Our test method enabled the detection of open defects occurring at the newly designed interconnects of dies at experiments test speed of 1MHz. The simulation results reveal that an open defect generating additional delay of 279psec is detectable by the test method at a test speed of 200MHz beside of open defects that generate no logical errors. (Keyword) 3D stacked IC / open defects / design-for-testability / through-silicon via / electrical interconnect test (Link to Publication Site) ● Publication site (DOI): 10.1587/transinf.2018EDP7093 (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1390845712979360256 ● Summary page in Scopus @ Elsevier: 2-s2.0-85052019565 (DOI: 10.1587/transinf.2018EDP7093, CiNii: 1390845712979360256, Elsevier: Scopus)
8.	Hiroyuki Yotsuyanagi, Kotaro Ise, Masaki Hashizume, Yoshinobu Higami and Hiroshi Takahashi : Discrimination of a Resistive Open Using Anomaly Detection of Delay Variation Induced by Transitions on Adjacent Lines, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E100-A, No.12, 2842-2850, 2017. (Summary) Small delay caused by a resistive open is difficult to test since circuit delay varies depending on various factors such as process variations and crosstalk even in fault-free circuits. We consider the problem of discriminating a resistive open by anomaly detection using delay distributions obtained by the effect of various input signals provided to adjacent lines. We examined the circuit delay in a fault-free circuit and a faulty circuit by applying electromagnetic simulator and circuit simulator for a line structure with adjacent lines under consideration of process variations. The effectiveness of the method that discriminates a resistive open is shown for the results obtained by the simulation. (Link to Publication Site) ● Publication site (DOI): 10.1587/transfun.E100.A.2842 (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1390282681291678848 ● Search Scopus @ Elsevier (DOI): 10.1587/transfun.E100.A.2842 (DOI: 10.1587/transfun.E100.A.2842, CiNii: 1390282681291678848)
9.	Fara Alia Ashikin, Akihiro Odoriba, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Electrical Tests for Capacitive Open Defects in Assembled PCBs, Journal of Telecommunication, Electronic and Computer Engineering, Vol.9, No.3-2, 49-52, 2017. (Summary) Nowadays, Ball Grid Array (BGA) becomes a major packaging type due to its high bulk for input/output (I/O) pins. However, there are defects such as voids and cracks occurring between a BGA IC and a PCB which may result in an electrical failure in the circuit. This paper presents electrical tests for capacitive open defects occurring at an interconnection between an IC and a PCB. Feasibility of the electrical test with the test circuit is evaluated by SPICE simulation and experiments. Capacitive open defects occurring at interconnects are detected by the test method. Both simulation and experimental results showed that capacitive open defects generating no logical errors can be detected by the test method at a test speed of 1kHz and 1MHz. (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-85032968134 (Elsevier: Scopus)
10.	Masaki Hashizume, Yudai Shiraishi, Hiroyuki Yotsuyanagi, Hiroshi Yokoyama, Tetsuo Tada and Shyue-Kung Lu : Electrical Test of Resistive and Capacitive Open Defects at Data Bus in 3D Memory IC, Journal of Telecommunication, Electronic and Computer Engineering, Vol.9, No.3-2, 39-42, 2017. (Summary) We propose an electrical test method of resistive and capacitive open defects occurring at data bus lines between dies, and between dies and I/O pins in 3D memory ICs. The test method is based on supply current of an IC. The number of test vectors for a 3D memory IC made of ND memory dies in the test method is 10ND and small. Also, defective interconnects are located by the test method. Feasibility of the tests is examined by some experiments for a circuit made of an SRAM IC on a printed circuit board. The experimental results show that capacitive open defects and resistive open ones whose resistance values are greater than 200 can be detected by the test method. (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-85032895662 (Elsevier: Scopus)
11.	Zheng-Hong Cai, Hiroyuki Yotsuyanagi and Masaki Hashizume : Modified PRPG for Test Data Reduction Using BAST Structure, Journal of Signal Processing, Vol.21, No.4, 125-128, 2017. (Summary) In order to reduce the volume of test data, built-in self test (BIST) and BIST-aided scan test (BAST) techniques have been proposed. To provide the test pattern generated by an automatic test pattern generator (ATPG) using BAST, we enhanced the structure of a pseudorandom pattern generator (PRPG) by inserting MUXes and NOT gates in the linear feedback shift register (LFSR) based on correlations of ATPG patterns. The procedures can achieve about 15 to 56% reduction in the volume of test data for BAST. (Link to Publication Site) ● Publication site (DOI): 10.2299/jsp.21.125 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.2299/jsp.21.125 (DOI: 10.2299/jsp.21.125)
12.	(名) Widiant, Masaki Hashizume, Shohei Suenaga, Hiroyuki Yotsuyanagi, Akira Ono, Shyue-Kung Lu and Zvi Roth : A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs, IEICE Transactions on Information and Systems, Vol.E99-D, No.11, 2723-2733, 2016. (Summary) <p>In this paper, a built-in test circuit for an electrical interconnect test method is proposed to detect an open defect occurring at an interconnect between an IC and a printed circuit board. The test method is based on measuring the supply current of an inverter gate in the test circuit. A time-varying signal is provided to an interconnect as a test signal by the built-in test circuit. In this paper, the test circuit is evaluated by SPICE simulation and by experiments with a prototyping IC. The experimental results reveal that a hard open defect is detectable by the test method in addition to a resistive open defect and a capacitive open one at a test speed of 400 kHz.</p> (Keyword) electrical test / built-in test circuit / open defect / interconnect test / design for testability (Link to Publication Site) ● Publication site (DOI): 10.1587/transinf.2015EDP7273 (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1390282679355793792 ● Search Scopus @ Elsevier (DOI): 10.1587/transinf.2015EDP7273 (DOI: 10.1587/transinf.2015EDP7273, CiNii: 1390282679355793792)
13.	Masaki Hashizume, Yuki Ikiri, Tomoaki Konishi, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Electrical Interconnect Test of Solder Joint Part with Boudary Scan Flip Flops and a Built-in Test Circuit, Journal of Japan Institute of Electronics Packaging, Vol.19, No.3, 161-165, 2016. (Link to Publication Site) ● Publication site (DOI): 10.5104/jiep.19.161 (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1390282679537111680 ● Search Scopus @ Elsevier (DOI): 10.5104/jiep.19.161 (DOI: 10.5104/jiep.19.161, CiNii: 1390282679537111680)
14.	Jun Yamashita, Hiroyuki Yotsuyanagi, Masaki Hashizume and Kozo Kinoshita : SAT-Based Test Generation for Open Faults Using Fault Excitation Caused by Effect of Adjacent Lines, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E96-A, No.12, 2561-2567, 2013. (Summary) Open faults are difficult to test since the voltage at the floating line is unpredictable and depends on the voltage at the adjacent lines. The effect of open faults can be easily excited if a test pattern provides the opposite logic value to most of the adjacent lines. In this paper, we present a procedure to generate as high a quality test as possible. We define the test quality for evaluating the effect of adjacent lines by assigning an opposite logic value to the faulty line. In our proposed test generation method, we utilize the SAT-based ATPG method. We generate test patterns that propagate the faulty effect to primary outputs and assign logic values to adjacent lines opposite that of the faulty line. In order to estimate test quality for open faults, we define the excitation effectiveness Eeff. To reduce the test volume, we utilize the open fault simulation. We calculate the excitation effectiveness by open fault simulation in order to eliminate unnecessary test patterns. The experimental results for the benchmark circuits prove the effectiveness of our procedure. (Keyword) open faults / adjacent lines / test pattern generation / coupling capacitance / SAT-based ATPG (Link to Publication Site) ● Publication site (DOI): 10.1587/transfun.E96.A.2561 (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1390282681288947840 ● Search Scopus @ Elsevier (DOI): 10.1587/transfun.E96.A.2561 (DOI: 10.1587/transfun.E96.A.2561, CiNii: 1390282681288947840)
15.	Masaki Hashizume, Tomoaki Konishi and Hiroyuki Yotsuyanagi : Electrical Testable Design for Open Defects at Logic Signal Lines between Dies in 3D ICs, The Transactions of the Institute of Electronics, Information and Communication Engineers C, Vol.J96-C, No.11, 361-370, 2013. (Summary) 本論文では3次元実装IC内のダイ間の論理信号線に発生する断線の電気テストを可能にする検査用回路とそれを用いたテスト法を提案する.その検査用回路はIEEE1149.1の検査回路を流用するもので,断線の検出と断線配線の特定を可能とするとともに,ESD入力保護回路を変更しないため,その保護能力低下を招かない.本検査用回路によるテスト法の検査能力は回路シミュレーションと,試作ICを用いてプリント配線板上に作製した回路における実験で調査した.その結果,本検査用回路を用いた電気テスト法により完全断線だけでなく,従来のテスト法で見逃す可能性のある抵抗断線,容量断線を検査速度20MHzで検出でき,また断線配線の特定も容易に行えることがわかった. (Keyword) 3D IC / Interconnect Test / electrical test / DfT (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1520853833941357824 (CiNii: 1520853833941357824)
16.	Hiroyuki Yotsuyanagi, Hiroyuki Makimoto, Takanobu Nimiya and Masaki Hashizume : On Detecting Delay Faults Using Time-to-Digital Converter Embedded in Boundary Scan, IEICE Transactions on Information and Systems, Vol.E96-D, No.9, 1986-1993, 2013. (Summary) This paper proposes a method for testing delay faults using a boundary scan circuit in which a time-to-digital converter (TDC) is embedded. The incoming transitions from the other cores or chips are captured at the boundary scan circuit. The TDC circuit is modified to set the initial value for a delay line through which the transition is propagated. The condition for measuring timing slacks of two or more paths is also investigated since the overlap of the signals may occur in the delay line of the TDC in our boundary scan circuit. An experimental IC with the TDC and boundary scan is fabricated and is measured to estimate the delay of some paths measured by the TDC embedded in boundary scan cells. The simulation results for a benchmark circuit with the boundary scan circuit are also shown for the case that timing slacks of multiple paths can be observed even if the signals overlap in the TDC. (Keyword) delay testing / time-to-digital converter / boundary scan / design for testability (Link to Publication Site) ● Publication site (DOI): 10.1587/transinf.E96.D.1986 (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1390282679355091328 ● Search Scopus @ Elsevier (DOI): 10.1587/transinf.E96.D.1986 (DOI: 10.1587/transinf.E96.D.1986, CiNii: 1390282679355091328)
17.	Tomoaki Konishi, Hiroyuki Yotsuyanagi and Masaki Hashizume : Electrical Test Method for Interconnect Open Defects in 3D ICs, Transactions of The Japan Institute of Electronics Packaging, Vol.5, No.1, 26-33, 2012. (Summary) In this paper, an electrical test method is proposed to detect and locate open defects occurring at interconnects between two dies in 3D ICs. The test method utilizes a test architecture based on IEEE 1149.1 standards to provide a test vector to a targeted interconnect. Also, a testable design method for the IC is proposed for our testing. In this paper, testability of the electrical testing is evaluated using a SPICE simulation. The simulation results show that a resistive open defect of 100 Ω can be detected at a test speed of 1 GHz. Also, the test circuit is implemented inside a prototype IC. It is experimentally examined whether open defects between the IC and a printed circuit board can be detected by the test method. They are detected at a speed of 10 MHz by the test method in the experiments. It promises that interconnect open defects in a 3D IC can be detected by the test method per an interconnect at a test speed of at least 10 MHz. (Link to Publication Site) ● Publication site (DOI): 10.5104/jiepeng.5.26 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.5104/jiepeng.5.26 (DOI: 10.5104/jiepeng.5.26)
18.	Masaki Hashizume, Kenji Kato and Hiroyuki Yotsuyanagi : Electrical Testing of Open Defects between IEEE1149.1 Compliant ICs, Journal of Japan Institute of Electronics Packaging, Vol.14, No.2, 99-102, 2011. (Summary) バウンダリスキャンテスト機構を流用し,完全断線,半断線を確実に発見し,また不良発生箇所も容易に特定できるような電気検査法の開発を試みた．ここではその検査法とその検査を可能にする検査容易化設計法を提案するとともに,IC を試作しその IC を用いた実験で検査可能性を明らかにする． (Link to Publication Site) ● Publication site (DOI): 10.5104/jiep.14.99 (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1390282679537197440 ● Summary page in Scopus @ Elsevier: 2-s2.0-84876918191 (DOI: 10.5104/jiep.14.99, CiNii: 1390282679537197440, Elsevier: Scopus)
19.	Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Hiroyuki Yotsuyanagi, Masaki Hashizume and Yuzo Takamatsu : A Method for Locating Open Faults by Using a Fault Extraction Function, The Transactions of the Institute of Electronics, Information and Communication Engineers D, Vol.J93-D, No.11, 2416-2425, 2010. (Summary) 回路の微細化や銅配線の導入により,配線やビアの断線の発生頻度が高まっている.そのため,効率的なオープン故障の診断法の開発の重要性が増してきている.本論文では,完全に断線した信号線の論理値が,隣接信号線の論理値のしきい値関数として表される故障励起関数を提案する.次に,この故障励起関数を利用した単一オープン故障の診断法を提案する.この診断法では,故障励起関数を利用して故障信号線を絞り込み,更に故障信号線上の断線位置の推定を行う.計算機実験による性能評価の結果は,ほとんどの故障回路に対して高速に被疑故障信号線を1箇所に特定できること,及び故障信号線上の断線位置を故障信号線の長さの25%程度まで絞り込むことができることを示している. (Keyword) 故障診断 / オープン故障 / 故障励起関数 / しきい値関数 / パス / フェール情報 (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1520009408686075904 (CiNii: 1520009408686075904)
20.	Hiroyuki Yotsuyanagi, Masaki Hashizume and Masayuki Yamamoto : Scan Chain Ordering to Reduce Test Data for BIST-Aided Scan Test Using Compatible Scan Flip-Flops, IEICE Transactions on Information and Systems, Vol.E93-D, No.1, 10-16, 2010. (Summary) In this paper, the scan chain ordering method for BIST-aided scan test for reducing test data and test application time is proposed. In this work, we utilize the simple LFSR without a phase shifter as PRPG and configure scan chains using the compatible set of flip-flops with considering the correlations among flip-flops in an LFSR. The method can reduce the number of inverter codes required for inverting the bits in PRPG patterns that conflict with ATPG patterns. The experimental results for some benchmark circuits are shown to present the feasibility of our test method. (Keyword) BIST-aided scan test / scan chain ordering / test data reduction / compatible flip-flops / test pattern generation (Link to Publication Site) ● Publication site (DOI): 10.1587/transinf.E93.D.10 (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1390001204379032064 ● Summary page in Scopus @ Elsevier: 2-s2.0-77950211249 (DOI: 10.1587/transinf.E93.D.10, CiNii: 1390001204379032064, Elsevier: Scopus)
21.	小野安季良, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, 高木正夫 and Masaki Hashizume : Open lead detection method by sensing the switching current of CMOS gate on sensing probe, Journal of Japan Institute of Electronics Packaging, Vol.12, No.2, 137-143, 2009. (Summary) We propose a new test method for detecting open leads on ICs. The test method is based on using the supply current of a CMOS gate as an open lead detector; the current flows when an AC voltage signal is provided to a targeted lead with a probe as a stimulus. To evaluate the test method, we examined whether it could detect open leads in SSIs and LSIs. The experimental results confirm that open leads can be detected within 1μsec by providing an AC voltage signal with an amplitude that is 60% of the power supply voltage of the targeted IC. (Keyword) Open Lead / Electrical Test / Supply Current Test / CMOS IC (Link to Publication Site) ● Publication site (DOI): 10.5104/jiep.12.137 (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1390282679536583040 ● Summary page in Scopus @ Elsevier: 2-s2.0-84871269110 (DOI: 10.5104/jiep.12.137, CiNii: 1390282679536583040, Elsevier: Scopus)
22.	高木正夫, Masaki Hashizume, Masahiro Ichimiya and Hiroyuki Yotsuyanagi : Applied AC Voltage for Detecting Open Leads of CMOS LSI by Monitoring Supply Current under AC Electric Field, Journal of Japan Institute of Electronics Packaging, Vol.10, No.3, 219-228, 2007. (Summary) We have proposed a supply current test method for detecting open leads in CMOS ICs. The method is based on the supply current of a circuit made of CMOS ICs, which flows when an AC electric field is supplied from outside the ICs. The electric field is generated by providing AC voltage between electrodes which are placed over the targeted leads and under a targeted PCB. In this paper, we experimentally examine how large an amplitude of AC voltage should be provided between the electrodes to detect open leads in the CPLD LSIs of PLCC, QFP and TQFP packages. The results reveal that the amplitude of the AC voltage needed to enable open leads detection depends on the shape of the package and the logic threshold voltage of the targeted ICs and printed circuit boards used. Also, they show that in some LSIs the required amplitude depends on the output logic level to an open lead. (Keyword) Open Lead / CMOS LSI / Supply Current Test / Electric Field (Link to Publication Site) ● Publication site (DOI): 10.5104/jiep.10.219 (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1520572359685232384 ● Search Scopus @ Elsevier (DOI): 10.5104/jiep.10.219 (DOI: 10.5104/jiep.10.219, CiNii: 1520572359685232384)
23.	Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume and Kozo Kinoshita : Reducing Scan Shifts Using Configurations of Compatible and Folding Scan Trees, Journal of Electronic Testing - Theory and Applications, Vol.21, No.6, 613-620, 2005. (Summary) In this paper, a new method for reducing scan shifts is presented. Scan design is one of the most popular designs for test method for sequential circuits. However, for circuits with many flip-flops, it requires a long test application time and high test-data volume. Our new scan method utilizes two configurations of scan chains, a folding scan tree and a fully compatible scan tree to alleviate these problems. It is observed that uncompacted test patterns typically contain a large fraction of don't care values. This property is exploited in the fully compatible scan tree to reduce scan shifts without degrading fault coverage. Then, a folding scan tree is configured to further reduce the length of scan chain and scan shifts. Experimental results on benchmark circuits show that this scan method can significantly reduce scan shifts. (Keyword) scan tree / design for testability / logic testing / sequential circuit (Link to Publication Site) ● Publication site (DOI): 10.1007/s10836-005-2719-2 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1007/s10836-005-2719-2 (DOI: 10.1007/s10836-005-2719-2)
24.	月本功, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : ばらつきを有するICで構成したTTL回路の電源電流による統計的断線故障検出法, Journal of Japan Institute of Electronics Packaging, Vol.8, No.3, 199-207, 2005. (Summary) In this paper, a supply-current test method is proposed for detecting open faults in logic circuits made of TTL ICs on printed circuit boards. This method is applicable even if there is any variation of the supply current among the ICs used. In this method, variation of the supply current in a logic circuit is modeled as a Gaussian distribution and a statistical analysis method with level of significance is used for fault detection. In this paper, the fault coverage of the test method is evaluated experimentally. In the experimental evaluation, test input vectors of the supply-current test method are generated for detecting single open faults of signal lines in ISCAS-85 benchmark circuits made of TTL SSIs. The results show that more open faults can be detected by this test method than by a functional test method if the deviation (ς/μ) of the supply current in each SSI used is smaller than 1.1%. (Keyword) Open / Supply Current Test / TTL (Link to Publication Site) ● Publication site (DOI): 10.5104/jiep.8.199 (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1520853834658646016 ● Search Scopus @ Elsevier (DOI): 10.5104/jiep.8.199 (DOI: 10.5104/jiep.8.199, CiNii: 1520853834658646016)
25.	Masaki Hashizume, Teruyoshi Matsushima, Takashi Shimamoto, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Akio Sakamoto : Genetic State Reduction Method of Incompletely Specified Machines, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E87-A, No.6, 1555-1563, 2004. (Summary) A new state reduction method of incompletely specified sequential machines is proposed in this paper. The method is based on a genetic algorithm implementing a dormant mechanism. MCNC benchmark machines are simplified by using this method to evaluate the method. The experimental results show that machines of almost the same number of states as the minimum ones can be derived by this method. (Keyword) incompletely specified machine / maximal compatible set / state reduction (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1574231877208281344 ● Summary page in Scopus @ Elsevier: 2-s2.0-3042693560 (CiNii: 1574231877208281344, Elsevier: Scopus)
26.	Masao Takagi, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Lead Open Detection Based on Supply Current of CMOS LSIs, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E87-A, No.6, 1330-1337, 2004. (Summary) In this paper, a test method is proposed to detect lead opens in CMOS LSIs. The test method is based on supply current which flows when test input vectors and AC electric field are provided from the outside of the ICs. Also, an application method of the test input vectors is proposed in this paper. It is shown experimentally that lead opens of SSIs and LSIs will be detected by providing each of the test input vectors per the period of AC electric field applied. (Keyword) lead open / CMOS LSI / supply current test / electric field (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1572261552371298560 ● Summary page in Scopus @ Elsevier: 2-s2.0-3042543542 (CiNii: 1572261552371298560, Elsevier: Scopus)
27.	Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Test Sequence Generation for Test Time Reduction of IDDQ Testing, IEICE Transactions on Information and Systems, Vol.E87-D, No.3, 537-543, 2004. (Summary) In this paper, test time reduction for IDDQ testing is discussed. Although IDDQ testing is known to be effective to detect faults in CMOS circuit, test time of IDDQ testing is larger than that of logic testing since supply current is measured after a circuit is in its quiescent state. It is shown by simulation that test time of IDDQ test mostly depends on switching current. A procedure to modify test vectors and a procedure to arrange test vectors are presented for reducing the test time of IDDQ testing. A test sequence is modified such that switching current quickly disappears. The procedure utilizes a unit delay model to estimate the time of the last transition of logic value from L to H in a circuit. Experimental results for benchmark circuits show the effectiveness of the procedure. (Keyword) IDDQ testing / bridging faults / switching current / supply current test / CMOS circuits (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1570009752557232384 ● Summary page in Scopus @ Elsevier: 2-s2.0-1642322367 (CiNii: 1570009752557232384, Elsevier: Scopus)
28.	Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Identification and Frequency Estimation of Feedback Bridging Faults Generating Logical Oscillation in CMOS Circuits, IEICE Transactions on Information and Systems, Vol.E87-D, No.3, 571-579, 2004. (Summary) When a feedback bridging fault occurs in a combinational circuit and it is activated, logical oscillation may occur in the circuit. In this paper, some electrical conditions are proposed to identify whether a feedback bridging fault occurs logical oscillation. Also, it is proposed how to estimate the oscillation frequency. They are based on piece linearized models and do not require circuit simulation of large size of circuits. They are evaluated by some experiments. In the experiments, all of the feedback bridging faults occurring logical oscillation are identified. Also, oscillation frequencies larger than the ones obtained by SPICE simulation are derived by the proposed estimation method in the experiments. It promises us that the methods will be used for identifying such bridging faults and estimating the oscillation frequencies. (Keyword) feedback bridging fault / combinational circuit / logical oscillation (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1571980077394203904 ● Summary page in Scopus @ Elsevier: 2-s2.0-1642388921 (CiNii: 1571980077394203904, Elsevier: Scopus)
29.	Hiroyuki Yotsuyanagi, Taisuke Iwakiri, Masaki Hashizume and Takeomi Tamesada : Test Pattern Generation for CMOS Open Defect Detection by Supply Current Testing under AC Electric Field, IEICE Transactions on Information and Systems, Vol.E86-D, No.12, 2666-2673, 2003. (Summary) In this paper, supply current testing for detecting open defects in CMOS circuits is discussed. It is known that open defects cause unpredictable faulty effects and are difficult to be detected. In our test method, an AC electric field is applied during testing. The voltage at a floating node caused by an open defect is varied by the applied electric field and then the defect can be detected. The test pattern generation procedure for open defects is proposed and is applied to benchmark circuits. The experimental results shows that the number of test vectors for opens are much smaller than that for stuck-at faults. The experimental evaluation for an LSI chip is also shown to present the feasibility of our test method. (Keyword) open defects / supply current test / CMOS circuits / electric field (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1573668927254908928 ● Summary page in Scopus @ Elsevier: 2-s2.0-0842332030 (CiNii: 1573668927254908928, Elsevier: Scopus)
30.	Masaki Hashizume, 田坂英司, Hiroyuki Yotsuyanagi, Takeomi Tamesada, 茅原敏広, Ikuro Morita and Takahiro Oie : CMOSマイクロコンピュータ回路の電源電流によるブリッジ故障検出法, Journal of Japan Institute of Electronics Packaging, Vol.6, No.7, 564-572, 2003. (Summary) A new supply current test method is proposed for bridging faults in CMOS microprocessor based circuits which are implemented circuit boards with discrete ICs. The method is based on supply current of a circuit under test, which flows when a test program is executed. A commercial microcomputer circuit is tested by the proposed method. In the tests, 98.7% of the bridging faults between two neighboring pins in the circuit are detected within 326 msec. It promises us that the method can be used in production tests of microprocessor based circuits. Also, it is sown that the test program can be developed by means of timing charts in data sheets of the microprocessor. (Keyword) Bridging Fault / Microcomputer / Supply Current Testing (Link to Publication Site) ● Publication site (DOI): 10.5104/jiep.6.564 (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1520290884709986560 ● Search Scopus @ Elsevier (DOI): 10.5104/jiep.6.564 (DOI: 10.5104/jiep.6.564, CiNii: 1520290884709986560)
31.	Masahiro Ichimiya, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : A Test Circuit for Pin Shorts Generating Oscillation in CMOS Logic Circuits, The Transactions of the Institute of Electronics, Information and Communication Engineers D-I, Vol.J86-D-I, No.6, 402-411, 2003. (Summary) CMOS論理ICをプリント配線板上にはんだ付けする際，ICピン短絡故障が発生する可能性がある．その故障励起時に，故障発生箇所に論理発振が生じる場合がある．その論理発振を生じる故障を論理回路に流れる電源電流によって検出するための検査法とその検査回路を本論文では提案している．実際にその検査回路を試作し，故障励起時に論理発振を生じる故障がその検査回路で検出できることを実験により明らかにしている． (Keyword) ICピン短絡故障 / 検査回路 / CMOS論理回路 / フィードバックブリッジ故障 / 電流テスト (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1520572357417353088 (CiNii: 1520572357417353088)
32.	Masahiro Ichimiya, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Pin Open Detection for CMOS Logic ICs by Measuring Supply Current under AC Electric Field, Journal of Japan Institute of Electronics Packaging, Vol.6, No.2, 140-146, 2003. (Summary) A new test method is proposed in this paper for detecting pin opens in CMOS logic circuits fabricated on printed circuit boards, which are caused by missing solder and so on. In our test method, supply current of an IC is measured with AC electric filed applied outside of CMOS ICs. When any pin opens do not occur in the IC, only quiescent supply current will flow. If a pin open occurs, large supply current change will be generated. The proposed test method uses this property for detecting pin opens. In this paper, the feasibility of the test method is evaluated by some experiments. Also, the test input vectors are proposed for this test method. (Keyword) Current Testing / Pin Open / CMOS Logic Circuit / Electric Field (Link to Publication Site) ● Publication site (DOI): 10.5104/jiep.6.140 (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1520853834658559360 ● Search Scopus @ Elsevier (DOI): 10.5104/jiep.6.140 (DOI: 10.5104/jiep.6.140, CiNii: 1520853834658559360)
33.	Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : CMOS Open Defect Detection by Supply Current Measurement under Time-Variable Electric Field Supply, IEICE Transactions on Information and Systems, Vol.E85-D, No.10, 1542-1550, 2002. (Summary) In this paper, a new test method is proposed for detecting open defects in CMOS logic ICs. The method is based on supply current of ICs generated by supplying time-variable supply voltage and electric field from the outside of the ICs. Also, test input vectors for the test method are proposed and it is shown that they can be generated more easily than functional test methods based on stuck-at fault models. The feasibility of the test is examined by some experiments. The empirical results promise us that by using the method, open defects in CMOS ICs can be detected. (Keyword) open defect / CMOS / supply current test / electric field (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1574231876981112832 ● Summary page in Scopus @ Elsevier: 2-s2.0-0036825554 (CiNii: 1574231876981112832, Elsevier: Scopus)
34.	Masaki Hashizume, Teppei Takeda, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Yukiya Miura and Kozo Kinoshita : IDDQ Test Time Reduction by High Speed Charging of Load Capacitors of CMOS Logic Gates, IEICE Transactions on Information and Systems, Vol.E85-D, No.10, 1534-1541, 2002. (Summary) In this paper, a useful technique is proposed for realizing high speed IDDQ tests. By using the technique, load capacitors of the CMOS logic gates can be charged quickly, whose output logic values change from L to H by applying a test input vector to a circuit under test. The technique is applied to built-in I_<DDQ> sensor design and external I_<DDQ> sensor design. It is shown experimentally that high speed IDDQ tests can be realized by using the technique. (Keyword) IDDQ sensor / CMOS / IDDQ test / bridging fault (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1570854177260582912 ● Summary page in Scopus @ Elsevier: 2-s2.0-0036825934 (CiNii: 1570854177260582912, Elsevier: Scopus)
35.	Masaki Hashizume, Hiroshi Hoshika, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Testable Static CMOS PLA for IDDQ Testing, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E84-A, No.6, 1488-1495, 2001. (Summary) A new IDDQ tastable design method is proposed for static CMOS PLA circuits. A testable PLA circuit of NOR-NOR type is designed using this method. It is shown that all bridging faults in NOR planes of the tastable designed PLA circuit can be detected by IDDQ testing with 4 sets of test input vectors. The test input vectors are independent of the logical functions to be realized in the PLA circuit. PLA circuits are designed using this method so that the quiescent supply current generated when they are tested will be zero. Thus, high resolution of IDDQ tests for the PLA circuits can be obtained by using the testable design method. Results of IDDQ tests of PLA circuits designed using this testable design method confirm not that the expected output can be generated from the circuits but that the circuits are fabricated without bridging faults in NOR planes. Since bridging faults often occur in state-of-the-art IC fabrication, the testable design is indispensable for realizing highly reliable logic systems. (Keyword) static PLA / testable design / IDDQ test / bridging fault (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1571135652357071360 ● Summary page in Scopus @ Elsevier: 2-s2.0-0035367034 (CiNii: 1571135652357071360, Elsevier: Scopus)
36.	Hiroyuki Yotsuyanagi and Kozo Kinoshita : Finding Unreachable States of Sequential Circuits, Technology Reports of the Osaka University, Vol.49, No.2344, 49-55, 1999. (Summary) Some states in a sequential circuit can not be reached by any input sequence. A state is said to be unreachable if it has no transition from any other state. A test generator wastes a time if it tries to bring a state of a circuit to an unreachable state. Therefore the information about unreachable states in the circuit is useful for reducing test generation time. We have reported that obtaining strongly unreachable states, which is a part of unreachable states, is useful to simplify the sequential circuit. In this paper, we present a procedure to identify strongly unreachable states for the circuit which is described by the gate-level and whose state transition table is not given. The input functions of flip-flops are used to identify the invalid combination of state values. Since the procedure to identify unreachable states requires large memory for the circuits with many flip-flops, we also present a procedure to partition the set of flip-flops in order to restrict the number of flip-flops. Experimental results for benchmark sequential circuits show the effectiveness of the proposed procedure.
37.	Hiroyuki Yotsuyanagi, Seiji Kajihara and Kozo Kinoshita : A Redundancy Removal Method for Sequential Circuits Based on Unreachable States, The Transactions of the Institute of Electronics, Information and Communication Engineers D-I, Vol.J81-D-I, No.2, 204-212, 1998. (Summary) 縮退故障の存在する論理回路の出力系列が正常回路の出力系列と等しくなるとき, 故障に対応する信号線を除去することで回路を簡単化できる.故障に対応する信号線が除去できるとき, その故障は除去可能であると言う.本論文では除去可能な縮退故障の一部を容易に求める手法を提案する.提案手法ではいかなる状態からも遷移させることのできない到達不能状態に基づいて検出不能故障を求め, その状態が故障回路において到達不能であるか否かによりその故障の除去可能性を判定する.本手法では判定に用いる状態を到達不能状態に限るため, フリップフロップ数の多い回路に対しても適用可能である.ベンチマーク回路に対する実験結果より多くの冗長部分が除去されることを示す.また, テスト生成の結果から本手法の適用により回路のテスタビリティが向上することも示す. (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1520572360264178688 (CiNii: 1520572360264178688)
38.	Hiroyuki Yotsuyanagi, Seiji Kajihara and Kozo Kinoshita : Synthesis of Sequential Circuits by Redundancy Removal and Retiming, Journal of Electronic Testing - Theory and Applications, Vol.11, No.1, 81-92, 1997. (Summary) In this paper we propose a method for synthesizing sequential circuits to reduce the number of gates and flip-flops by removing both combinationally and sequentially redundant faults. In order to remove sequentially redundant faults these faults are converted into combinationally redundant faults by using retiming techniques and the combinationally redundant faults can be removed by using a test pattern generation method for combinational circuits. To simplify a given circuit retiming is utilized for two purposes in this method. One is to find sequentially redundant faults and another is to reduce the number of flip-flops and gates. Before and after each retiming the combinationally redundant faults are removed. Experimental results for ISCAS '89 benchmark circuits show that this method can remove many of sequentially redundant faults and can reduce a large number of gates and flip-flops. (Link to Publication Site) ● Publication site (DOI): 10.1023/A:1008251901959 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1023/A:1008251901959 (DOI: 10.1023/A:1008251901959)
39.	Hiroyuki Yotsuyanagi, Seiji Kajihara and Kozo Kinoshita : Retiming for Sequential Circuits with a Specified Initial State and Its Application to Testability Enhancement, IEICE Transactions on Information and Systems, Vol.E78-D, No.7, 861-867, 1995. (Summary) Retiming is a technique to resynthesize a synchronous sequential circuit by rearranging flip-flops. In view of logic optimization, retiming can potentially derive a circuit which is more simplified and testable because retiming can convert several sequential redundancies into combinational redundancies. Retiming methods proposed before have no guarantee to generate the same output sequences when the circuit start from a specified initial state such as the reset state. If the circuit with a specified initial state must have the same output sequences after retiming, rearrangement of flip-flops should be restricted. This paper presents a retiming method for circuits with a specified initial state so that retimed circuits give the same output sequences of the original circuits for any input sequences. In the proposed method, during the procedure of retiming each flip-flop keeps a value corresponding to the initial state and unification of flip-flops with different value is avoided. Our procedure uses 5-valued logic on gate level implementation to describe and calculate the values of flip-flops. Therefore after optimization using our method, the circuit has completely the same behavior as that of the original. Experimental results for ISCAS'89 benchmark circuits show the method can be used to optimize the circuits as well as a method without considering the initial state. And testability of the retimed circuit is more enhanced than that of the original circuit. (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1572261552264073344 (CiNii: 1572261552264073344)

Academic Paper (Unrefereed Paper):

1.	Hiroyuki Yotsuyanagi and Masaki Hashizume : On testing of open faults in multi-layered wiring LSIs, Bulletin of Institute of Technology and Science, The University of Tokushima, No.53, 16-20, 2008. (Summary) Open faults are difficult to test since the floating wire occurred by an open fault has unstable voltage. In this work, the effect of adjacent lines around an open fault in multi-layered wiring LSIs is discussed. To observe the relation between an open fault and the adjacent lines, a 0.35μm CMOS IC is designed and fabricated. The open fault macros with a transmission gate and with an intentional break are included in the IC. The adjacent lines in the same layer and the different layers are placed in the test chip. The simulation and experimental results show that the voltage at the floating wire is affected by the adjacent lines. (Tokushima University Institutional Repository) ● Metadata: 59703 (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1050564287417110144 (Tokushima University Institutional Repository: 59703, CiNii: 1050564287417110144)

Academic Letter:

1.	Shohei Kondo, Hiroyuki Yotsuyanagi and Masaki Hashizume : Propagation Delay Analysis of a Soft Open Defect inside a TSV, Transactions of The Japan Institute of Electronics Packaging, Vol.4, No.1, 119-126, 2011. (Summary) The propagation delay of a logic signal through a through silicon via (TSV) in a 3D IC may depend on a soft open defect inside it. The propagation delay of a defective TSV which is connected only with barrier metal, in part owing to a soft open defect, is analyzed with an electromagnetic simulator and a circuit one in this paper. The results reveal that if such a soft open defect occurs inside a TSV, the delay depends on the defect size and the IC may work without any errors. A soft open defect will change into a hard open one in operation of a 3D IC and may generate a logical error. In order to realize high reliability of the IC, the defect should be detected before it changes into a hard open defect. In this paper, test input vectors are proposed with which a soft open defect can be detected by delay testing. However, the simulation results suggest that when the input and output capacitance of a TSV is small, the defect may not be detected even if the test vectors are provided to the defective IC, since the propagation delay of the defective TSV can be smaller than a defect-free one. (Keyword) TSV / Soft Open / Propagation Delay / Electromagnetic Simulation / Fault Analysis / 3D IC / Delay Testing / Test Input Vector (Link to Publication Site) ● Publication site (DOI): 10.5104/jiepeng.4.119 (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1390001205315231104 ● Search Scopus @ Elsevier (DOI): 10.5104/jiepeng.4.119 (DOI: 10.5104/jiepeng.4.119, CiNii: 1390001205315231104)
2.	Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Sequential Redundancy Removal Using Test Generation and Multiple Strongly Unreachable States, IEICE Transactions on Information and Systems, Vol.E85-D, No.10, 1605-1608, 2002. (Summary) A procedure to remove redundancies in sequential circuits is proposed using strongly unreachable states, which are the states with no incoming transitions. Test generation is used to find undetectable faults related to two or more strongly unreachable states. Experimental results show the new procedure can find more redundancies of sequential circuits. (Keyword) synthesis for testability / redundancy removal / sequential circuit / undetectable faults / unreachable states (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1573950402004399616 ● Summary page in Scopus @ Elsevier: 2-s2.0-0036826120 (CiNii: 1573950402004399616, Elsevier: Scopus)

Review, Commentary:

1.	Hiroyuki Yotsuyanagi and バウンダリスキャン研究会 : The Current Status and Prospect in Boundary Scan Design, Journal of Japan Institute of Electronics Packaging, Vol.24, No.1, 96-98, Jan. 2021. (Link to Publication Site) ● Publication site (DOI): 10.5104/jiep.24.96 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.5104/jiep.24.96 (DOI: 10.5104/jiep.24.96)
2.	Hiroyuki Yotsuyanagi and バウンダリスキャン研究会 : Current Research Topics on Boundary-Scan Technology, Journal of Japan Institute of Electronics Packaging, Vol.23, No.6, 539-542, Sep. 2020. (Link to Publication Site) ● Publication site (DOI): 10.5104/jiep.23.539 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.5104/jiep.23.539 (DOI: 10.5104/jiep.23.539)
3.	Hiroyuki Yotsuyanagi and 検査技術委員会 : The Current Status and Perspective in Testing 3D Stacked ICs, Journal of Japan Institute of Electronics Packaging, Vol.23, No.1, 32-36, Jan. 2020. (Tokushima University Institutional Repository) ● Metadata: 118045 (Link to Publication Site) ● Publication site (DOI): 10.5104/jiep.23.32 (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1390565134815288448 ● Summary page in Scopus @ Elsevier: 2-s2.0-85077987511 (Tokushima University Institutional Repository: 118045, DOI: 10.5104/jiep.23.32, CiNii: 1390565134815288448, Elsevier: Scopus)
4.	Hiroyuki Yotsuyanagi : VLSI設計教育用設備の導入について, 広報, Vol.15, 41-42, Dec. 2008.
5.	Masaki Hashizume and Hiroyuki Yotsuyanagi : 東京大学VDECのICツールを用いたICの設計と試作, 広報, Vol.13, 30-32, Dec. 2006.

Proceeding of International Conference:

1.	Hiroyuki Yotsuyanagi : On the application of boundary scan design with embedded time-to-digital converter to 3D stacked IC, Proc. 2023 IEEE International Test Conference in Asia, Matsue, Sep. 2023.
2.	Shogo Tohkai, Daichi Akamatsu, Hiroyuki Yotsuyanagi and Masaki Hashizume : On Test Pattern Generation Method for an Approximate Multiplier Considering Acceptable Faults, Proc. 2023 IEEE International Test Conference in Asia, 1-6, Matsue, Sep. 2023. (Link to Publication Site) ● Publication site (DOI): 10.1109/ITC-Asia58802.2023.10301158 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/ITC-Asia58802.2023.10301158 (DOI: 10.1109/ITC-Asia58802.2023.10301158)
3.	Miki Hayato, Eisuke Ohama, Hiroyuki Yotsuyanagi and Masaki Hashizume : Evaluation of a PUF Embedded in the Delay Testable Boundary Scan Circuit, Proc. of 2023 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), 896-901, Cheju, Jun. 2023. (Summary) In recent years, as a security technology against counterfeit IC, Physically unclonable function (PUF) has been proposed that generates unique values based on manufacturing variability information that is difficult to be replicated. However, it requires area overhead to embed the PUF design into an IC to generate unique responses. In order to reduce the area overhead, we propose a method to make delay testing using design-for-testability also function as a PUF. In addition, we applied the unanimous selection method to generate unique values using the proposed method. We fabricated the prototype ICs in two different manufacturing lots and evaluated the stability and uniqueness of the PUF. The results show that different eigenvalues were generated for all chips, including those with different manufacturing lots. (Link to Publication Site) ● Publication site (DOI): 10.1109/ITC-CSCC58803.2023.10212656 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/ITC-CSCC58803.2023.10212656 (DOI: 10.1109/ITC-CSCC58803.2023.10212656)
4.	Ohmatsu Masao, Yuto Ohtera, Yuki Ikiri, Hiroyuki Yotsuyanagi, Shyue-Kung Lu and Masaki Hashizume : Enhanced Interconnect Test Method for Resistive Open Defects in Final Tests with Relaxation Oscillators, Proc.of IEEE 31st Asian Test Symposium, 49-53, Nov. 2022. (Summary) Resistive open defects may occur at interconnects between a printed circuit board and ICs in solder process. An enhanced test method in final tests and a built-in test circuit are proposed to detect resistive open defects of small resistance with relaxation oscillator embedded in ICs in this paper. It is examined by Spice simulations what resistive open defects can be detected. The results show that resistive open defects of 23.4 Ω and above are detected by the test method in a test speed of 1 MHz per an interconnect. (Link to Publication Site) ● Publication site (DOI): 10.1109/ATS56056.2022.00021 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-85145876818 (DOI: 10.1109/ATS56056.2022.00021, Elsevier: Scopus)
5.	Masao Ohmatsu, Fumiya Sako, Ikiri Yuki, Hiroyuki Yotsuyanagi, Lu Shyue-Kung and Masaki Hashizume : Detectability of Open Defects at Interconnects between Dies in 3D Stacked ICs with Relaxation Oscillators, Proc. of IEEE CPMT Symposium Japan 2022, 94-95, Kyoto, Nov. 2022. (Summary) Detectability of a test method utilizing a relaxation oscillator is examined by circuit simulations for open defects between dies in 3D stacked ICs, The results show that resistive open defects of O.6Ω above are detected. (Link to Publication Site) ● Publication site (DOI): 10.1109/ICSJ55786.2022.10034736 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-85148698769 (DOI: 10.1109/ICSJ55786.2022.10034736, Elsevier: Scopus)
6.	Hiroyuki Yotsuyanagi, Kohji Arimoto, Koji Makino and Masaki Hashizume : Scan Shift Reduction in Delay Testing using Bounary Scan with Embedded TDC, the 22nd IEEE Workshop on RTL and High Level Testing, Online, Nov. 2021.
7.	Yuya Okumoto, Hiroyuki Yotsuyanagi, Masaki Hashizume and Shyue-Kung Lu : Detectable Resistance Increase of Open Defects in Assembled PCBs by Quiescent Currents through Embedded Diodes, Proc. of 2021 International Conference on Electronics Packaging (ICEP), Tokyo, May 2021. (Summary) It is discussed in this paper what resistance increase can be detected by an electrical interconnect test method that occurs after shipping to market at interconnects between ICs and printed circuit boards. The test method is based on a quiescent current made flow through a diode embedded for the tests. Independently of the current variations caused by process variations of ICs, we show by Spice simulations that resistance increase of 0.5 Ω can be detected by the test method with a measurement tool of 0.1mV resolution. (Link to Publication Site) ● Publication site (DOI): 10.23919/ICEP51988.2021.9451913 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.23919/ICEP51988.2021.9451913 (DOI: 10.23919/ICEP51988.2021.9451913)
8.	Yuki Ikiri, Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Yokoyama and Shyue-Kung Lu : Recovery of Defective TSVs with A Small Number of Redundant TSVs in 3D Stacked ICs, the 21st IEEE Workshop on RTL and High Level Testing, Online, Nov. 2020. (Summary) A repair circuit is proposed to recover defective Through Silicon Vias (TSVs) in a 3D stacked ICs in this paper. A defective TSV is replaced to a defect-free one in a small number of redundant TSVs with the circuit. The number is specified from yield of TSVs in the fabrication process. The circuit size is small, since the number of redundant TSVs is small. The circuit is evaluated by Spice simulation. The results show that a TSV is connected to a defect-free one with a small area overhead and a small additional delay.
9.	Kanami Nagata, Hiroyuki Yotsuyanagi and Masaki Hashizume : Test Time Reduction of Small Delay Testing for Scan Design with Embedded TDC, the 21st IEEE Workshop on RTL and High Level Testing, Online, Nov. 2020.
10.	Sako Fumiya, yuki ikiri, Masaki Hashizume, Hiroyuki Yotsuyanagi, Yokoyama Hiroshi and Shyue-Kung Lu : Temperature Sensing with a Relaxation Oscillator in CMOS ICs, Proc. of The 35th International Technical Conference on Circuits/Systems, Computers and Communications, 141-144, Jul. 2020. (Summary) Temperature monitoring is indispensable for realizing a long life in ICs, since reliability of ICs is affected by the temperature. We propose a temperature sensor based on an oscillation frequency of a relaxation oscillator embedded in an IC. In order to examine feasibility of the temperature monitoring, we designed a sensor circuit utilizing a relaxation oscillator and examined it by SPICE simulations. The simulation results show that temperatures in ICs can be estimated by a single regression straight line with a small error under process variations of MOSs in the ICs. (Keyword) sensor / Relaxation Oscillator / analog electronic circuits (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-85091417654 (Elsevier: Scopus)
11.	Toshiaki Satoh, Hiroyuki Yotsuyanagi and Masaki Hashizume : On Delay Elements in Boundary Scan Cells for Delay Testing of 3D IC Interconnection, Proc. of The IEEE 2019 International 3D Systems Integration Conference, P4023-1-P4023-4, Sendai, Oct. 2019. (Summary) For testing delay faults in 3D IC interconnection, we have proposed a DFT (Design-for-Testability) method for TSVs using a modified boundary scan circuit with embedded Time-to-Digital Converter (TDCBS). A TDCBS cell has a delay element to form a delay line. In this paper, for improving delay resolution, delay gates that have small propagation delay time are investigated and implemented as a delay line. In order to prevent pulse shrinking of transition signal through a delay line, the proposed cell is designed to reduce the difference in transition delay between the delay for rising transition and for falling transition. The measurement results for an experimental chip show the effectiveness of our new design. (Link to Publication Site) ● Publication site (DOI): 10.1109/3DIC48104.2019.9058908 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-85084110950 (DOI: 10.1109/3DIC48104.2019.9058908, Elsevier: Scopus)
12.	Hanna Soneda, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Electrical Field Test Method of Resistive Open Defects between Dies by Quiescent Currents through Embedded Diodes, Proc. of The IEEE 2019 International 3D Systems Integration Conference, P4022-1-P4022-5, Sendai, Oct. 2019. (Summary) Dies in 3D stacked ICs are connected with Through-Silicon-Vias or micro bumps. Resistive open defects may occur at interconnects between the dies in fabrication process. The defects may grow to an open circuit fault in the field after shipping to a market. In this paper, a field test method is proposed so as the defect to be detected after shipping to a market before it becomes an open circuit fault. This test method is based on a quiescent supply current that is made flow through an interconnect between dies only in tests. It is shown by Spice simulation that an increase of 0.01Ω is detected by the test method in field tests. (Link to Publication Site) ● Publication site (DOI): 10.1109/3DIC48104.2019.9058777 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-85084108412 (DOI: 10.1109/3DIC48104.2019.9058777, Elsevier: Scopus)
13.	Shuya Kikuchi, Hiroyuki Yotsuyanagi and Masaki Hashizume : On Delay Measurement under Delay Variations in Boundary Scan Circuit with Embedded TDC, Proc. 2019 IEEE International Test Conference in Asia, 169-174, Tokyo, Sep. 2019. (Summary) With the high integration of integrated circuits, small delay faults have occurred as the cause of a circuit failure. We have proposed a method for testing small delay faults using a boundary scan circuit with embedded TDC (TDCBS). In this method, delay faults are detected by using the number of stages in which a transition signal has propagated through a delay line. However, there exists delay variation in a delay line. This paper investigated delay variation by measuring transition delay for different paths in the delay line. In addition, to calibrate delay variation, we investigated a calibration method for considering the variation of wire length and delay in a delay line in TDCBS. Measurement results for an experimental chip show that the method can compensate the variations in the delay line. (Link to Publication Site) ● Publication site (DOI): 10.1109/ITC-Asia.2019.00042 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-85074417754 (DOI: 10.1109/ITC-Asia.2019.00042, Elsevier: Scopus)
14.	Michiya Kanda, Daisuke Yabui, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Stand-by Mode Test Method of Interconnects between Dies in 3D ICs with IEEE 1149.1 Test Circuits, Proc. of IEEE CPMT Symposium Japan 2018, 189-192, Kyoto, Nov. 2018. (Summary) In this paper, we propose a stand-by interconnect test method of 3D stacked ICs with IEEE 1149.1 test circuits embedded in dies. Resistive open defects are detected after shipping to a market by the test method that occur at input interconnects of dies operating at a stand-by mode. Feasibility of the stand-by tests is examined by SPICE simulation. It is shown that a resistive open defect of 83kΩ and above can be detected at a test speed of 20MHz by the test method. (Link to Publication Site) ● Publication site (DOI): 10.1109/ICSJ.2018.8602560 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/ICSJ.2018.8602560 (DOI: 10.1109/ICSJ.2018.8602560)
15.	Yuta Matsumoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Resistive Open Defect Detection in SoCs by a Test Method Based on Injected Charge Volume after Test Input Application, Proc. of IEEE CPMT Symposium Japan 2018, 141-142, Kyoto, Nov. 2018. (Summary) A test method is proposed of resistive open defects in an SoC by means of charge volume injected from the VDD terminal. The charge is injected after providing a test input vector from a charge injector instead of a DC power voltage source. It is shown by Spice simulation that a resistive open defect in four parallel inverter chain circuits of 30 stages whose resistance is larger than 10kΩ can be detected by the test method. (Link to Publication Site) ● Publication site (DOI): 10.1109/ICSJ.2018.8602818 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-85061740936 (DOI: 10.1109/ICSJ.2018.8602818, Elsevier: Scopus)
16.	Satoshi Hirai, Hiroyuki Yotsuyanagi and Masaki Hashizume : Test Time Reduction on Testing Delay Faults in 3D ICs Using Boundary Scan Design, Proc.of IEEE 27th Asian Test Symposium, 7-12, Hefei, Oct. 2018. (Summary) A boundary scan design with embedded time-to- digital converter (TDCBS) has been proposed for testing small delay faults. In this paper, the TDCBS is applied for testing TSVs in 3D IC. To reduce test application time of the TDCBS, we propose a modified TAP controller that utilizes the bypass mode for reducing unnecessary scan shifts during observation of the captured results. The simulation for an experimental circuit is shown to evaluate the effectiveness of the proposed method. Keywords delay (Link to Publication Site) ● Publication site (DOI): 10.1109/ATS.2018.00013 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-85060031897 (DOI: 10.1109/ATS.2018.00013, Elsevier: Scopus)
17.	Ishihara Ken, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Resistive Open Defects in 3D Stacked ICs Detected by Electrical Interconnect Testing with a Charge Injector Made of MOS Capacitors, Proc. of 33rd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2018), 114-117, Bangkok, Jul. 2018.
18.	Jumpei Kawano, Hiroyuki Yotsuyanagi and Masaki Hashizume : On Design and Evaluation of a TDC Cell Embedded in the Boundary Scan Circuit for Delay Fault Testing of 3D ICs, Proc. of 33rd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2018), 110-113, Bangkok, Jul. 2018.
19.	Toshinori Hosokawa, Morito Niseki, Masayoshi Yoshimura, Hiroshi Yamazaki, Masayuki Arai, Hiroyuki Yotsuyanagi and Masaki Hashizume : A Sequentially Untestable Fault Identification Method Based on n-Bit State Cube Justification, 24th IEEE International Symposium on On-Line Testing and Robust System Design, Spain, Jul. 2018. (Summary) Non-scan based test generation is required to reduce test cost and improve security. However, sequential test generation consumes a lot of time to identify untestable faults. Therefore, it is important to identify untestable faults in the preprocessing of the test generation. In this paper, an unreachable state identification method, which identifies whether states on a few flip-flops can be justified using SAT, and an untestable fault identification method using the unreachable states are proposed. Experimental results show that our proposed method was effective compared with conventional methods. (Link to Publication Site) ● Publication site (DOI): 10.1109/IOLTS.2018.8474268 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-85055817233 (DOI: 10.1109/IOLTS.2018.8474268, Elsevier: Scopus)
20.	Jumpei Kawano, Hiroyuki Yotsuyanagi and Masaki Hashizume : Effect of Routing in Testing a TSV Array Using Boundary Scan Circuit with Embedded TDC, Proc. of International Forum on Advanced Technologies 2018, P1-13-1-P1-13-3, Tokushima, Japan, Mar. 2018.
21.	Alia Ashikin Fara, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Electrical Tests for Capacitive Open Defects in Assembled PCBs, Proc. of International Forum on Advanced Technologies 2018, P1-12-1-P1-12-3, Tokushima, Japan, Mar. 2018.
22.	Michiya Kanda, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Resistive Open Defect Detection in 3D ICs with a Comparator of Offset Cancellation Type under Process Variation, Proc. of International Forum on Advanced Technologies 2018, P1-11-1-P1-11-3, Tokushima, Japan, Mar. 2018.
23.	Miyatake Noriko, Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Yokoyama and Tetsuo Tada : Oscillation Frequency Estimation of Ring Oscillator for Interconnect Tests in 3D Stacked ICs, Proc. of 2018 RISP International Workshop on Nonlinear Circuits, Communications, 659-662, Mar. 2018. (Summary) A powerful electrical test method with a ring oscillator has been proposed to detect resistive open defects at interconnects between dies in 3D ICs. An oscillation frequency of the ring oscillator and the testability of the test method may change with temperature. Thus, we designed a ring oscillator and examined what extend the oscillation frequency of the ring oscillator changed with temperature by Spice simulation. The simulation results show that the frequency depends on temperature but is able to be estimated by a linear regression method precisely.
24.	Hanna Soneda, Michiya Kanda, Masaki Hashizume, Hiroyuki Yotsuyanagi and Kung Shyue LU : Detectable Resistive Open Defects in 3D ICs with Electrical Interconnect Test Circuit Made of Diodes, Proc. of 2018 RISP International Workshop on Nonlinear Circuits, Communications, 655-658, Mar. 2018. (Summary) We have proposed an electrical test method for detecting open defects that occur at interconnect between dies in 3D ICs and a built-in test circuits for the tests. The test method is based on supply current that is made flowthrough an interconnect to be tested. Testability of the test method may depend on process variation, since the test method utilizes the built-in test circuit. We have examined what resistance of an open defect can be detected by the test method under a process variation by Spice simulation.The results show that resistive open defects of 56 or more can be detected by the test method.
25.	Morito Niseki, Toshinori Hosokawa, Masayoshi Yoshimura, Hiroshi Yamazaki, Masayuki Arai, Hiroyuki Yotsuyanagi and Masaki Hashizume : A Sequentially Untestable Fault Identification Method Based on State Cube Justification, the 18th IEEE Workshop on RTL and High Level Testing, 43-46, Taipei, Dec. 2017.
26.	Satoshi Hirai, Hiroyuki Yotsuyanagi and Masaki Hashizume : Reordering Delay Elements in Boundary Scan Circuit with Embedded TDC, the 18th IEEE Workshop on RTL and High Level Testing, Taipei, Dec. 2017.
27.	Shyue-Kung Lu, Shu-Chi Yu, Masaki Hashizume and Hiroyuki Yotsuyanagi : Fault-Aware Page Address Remapping Techniques for Enhancing Yield and Reliability of Flash Memories, Proc.of IEEE 26th Asian Test Symposium, 249-254, Taipei, Nov. 2017. (Link to Publication Site) ● Publication site (DOI): 10.1109/ATS.2017.55 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-85045203112 (DOI: 10.1109/ATS.2017.55, Elsevier: Scopus)
28.	Ayumu Kambara, Hiroyuki Yotsuyanagi, Daichi Miyoshi, Masaki Hashizume and Shyue-Kung Lu : Open Defect Detection with a Built-in Test Circuit by IDDT Appearance Time in CMOS ICs, Proc.of IEEE 26th Asian Test Symposium, 237-242, Taipei, Nov. 2017. (Link to Publication Site) ● Publication site (DOI): 10.1109/ATS.2017.53 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-85045184667 (DOI: 10.1109/ATS.2017.53, Elsevier: Scopus)
29.	Kouhei Ohtani, Naho Osato, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Resistive Open Defects Detected by Interconnect Testing Based on Charge Volume Injected to 3D ICs, Proc. of IEEE CPMT Symposium Japan 2017, 231-234, Kyoto, Nov. 2017. (Link to Publication Site) ● Publication site (DOI): 10.1109/ICSJ.2017.8240124 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-85049240955 (DOI: 10.1109/ICSJ.2017.8240124, Elsevier: Scopus)
30.	Michiya Kanda, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : A Built-in Current Sensor Made of a Comparator of Offset Cancellation Type for Electrical Interconnect Tests of 3D ICs, Proc. of IEEE CPMT Symposium Japan 2017, 137-138, Kyoto, Nov. 2017. (Link to Publication Site) ● Publication site (DOI): 10.1109/ICSJ.2017.8240131 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-85049257021 (DOI: 10.1109/ICSJ.2017.8240131, Elsevier: Scopus)
31.	Michiya Kanda, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : A Defective Level Monitor of Open Defects in 3D ICs with a Comparator of Offset Cancellation Type, 2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 1-4, Cambridge, Oct. 2017. (Summary) 3D IC内にIEEE1149.1テスト回路が適用されたIC間の接続の欠陥レベルモニタとしてIC内の静的電源電流を用いる手法を提案する．オフセットキャンセル型比較回路を用いることで5Ωの精度での断線故障の観測可能性を示す． (Link to Publication Site) ● Publication site (DOI): 10.1109/DFT.2017.8244446 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-85046006104 (DOI: 10.1109/DFT.2017.8244446, Elsevier: Scopus)
32.	Yuuya Ohama, Masaki Hashizume, Hiroyuki Yotsuyanagi, Yoshinobu Higami and Hiroshi Takahashi : On Selection of Adjacent Lines in Test Pattern Generation for Delay Faults Considering Crosstalk Effects, Proc. of 17th International Symposium on Communications and Information Technologies, 96-100, Cairns, Sep. 2017. (Summary) With miniaturization of semiconductor manufacturing process, line spacing becomes narrower and hence the influence of coupling capacitance cannot be ignored. The signal delay on a defective line is affected by the signal transitions on its adjacent lines through the coupling capacitance. In addition, the delay size depends on the timing skew between signal transitions on the defective line and its adjacent lines. In test pattern generation, not all adjacent lines are required to have signal transitions to excite the fault effect if a large relative timing skew exists between the faulty line and the adjacent line. In this paper, we propose a selection method of adjacent lines for assigning signal transitions in test pattern generation. The proposed method can reduce the number of adjacent lines used in test pattern generation without degrading the quality of test pattern that can excite the fault effect. (Link to Publication Site) ● Publication site (DOI): 10.1109/ISCIT.2017.8261186 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-85049501874 (DOI: 10.1109/ISCIT.2017.8261186, Elsevier: Scopus)
33.	Kouhei Ohtani, Naho Osato, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : A Defect Level Monitor of Resistive Open Defect at Interconnects in 3D ICs by Injected Charge Volume, Proc. of 17th International Symposium on Communications and Information Technologies, 46-50, Cairns, Sep. 2017. (Summary) Resistive open defects may occur at interconnects among dies in 3D stacked ICs. A defect level monitor is proposed so as for the defects to be detected before they change into a hard open defect that generates logical errors. The changing process of resistive open defects is monitored by means of charge volume injected from the monitor. It is shown by Spice simulation that resistive open defects whose resistance is greater than 2Ω can be detected by online tests with the monitor before changing them to hard open defects in the field. (Link to Publication Site) ● Publication site (DOI): 10.1109/ISCIT.2017.8261176 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-85049520908 (DOI: 10.1109/ISCIT.2017.8261176, Elsevier: Scopus)
34.	Michiya Kanda, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Capacitive Open Detection in 3D ICs with A Built-in Comparator of Offset Cancellation Type, IEEE 2017 Taiwan and Japan Conference on Circuits and Systems, Okayama, Aug. 2017.
35.	Michiya Kanda, Masaki Hashizume, Akihiro Odoriba, Yohei Kakee, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : A Built-in Test Circuit Using A Comparator of Offset Cancel Type for Electrical Interconnect Tests of 3D Stacked ICs, Proc. of International Forum on Advanced Technologies 2017, 233-235, Hualien, Taiwan, Mar. 2017.
36.	Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Yokoyama, Tetsuo Tada and Shyue-Kung Lu : Test Input Vectors for Detecting Stuck-at Faults at Address and Data Buses in 3D Stacked Memory ICs, Proc. of International Forum on Advanced Technologies 2017, 127-129, Hualien, Taiwan, Mar. 2017.
37.	Zheng-Hong Cai, Hiroyuki Yotsuyanagi and Masaki Hashizume : A Modified PRPG for Test Data Reduction Using BAST Structure, Proc. RISP International Workshop on Nonlinear Circuit and Signal Processing, 441-444, Guam, Mar. 2017.
38.	Fara Ashikin Binti Ali, Yuki Ikiri, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Capacitive Open Defect Detection by Electrical Interconnect Test of 3D ICs without Boundary Scan Flip Flops, Proc. of the 17th IEEE Workshop on RTL and High Level Testing, 1-2-1-1-2-6, Hiroshima, Nov. 2016. (Summary) Three-dimensional (3D) integration using Through-Silicon Via (TSV) has been proposed as an excellent alternative to cope with the challenges faced by the current 2D technology. A 3D IC using TSV is fabricated by stacking multiple dies and vertically connected by TSVs and/or micro bumps. This enables the interconnects in the 3D IC to be shortened and high performance improvement to be achieved. However, there are open defects, such as voids and cracks, that occur between dies in 3D IC that can decrease the performance of the chip. Conventionally, a boundary scan embedded inside IC is used in order to test the interconnects. On the other hand, there is also a case where the IC not embedded with boundary scan is used. In this paper, we propose an electrical test circuit of 3D IC that does not implement boundary scan flip flops. The testability of the electrical test is evaluated by SPICE simulation. Capacitive open defects occuring at interconnect are detected by the test method. Simulation results show that capacitive open defect generating no logical errors can be detected by our method at a test speed of 1MHz.
39.	Takumi Kawaguchi, Hiroyuki Yotsuyanagi and Masaki Hashizume : On Control Circuit and Observation Conditions for Testing Multiple TSVs Using Boundary Scan Circuit with Embedded TDC, Proc. of the 17th IEEE Workshop on RTL and High Level Testing, 1-3-1-1-3-6, Hiroshima, Nov. 2016. (Summary) In this study, we design the control circuit for boundary scan circuit with embedded Time-to-Digital Converter (TDCBS) and derive the observation condition of delay amounts of TSVs (Through Silicon Via) to implement TDCBS for testing TSVs in 3-Dimensional IC (3DIC). TSVs may cause small delay fault that is impossible to detect using conventional logic testing methods due to the complexity of the manufacturing process of interconnects in 3DIC including TSVs and microbumps. Although we have been proposed a DFT (Design For Testability) method for TSVs using TDCBS, the application of TDCBS in 3DIC will cause an increase in number of dedicated control pins and TSVs. In addition, it maybe difficult to observe each delay amounts of TSV in case of testing multiple TSVs. In this paper, to implement TDCBS for testing TSVs in 3DIC, we designed a circuit which can control the pins inside TDCBS circuit and explain the observation conditions for measuring delay of each TSV in case of testing multiple TSVs.
40.	Ali Ashikin Binti Fara, Masaki Hashizume, Yuki Ikiri, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Testability for Resistive Open Defects by Electrical Interconnect Test of 3D ICs without Boundary Scan Flip Flops, Proc. of IEEE CPMT Symposium Japan 2016, 137-138, Kyoto, Nov. 2016. (Summary) A three-dimensional integrated circuit is fabricated by stacking multiple dies. A resistive open defect may occur at interconnects between the dies by a void and a crack in the fabrication process. We have proposed an electrical test method for an IC made of dies in which boundary scan flip flops are not embedded. In this paper, testability of the test method for resistive open defects is examined by Spice simulation. The results show that a resistive open defect whose resistance is greater than 150 is able to be detected at a test speed of 500kHz. (Link to Publication Site) ● Publication site (DOI): 10.1109/ICSJ.2016.7801302 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-85010669834 (DOI: 10.1109/ICSJ.2016.7801302, Elsevier: Scopus)
41.	Kouhei Ohtani, Masaki Hashizume, Daisuke Suga, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : A Power Supply Circuit for Interconnect Tests Based on Injected Charge Volume of 3D IC, Proc. of IEEE CPMT Symposium Japan 2016, 139-140, Kyoto, Nov. 2016. (Summary) A power supply circuit and an electrical interconnect test method are proposed to detect open defects at interconnects between dies in 3D ICs. The test method is based on the amount of charge injected from the power supply voltage source. It is shown by Spice simulation that resistive open defects whose resistance is greater than 20 can be detected with the power supply circuit by the test method. (Link to Publication Site) ● Publication site (DOI): 10.1109/ICSJ.2016.7801303 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-85010664460 (DOI: 10.1109/ICSJ.2016.7801303, Elsevier: Scopus)
42.	Masaki Hashizume, Akihiro Odoriba, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : A Built-in Defective Level Monitor of Resistive Open Defects in 3D ICs with Logic Gates, Proc. of IEEE CPMT Symposium Japan 2016, 99-102, Kyoto, Nov. 2016. (Summary) Resistive open defects in 3D ICs may change into hard open ones. In this paper, a built-in test circuit is proposed to monitor the changing process of the resistive open defects occurring at interconnects between dies embedding an IEEE 1149.1 test circuit. Feasibility of the process monitoring is examined experimentally in a PCB circuit made of ICs embedding the test circuit. It is shown that the changing process of a resistive open defect can be monitored at a test speed of 500 kHz. (Link to Publication Site) ● Publication site (DOI): 10.1109/ICSJ.2016.7801299 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-85010688871 (DOI: 10.1109/ICSJ.2016.7801299, Elsevier: Scopus)
43.	Fara Binti Ali Ashikin, Akihiro Odoriba, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Electrical Tests for Capacitive Open Defects in Assembled PCBs, Proc. of International Design and Concurrent Engineering Conference 2016, Langkawi, Sep. 2016.
44.	Masaki Hashizume, Yudai Shiraishi, Hiroyuki Yotsuyanagi, Hiroshi Yokiyama, Tetsuo Tada and Shyue-Kung Lu : Electrical Test of Resistive and Capacitive Open Defects at Data Bus in 3D Memory IC, Proc. of International Design and Concurrent Engineering Conference 2016, Langkawi, Sep. 2016. (Summary) an electrical test method of resistive and capacitive open defects occurring at data bus lines between dies in a 3D memory IC is proposed. The test method is based on supply current of the IC. The number of test vectors for a 3D memory IC made of ND memory dies in the test method is 10*ND and small. Also, a defective interconnect is located by the test method. Feasibility of the tests is examined by some experiments for a circuit made of an SRAM IC on a printed circuit board. The experimental results show that a capacitive open defect and a resistive open one whose resistance is greater than 200 can be detected by the test method.
45.	Kouhei Ohtani, Daisuke Suga, Hiroyuki Yotsuyanagi and Masaki Hashizume : A Built-in Test Circuit for Injected Charge Tests of Open Defects in CMOS ICs, Proc. of International Technical Conference on Circuits/Systems, Computers and Communications 2016, 291-294, Okinawa, Jul. 2016. (Summary) CMOS ICの断線故障検査のために電圧源からの注入電荷量に基づき故障判定を行う手法を提案する．試作ICに提案回路を実装し，実験により検査可能性について評価する． (Keyword) SOC / BIST / open defect / Electrical Test
46.	Masashi Okamoto, Akihiro Odoriba, Hiroyuki Yotsuyanagi, Masaki Hashizume and Shyue-Kung Lu : A Built-in Test Circuit to Monitor Changing Process of Resistive Open Defects in 3D ICs, Proc. of International Technical Conference on Circuits/Systems, Computers and Communications 2016, 295-298, Okinawa, Jul. 2016. (Summary) 抵抗性断線欠陥の進行プロセスを監視するための3D IC用組込みテスト回路を提案する．IEEE1149.1テスト回路と検査容易化設計された入出力バッファを用いた提案回路における監視の可能性をシミュレーションにより評価する． (Keyword) 3D IC / Process Monitor / open defect / BIST
47.	Takumi Miyabe, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu and Zvi Roth : A Built-in Electrical Test Circuit for Detecting Open Leads in Assembled PCB Circuits with RC Integrator, Proceedings of International Conference on Electronics Packaging 2016, 451-455, Sapporo, Apr. 2016. (Summary) BGA ICのリードとプリント基板間の断線について積分回路により生成する時変信号を印加することで検査する組込み電気的検査回路を提案する．断線故障は入力バッファをセンサとして用いることで電源電流の異常として検出される． (Keyword) Open / PCB / Test
48.	Ali Ashikin Binti Fara, Akihiro Odoriba, Masaki Hashizume, Shoichi Umezu, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Electrical Tests of Capacitive Open Defects at BGA ICs in Assembled PCB, Proc. of International Forum on Advanced Technologies 2016, 229-231, Tokushima, Mar. 2016.
49.	Yuki Ikiri, Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Yokoyama, Tetsuo Tada and Shyue-Kung Lu : Die Design for Cost reduction of 3F Stacked Memory ICs, Proc. of International Forum on Advanced Technologies 2016, 79-80, Tokushima, Mar. 2016.
50.	Masaki Hashizume, Yuki Ikiri, Shoichi Umezu, Ali Ashikin Binti Fara, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Feasibility of Electrical Test for Open Defects at Address Bus in 3D Memory IC, Proc. of International Forum on Advanced Technologies 2016, 51-53, Tokushima, Mar. 2016.
51.	Masaki Hashizume, Shoichi Umezu, Yuki Ikiri, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Test Circuit for Electrical Interconnect Tests of 3D ICs without Boundary Scan Flip Flops, Proc. of the 16th IEEE Workshop on RTL and High Level Testing, 23-28, Mumbai, Nov. 2015. (Summary) A test circuit for an electrical interconnect test method is proposed of a 3D stacked ICs made of dies in which boundary scan flip flops are not embedded in this paper. Hard and resistive open defects occurring at interconnects between dies embedding the test circuit are detected by the test method. Feasibility of the electrical tests with the test circuit is evaluated by some experiments in a circuit made of a prototype IC and by Spice simulation. The experimental results show that a hard open defect and a resistive open one are able to be detected by the test method at a test speed of 500Hz. In the simulation results, they are detected at a test speed of 250MHz.
52.	Masaki Hashizume, Shoichi Umezu, Yuki Ikiri, Ali Ashikin Binti Fara, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Electrical Interconnect Test Method of 3D ICs without Boundary Scan Flip Flops, Proc. of IEEE CPMT Symposium Japan 2015, 136-139, Kyoto, Nov. 2015. (Summary) 3D IC の接続テスト手法として，バウンダリスキャン回路を用いない電気的検査法を提案する．試作回路により実験を行い500kHzの検査速度での完全断線故障と抵抗性断線の検査可能であることを示す． (Link to Publication Site) ● Publication site (DOI): 10.1109/ICSJ.2015.7357381 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-84964061341 (DOI: 10.1109/ICSJ.2015.7357381, Elsevier: Scopus)
53.	Akihiro Odoriba, Masaki Hashizume, Shoichi Umezu and Hiroyuki Yotsuyanagi : A Design for Testability with nMOS Switches to Detect Open pins in Assembled PCBs, Proc. of International Design and Concurrent Engineering Conference 2015, 31-1-31-6, Tokushima, Sep. 2015. (Summary) ICとプリント基板間のはんだオープンについてnMOSスイッチとダイオードを用いた検査容易化設計を提案する．入力保護回路とICコア間に付加回路を挿入し，バウンダリスキャンテスト回路を用いてテストパターンを印加し，供給電流の測定により検査を行う．シミュレーションと試作ICにより提案手法の有効性を評価する．
54.	Hiroyuki Yotsuyanagi, Akihiro Fujiwara and Masaki Hashizume : On TSV Array Defect Detection Method Using Two Ring-oscillators Considering Signal Transitions at Adjacent TSVs, Proc. of IEEE 3D System Integration Conference 2015, TS8.24.1-TS8.24.4, Sep. 2015. (Link to Publication Site) ● Publication site (DOI): 10.1109/3DIC.2015.7334594 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-84962289242 (DOI: 10.1109/3DIC.2015.7334594, Elsevier: Scopus)
55.	Daisuke Suga, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Electrical Interconnect Test Method of 3D ICs by Injected Charge Volume, Proc. of IEEE 3D System Integration Conference 2015, TS8.19.1-TS8.19.5, Sendai, Sep. 2015. (Link to Publication Site) ● Publication site (DOI): 10.1109/3DIC.2015.7334588 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-84962274243 (DOI: 10.1109/3DIC.2015.7334588, Elsevier: Scopus)
56.	Kosuke Nanbara, Akihiro Odoriba, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Electrical Interconnect Test of 3D ICs Made of Dies without ESD Protection Circuits with a Built-in Test Circuit, Proc. of IEEE 3D System Integration Conference 2015, TS8.22.1-TS8.22.5, Sendai, Sep. 2015. (Link to Publication Site) ● Publication site (DOI): 10.1109/3DIC.2015.7334592 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-84962313695 (DOI: 10.1109/3DIC.2015.7334592, Elsevier: Scopus)
57.	Masaki Hashizume, Singo Saijyo and Hiroyuki Yotsuyanagi : Electrically Testable CMOS Image Pixel Circuit, Proc. of IEEE 2015 European Conference on Circuit Theory and Design, 1-4, Trondheim, Aug. 2015. (Summary) CMOS画素回路の電気的検査法として，光を照射せずに検査可能な検査容易化設計手法を提案する．SPICEシミュレーションにより断線故障の89%が提案手法にて検出可能であることを示す． (Link to Publication Site) ● Publication site (DOI): 10.1109/ECCTD.2015.7300000 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/ECCTD.2015.7300000 (DOI: 10.1109/ECCTD.2015.7300000)
58.	Daisuke Suga, Hiroyuki Yotsuyanagi and Masaki Hashizume : Electrical Test for Open Defects in CMOS ICs by Injected Charge, Proc. of International Technical Conference on Circuits/Systems, Computers and Communications 2015, 653-656, Seoul, Jun. 2015. (Summary) CMOS ICの断線故障の検査手法として，電源電圧源からの電荷供給量に基づき故障を検出する手法を提案する．インバータチェイン回路内に発生する断線故障に対して提案手法を適用し故障検出が可能であることを示す． (Keyword) CMOS IC / Open Defect / Electrical Test
59.	Yuki Ikiri, Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Yokoyama, Tetsuo Tada and Shyue-Kung Lu : Repair Circuit of TSVs in a 3D Stacked Memory IC, Proc. of International Technical Conference on Circuits/Systems, Computers and Communications 2015, 431-434, Seoul, Jun. 2015. (Summary) 3D IC のシリコン貫通ビアのリペア回路を提案する．故障TSVを正常TSVに接続変更するためのスイッチ回路を設計し，小面積で付加遅延も小さいことをSpiceシミュレーションにて評価した． (Keyword) 3D IC / Repair Circuit / TSV / Yield Improvement
60.	Akihiro Odoriba, Shoichi Umezu, Masaki Hashizume, Hiroyuki Yotsuyanagi, Ali Ashikin Binti Fara and Shyue-Kung Lu : A Testable Design for Electrical Interconnect Tests of 3D ICs, Proceedings of 2015 International Conference on Electronics Packaging and iMAPS All Asia Conference, 718-722, Kyoto, Japan, Apr. 2015. (Summary) 3D ICのダイ間の断線故障を検出する電気的検査法としてIEEE1149.1テスト回路を用いてテストパターンを印加する手法を提案する．シミュレーションにて1GHzのテスト速度の下で完全断線故障と抵抗性断線故障の検出可能性を評価する． (Keyword) Open Defect / 3D IC / Test (Link to Publication Site) ● Publication site (DOI): 10.1109/ICEP-IAAC.2015.7111105 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-84936077882 (DOI: 10.1109/ICEP-IAAC.2015.7111105, Elsevier: Scopus)
61.	Yuki Ikiri, Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Yokoyama, Tetsuo Tada and Shyue-Kung Lu : Switch Circuit for Repairing Defective TSVs in a 3D Stacked Memory IC, Proc. of International Forum on Advanced Technologies 2015, 160-161, Tokushima, Mar. 2015.
62.	Masaki Hashizume, Shoichi Umezu, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : A Built-in Supply Current Test Circuit for Electrical Interconnect Tests of 3D ICs, Proc. of IEEE 3D System Integration Conference 2014, O7-1-O7-6, Kinsdale, Ireland, Dec. 2014. (Summary) 3D ICの接続テストのための組込み電流テスト回路を提案する．試作ICとシミュレーションにより，1MHzのテスト速度の下で10nFの容量断線，1kΩの抵抗断線が検出可能であることを示す． (Link to Publication Site) ● Publication site (DOI): 10.1109/3DIC.2014.7152148 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/3DIC.2014.7152148 (DOI: 10.1109/3DIC.2014.7152148)
63.	Chih-Chan Fang, Hiroyuki Yotsuyanagi and Masaki Hashizume : A Test Pattern Matching Method on BAST Architecture for Test Data Reduction by Controlling Scan Shift, Proc. of the 15th IEEE Workshop on RTL and High Level Testing, 130-134, Nov. 2014. (Summary) To reduce test data volume, BIST-Aided Scan Test (BAST) technique that combines Automatic Test Pattern Generator (ATPG) and Built-In-Self-Test had been proposed. In this paper, we propose a test pattern matching method used on BAST architecture which can reduce test data required for bit-flips and skipping random patterns. To find a better matching with less BAST codes, we propose a procedure to modify matching obtained by the previous method. In this procedure, the ATPG pattern matched with the last part in the PRPG patterns is selected to find another matching that can reduce BAST codes. The experimental results for some benchmark circuits are also shown.
64.	Jun Yamashita, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yoshinobu Higami and Hiroshi Takahashi : On SAT-based Test Generation for Resistive Open Using Delay Variation Caused by Effect of Adjacent Lines, Proc. of the 15th IEEE Workshop on RTL and High Level Testing, 49-53, Nov. 2014. (Summary) Small delay faults caused by the resistive opens may induce the incorrect operation in present ICs. The small delay is hard to detect since it is difficult to distinguish faulty effect from process variations. Coupling capacitances have greater effect on the faulty circuit than that of the normal circuit. In this paper, we present a procedure for generating test pattern pairs for the resistive open faults by SAT-based ATPG. The difference of the path delay between test pattern pairs is used to detect the resistive open fault. Experimental results for some benchmarks are shown to our proposed method. Furthermore, to estimate a difference of path delay between pattern pairs, we utilize an open fault simulator.
65.	Masaki Hashizume, Yudai Shiraishi, Hiroyuki Yotsuyanagi, Hiroshi Yokoyama, Tetsuo Tada and Shyue-Kung Lu : Threshold Setting of Electrical Test Method for Open Defects at Data Bus in 3D SRAM IC, Proc. of the 15th IEEE Workshop on RTL and High Level Testing, 64-68, Nov. 2014. (Summary) A Threshold setting method of an electrical test method is proposed for detecting an open defect occurring at a data bus of a 3D SRAM IC. Targeted defects are a hard open defect and a soft one in a data bus. The test method is based on supply current of the IC. The threshold setting method is evaluated by some experiments for a circuit made of an SRAM IC on a printed circuit board. The experimental results reveal us that threshold values of the test method should be prepared for each of data buses of memories accessed in the tests and the data stored in them.
66.	Kousuke Nambara, Shoichi Umezu, Hiroyuki Yotsuyanagi, Masaki Hashizume and Shyue-Kung Lu : Threshold Value Estimation of Electrical Interconnect, Proc. of IEEE CPMT Symposium Japan 2014, 158-161, Nov. 2014. (Summary) An estimation method of a threshold value for electrical interconnect tests is proposed for detecting open defects at interconnects between dies in a 3D IC. Threshold values of a circuit made of our prototyping IC on a printed circuit board are derived by the estimation method. The results show us that resistive open defects whose resistance is larger than 16.1Ω can be detected with a threshold value estimated by the method. (Link to Publication Site) ● Publication site (DOI): 10.1109/ICSJ.2014.7009634 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-84922827098 (DOI: 10.1109/ICSJ.2014.7009634, Elsevier: Scopus)
67.	Hiroyuki Yotsuyanagi, Hiroki Sakurai and Masaki Hashizume : Delay Line Embedded in Boundary Scan for Testing TSVs, Fifth IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, Seattle, Oct. 2014. (Summary) In this paper, we propose a test method that utilizes a time-to-digital converter (TDC) embedded in boundary-scan design to detect an excessive delay occurred at interconnects in 3D-IC. The boundary scan cells are used as the delay line in the lower die to provide the input transition to the upper die. The input transition is delayed by delay elements and is captured at the boundary scan cells in the upper die. The proposed boundary scan design is implemented in an experimental chip and is examined to evaluate the feasibility to detect delay at TSVs in 3D ICs.
68.	Masaki Hashizume, Shohei Suenaga and Hiroyuki Yotsuyanagi : A Built-in Test Circuit for Detecting Open Defects by IDDT Appearance Time in CMOS ICs, Proc. of the 3rd International Conference on Design and Concurrent Engineering, Sep. 2014.
69.	Yudai Shiraishi, Masaki Hashizume, Hiroyuki Yotsuyanagi, Tetsuo Tada and Shyue-Kung Lu : Electrical Test Method of Open Defects at Data Buses in 3D SRAM IC, Proc. of International Conference on Electronics Packaging 2014, 235-238, Apr. 2014. (Summary) An electrical test method is proposed for detecting an open defect occurring at a data bus of a 3D SRAM IC. Targeted defects are a hard open defect and a soft one in a data bus. The test method is based on supply current of the IC. There is no need to add a circuit for the test method to an original circuit. Feasibility of the tests is examined by some experiments for a circuit made of an SRAM IC on a printed circuit board. The experimental results show us that resistive open defects whose resistance is greater than 300 can be detected by the test method. (Link to Publication Site) ● Publication site (DOI): 10.1109/ICEP.2014.6826696 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-84903741590 (DOI: 10.1109/ICEP.2014.6826696, Elsevier: Scopus)
70.	Shoichi Umezu, Masaki Hashizume and Hiroyuki Yotsuyanagi : A Built-in Supply Current Test Circuit for Pin Opens in Assembled PCBs, Proceedings of International Conference on Electronics Packaging 2014, 227-230, Toyama, Apr. 2014. (Summary) In this paper, a built-in test circuit of electrical tests is proposed to detect pin opens of CMOS ICs. When a circuit is tested by the test method, current is made to flow through a targeted pin. An open defect is detected by means of the difference between the current of a defect-free circuit and the measured one. Feasibility of tests with the built-in supply current test circuit is examined by Spice simulation. It is shown that a pin open in a CMOS IC can be detected with the test circuit at a speed of 1MHz. (Keyword) Open / PCB / Test (Link to Publication Site) ● Publication site (DOI): 10.1109/ICEP.2014.6826694 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-84903709572 (DOI: 10.1109/ICEP.2014.6826694, Elsevier: Scopus)
71.	Akira Ono, Hiroyuki Yotsuyanagi and Masaki Hashizume : Pin Open Detection of BGA IC by Supply Current Testing, Proceedings of International Conference on Electronics Packaging 2014, 231-234, Toyama, Japan, Apr. 2014. (Summary) In this paper, we propose a test method for detecting pin opens of CMOS logic ICs in assembled PCBs. The test method is based on supply current of a circuit under test which flows when a time-varying signal is provided to a targeted pin with a test probe as a stimulus. Test signal's amplitude is less than VDD. Test vector generations are not needed for the tests. In the test, the test probe also can be checked simultaneously. The test can be used on devices such as BGA ICs which solder parts are hidden from a field of view. We show by some experiments that pin opens of BGA ICs can be detected by the supply current test method. (Keyword) Open / PCB / Test (Link to Publication Site) ● Publication site (DOI): 10.1109/ICEP.2014.6826695 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-84903736715 (DOI: 10.1109/ICEP.2014.6826695, Elsevier: Scopus)
72.	Shohei Suenaga, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu and Zvi Roth : DFT for Supply Current Testing to Detect Open Defects at Interconnects in 3D ICs, Proc. of IEEE Electrical Design of Advanced Packaging & Systems (EDAPS) Symposium, 60-63, Nara, Dec. 2013. (Summary) In this paper, a Design-for-Testability method is proposed to detect an open defect occurring at an interconnect between dies in a 3D IC. The open defect is detected by means of a supply current flowing whenever a time-varying voltage signal is provided to the targeted interconnect as a test input stimulus. Feasibility of the test method is examined by targeted experiments and circuit simulations. It is shown that an open defect in a testable designed IC is capable of being detected by measuring the supply current of the IC. (Link to Publication Site) ● Publication site (DOI): 10.1109/EDAPS.2013.6724389 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/EDAPS.2013.6724389 (DOI: 10.1109/EDAPS.2013.6724389)
73.	Jun Yamashita, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yoshinobu Higami and Hiroshi Takahashi : On SAT-based Test Generation for Observing Delay Variation Caused by a Resistive Open Fault and Its Adjacent Lines, Digest of Papers of the 14-th IEEE Workshop on RTL and High Level Testing, IV.2.F-1-IV.2.F-6, Yilan,Taiwan, Nov. 2013. (Summary) Testing small delay fault is becoming more important in recent ICs. Especially when small delay caused by a resistive open, a delay size is affected by the signal transition of the adjacent lines. In this paper, we present a procedure for detecting delay faults by the difference of the path delay between test pattern pair. To increase the difference of the path delay, the test pattern pair assign the signal transition to as many adjacent lines as possible. To determine the set of adjacent lines, we utilize the SAT-based method. Experimental results for some benchmarks are shown to our proposed method.
74.	Akira Ono, Masao Takagi, Hiroyuki Yotsuyanagi and Masaki Hashizume : Supply Current Test Method for Pin Open Defects in Assembled PCB Circuits, Digest of Papers of the 14-th IEEE Workshop on RTL and High Level Testing, I.3.S-1-I.3.S-4, Yilan,Taiwan, Nov. 2013. (Summary) In this paper, we propose a test method for detecting pin opens of CMOS logic ICs in assembled PCBs. The test method is based on supply current of a circuit under test which flows when a time-varying signal is provided to a targeted pin with a test probe as a stimulus. We show by some experiments that pin opens of BGA ICs can be detected by the supply current test method.
75.	Shoichi Umezu, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu and Zvi Roth : Feasibility of Interconnect Tests of Open Defects in a 3D IC with a Built-in Supply Current Test Circuit, Digest of Papers of the 14-th IEEE Workshop on RTL and High Level Testing, I.1.F-1-I.1.F-5, Yilan,Taiwan, Nov. 2013. (Summary) We have proposed a supply current test method and a built-in test circuit to detect open defects occurring at interconnects between dies in a 3D IC. In the test circuit, IEEE 1149.1 test architecture is used to provide a test vector to a targeted interconnect. In this paper, it is examined whether open defects can be detected by some experiments for a printed circuit board made of a prototype IC in which the built-in test circuit is implemented. The experimental results show us that resistive open defects of greater than 1kΩ and capacitive ones of smaller than 1nF can be detected at a test speed of 1MHz.
76.	Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Hiroyuki Yotsuyanagi, Masaki Hashizume and K. Kewal Saluja : Diagnosing Resistive Open Faults Using Small Delay Fault Simulation, Proc.of IEEE 22th Asian Test Symposium, 79-84, Yilan,Taiwan, Nov. 2013. (Summary) Modern high performance, high density integrated circuits use a very large number of metal layers, necessitating the need to deal with the problem of resistive open defects. Resistive opens often manifest as and are modeled as small delay faults. Furthermore, in deep sub-micron technologies, it is known that the additional delay of a line with resistive open fault is not only a function of the resistant of the faulty line but it is also dependent on the signal transition(s) on its adjacent lines. In this paper, we propose an efficient simulation method to simulate small delay faults and we use this simulator to diagnose resistive open faults. The fault simulator developed by us simulates all delay faults for one signal line simultaneously. This information is then used to deduce the candidate faulty lines in two steps. Experimental results for ISCAS'89 benchmark circuits show that by using the method proposed by us the faulty lines can be identified correctly in most cases. (Link to Publication Site) ● Publication site (DOI): 10.1109/ATS.2013.23 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/ATS.2013.23 (DOI: 10.1109/ATS.2013.23)
77.	Masaki Hashizume, Tomoaki Konishi, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Testable Design for Electrical Testing of Open Defects at Interconnects in 3D ICs, Proc.of IEEE 22th Asian Test Symposium, 13-18, Yilan,Taiwan, Nov. 2013. (Summary) A testable design method for electrical testing is proposed in this paper to detect open defects occurring at interconnects between dies in a 3D IC and locate the defective interconnects. An IEEE 1149.1 test circuit is utilized to provide a test input vector to a targeted interconnect in the electrical tests. Feasibility of the electrical tests is evaluated by Spice simulation and some experiments with a prototyping IC. It is shown by the experiments that an open defect can be detected at a test speed of 1MHz. (Link to Publication Site) ● Publication site (DOI): 10.1109/ATS.2013.13 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/ATS.2013.13 (DOI: 10.1109/ATS.2013.13)
78.	Ei Haraguchi, Masaki Hashizume, Katsuya Manabe, Hiroyuki Yotsuyanagi, Tetsuo Tada, Shyue-Kung Lu and Zvi Roth : Reduction Method of Number of Electromagnetic Simulation Times for Estimating Output Voltage at Hard Open TSV in 3D IC, Proc. of IEEE CPMT Symposium Japan(ICSJ2013), 251-254, Kyoto, Nov. 2013. (Summary) An estimation method of quiescent output voltage of a defective TSV is proposed at which a hard open defect occurs in a 3D IC. The method enables us to reduce the number of times of 3D electromagnetic simulation. (Link to Publication Site) ● Publication site (DOI): 10.1109/ICSJ.2013.6756128 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-84897487243 (DOI: 10.1109/ICSJ.2013.6756128, Elsevier: Scopus)
79.	Shohei Suenaga, Masaki Hashizume, Hiroyuki Yotsuyanagi, Tetsuo Tada and Shyue-Kung Lu : Built-in IDDT Appearance Time Sensor for Detecting Open Faults in 3D IC, Proc. of IEEE CPMT Symposium Japan(ICSJ2013), 247-250, Kyoto, Nov. 2013. (Summary) A built-in sensor is proposed for detecting open faults in a 3D IC by means of appearance time of dynamic supply current. It is shown by Spice simulation that they can be detected with the sensor. (Link to Publication Site) ● Publication site (DOI): 10.1109/ICSJ.2013.6756127 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-84897567378 (DOI: 10.1109/ICSJ.2013.6756127, Elsevier: Scopus)
80.	Hiroki Sakurai, Hiroyuki Yotsuyanagi, Masanori Nakamura and Masaki Hashizume : Time-to-Digital Converter Embedded in Boundary-Scan Circuit and Its Application to 3D iC Testing, International Test Conference 2013, PO30, Anaheim, Sep. 2013. (Summary) In this study, we propose a test method that utilizes a time-to-digital converter (TDC) embedded in boundary-scan design to estimate the excessive delay occurs at interconnects in 3D-IC. The boundary scan cells are used as an the input generation block in the lower die and as a delay detection block in the upper die. The other testing method is also proposed to utilize the effect of adjacent TSVs to enhance the fault effects.
81.	Shoichi Umezu, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Testability of Open Defects at Interconnections in 3D ICs with a Built-in Test Circuit for Supply Current Testing, International Test Conference 2013, PO29, Anaheim, Sep. 2013. (Summary) We proposed a supply current test method and the DFT one for detecting open defects between dies in 3D ICs[1]. The test method utilizes an IEEE 1149.1 test mechanism to provide test vectors to interconnects between dies. We present feasibility analysis results of the tests obtained by some experiments in a PCB circuit made of our testable designed IC.
82.	Akira Ono, Hiroyuki Yotsuyanagi, Masao Takagi and Masaki Hashizume : Open Defect Detection in Assembled PCBs by Supply Current Testing with Electrodes Embedded inside ICs, Proceedings of ICEP2013, 451-456, Osaka, Japan, Apr. 2013. (Keyword) Open / Assembled PCB / Test
83.	Masaki Hashizume, Masatake Akutagawa, Shyue-Kung Lu and Hiroyuki Yotsuyanagi : Electrical Test Method of Open Defects at Bi-directional Interconnects in 3D ICs, Proceedings of ICEP2013, 13-18, Osaka, Japan, Apr. 2013. (Keyword) Open / 3D IC / Test / TSV
84.	(名) Widianto, Hiroyuki Yotsuyanagi and Masaki Hashizume : Size Reduction of a Built-in Test Circuit for Locating Open Interconnects in 3D ICs, Proc. of International Conference on Electronics, Information and Communication, 302-303, Bali, Indonesia, Feb. 2013. (Summary) In this paper, a built-in test circuit with a test selector is proposed to detect open defects at interconnects between dies in a 3D IC. The test selector is used to select which interconnects will be tested. An inverter gate is used as open sensors for detecting open defects. An AC voltage signal is provided to targeted interconnects and open sensors. Feasibility of tests is examined by Spice simulation. The simulation results show that targeted interconnects can be selected and also open defect can be detected.
85.	(名) Widianto, Hiroyuki Yotsuyanagi, Akira Ono, Masao Takagi, Zvi Roth and Masaki Hashizume : A Built-in Electrical Test Circuit for Interconnect tests in Assembled PCBs, Proc. of IEEE CPMT Symposium Japan 2012, 201-204, Kyoto, Dec. 2012. (Summary) In this paper, a built-in electrical test circuit is proposed to detect an open defect at an interconnect between a land in a printed circuit board and an IC. An inverter gate is used as an open sensor in the test circuit. An AC voltage signal is provided to a targeted interconnect and the sensor as a test input signal to detect the defect. The defect is detected by means of supply current of the sensor. We examine by Spice simulation whether open defects can be detected with the test circuit. The results reveal us that an open defect can be detected at a test speed of 1 MHz for each interconnect. (Link to Publication Site) ● Publication site (DOI): 10.1109/ICSJ.2012.6523422 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/ICSJ.2012.6523422 (DOI: 10.1109/ICSJ.2012.6523422)
86.	Jun Yamashita, Hiroyuki Yotsuyanagi, Masaki Hashizume and Kozo Kinoshita : On Detectability Analysis of Open Faults Using SAT-based Test Pattern Generation Considering Adjacent Lines, Digest of Papers of the 13-th IEEE Workshop on RTL and High Level Testing, 2.1.1-2.1.6, Niigata, Nov. 2012. (Summary) The floating line caused by an open fault is difficult to test since its voltage is unpredicted and depends on the voltage at the adjacent lines. The fault effect can be easily detected if a test pattern provides the opposite logic value to most of the adjacent lines. We define detection probability for test pattern to estimate how much preferable logic values the test pattern assigns to adjacent lines. This paper proposes a procedure for testing open faults with high detection probability. Experimental results for some benchmarks are also shown to prove the effectiveness of our procedure.
87.	Masaki Hashizume, Shohei Kondo, Ei Haraguchi, Hiroyuki Yotsuyanagi, Tetsuo Tada and Zvi Roth : Output Voltage Estimation Method of Hard Open TSV in 3D ICs, Digest of Papers of the 13-th IEEE Workshop on RTL and High Level Testing, 6.1.1-6.1.5, Niigata, Nov. 2012. (Summary) In this paper, we propose a method to estimate output voltage of a defective TSV at which a hard open defect occurs in a 3D IC. The voltage is estimated by an approximate function that is extracted from 3D magnetic simulation results of a targeted layout. The estimation precision is evaluated for a layout made of 10 TSVs inserted a hard open defect. The result shows us that output voltage of a defective TSV in the layout can be estimated within an error rate of 4.1%.
88.	Masaki Hashizume, Tomoaki Konishi and Hiroyuki Yotsuyanagi : Electrical Interconnect Testing of Open Defects in Assembled PCBs Utilizing IEEE 1149.1 Test Mechanism, International Test Conference 2012, PO1, Anaheim, Nov. 2012. (Summary) We propose an electrical test method for detecting open defects between ICs and PCBs. The test method utilizes IEEE 1149.1 test mechanism to provide test vectors to each interconnect between an IC and a PCB. The test method requests us to modify ESD input protection circuits. However, hard open defects and resistive ones can be detected by the test method. Feasibility of the testing is examined by some experiments. The results show us that hard open defects and resistive ones of larger than 100Ω will be detected in a test speed of 20MHz and also defective interconnects will be located by the test method.
89.	Tomoaki Konishi, Hiroyuki Yotsuyanagi and Masaki Hashizume : A Built-in Test Circuit for Supply Current Testing of Open Defects at Interconnects in 3D ICs, Proc. of 4-th Electronics System Integration Technologies Conference(ESTC 2012), PA21.1_1-PA21.1_6, Amsterdam, Sep. 2012. (Summary) In this paper, a built-in test circuit is proposed to detect and locate open defects occurring at interconnects between dies in a 3D IC by means of the quiescent supply current. In the test circuit, IEEE 1149.1 test architecture is used to provide a test vector to a targeted interconnect. Testability of the testing with the test circuit is evaluated by Spice simulation. The simulation results show us that a hard open defect and a soft open one generating additional delay of 0.58nsec can be detected at a test speed of 100MHz. (Link to Publication Site) ● Publication site (DOI): 10.1109/ESTC.2012.6542127 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/ESTC.2012.6542127 (DOI: 10.1109/ESTC.2012.6542127)
90.	Takahashi Hiroshi, Higami Yoshinobu, Yamazaki Koji, Tsutsumi Toshiyuki, Hiroyuki Yotsuyanagi and Masaki Hashizume : Test Generation for Resistive Open Faults with Considering Adjacent Lines, Proc. of 2012 International Technical Conference on Circuits/Systems, Computers and Communications, P-T2-06-1-P-T2-06-4, Sapporo, Jul. 2012. (Summary) We propose an extended delay fault model where the size of the delay fault is affected by the signal transitions at the adjacent lines. We also propose a method for generating the test patterns for the resistive open faults under the launch-off-capture (LOC) test. From the experimental results, we demonstrated that the proposed method can generate the test patterns for resistive open faults that cannot be detected by the given test patterns for the transition faults.
91.	Shohei Suenaga, Hiroyuki Yotsuyanagi and Masaki Hashizume : A Built-in Sensor for IDDT Testing of CMOS ICs, Proc. of 2012 International Technical Conference on Circuits/Systems, Computers and Communications, E-M2-05-1-E-M2-05-4, Sapporo, Jul. 2012. (Summary) In this paper, a built-in sensor is proposed for detecting open defects on signal lines in CMOS logic circuits by IDDT testing. The test method is based on the appearance time of dynamic supply current that flows when a test input vector is provided to a circuit under test. Feasibility of tests with the sensor is examined by Spice simulation. The results show that open defects on signal lines in CMOS logic circuits can be detected with the sensor.
92.	Shingo Saijo, Hiroyuki Yotsuyanagi, Masaki Hashizume and Kozo Kinoshita : Testable Design of CMOS Image Pixel Circuits for Electrical Testing, Proc. of 2012 International Technical Conference on Circuits/Systems, Computers and Communications, D-W2-04-1-D-W2-04-4, Sapporo, Jul. 2012. (Summary) We propose a CMOS image pixel circuit that is designed so as to be tested by an electrical test method. The pixel circuit can be tested without a light source and test time reduction may be realized. We designed a CMOS image sensor module made of the pixel circuit and examined the testability by Spice simulation. The results show that 69% of our inserted open and short defects can be detected by our electrical test method.
93.	Tomoaki Konishi, Hiroyuki Yotsuyanagi and Masaki Hashizume : An Electrical Test Circuit for Detecting Interconnect Open Defects in 3D ICs, Proceedings of ICEP2012, 88-93, Tokyo, Japan, Apr. 2012. (Keyword) Open / 3D IC / Test / TSV
94.	Ei Haraguchi, Shohei Kondo, Katsuya Manabe, Hiroyuki Yotsuyanagi and Masaki Hashizume : Output Voltage of a Floating Metal Line Caused by a Neighboring Metal Line Bending at a Right Angle, Proc. RISP International Workshop on Nonlinear Circuit and Signal Processing, 233-236, Honolulu, Mar. 2012. (Summary) We analyzed faulty effects caused by a hard open defect at a metal line inside an IC with a 3D electromagnetic simulator. In our targeted layout, a metal line that runs in parallel to the defective one bends at a right angle. Also, we examined whether the faulty effects can be estimated from simulation results of a layout made of straight metal lines running in parallel. The result reveals us that since large fringing effect is caused by the bending metal line, faulty effects at an opened metal line in a layout should be estimate from simulation results of the layout.
95.	Yasuhiko Okada, Hiroyuki Yotsuyanagi and Masaki Hashizume : The Test Vector Compaction Considering Compatible Flip-Flops for BIST-Aided Scan Test, Proc. RISP International Workshop on Nonlinear Circuit and Signal Processing, 449-452, Honolulu, Mar. 2012. (Summary) In this paper, we propose the modified test vector compaction procedure for BIST-Aided Scan Test(BAST). In our method, test compaction is applied for test vectors even if a few bits in compatible flip-flops have conflicts to reduce the number of test vectors. We also show the effectiveness of our method by the experimental results for ISCAS 89 and ITC99 benchmark circuits.
96.	Hiroyuki Makimoto, Hiroyuki Yotsuyanagi and Masaki Hashizume : On Measuring Timing Slack Using Boundary Scan with Time-to-Digital Converter for Detecting Delay Faults, Proc. RISP International Workshop on Nonlinear Circuit and Signal Processing, 445-448, Honolulu, Mar. 2012. (Summary) This paper presents a new boundary scan architecture with time-to-digital converter(TDC) for detecting delay faults by measuring timing slack. In our boundary scan cells, flip-flops are utilized for both making a scan path and capturing circuit response. The architecture of the boundary scan design is proposed to detect delay from the other cores and chips or their interconnects. In this paper, we presents the boundary scan circuit modified from [15] for observing timing slack to reduce test application time. The proposed basic operation of the design is evaluated by simulation.
97.	Tomoaki Konishi, Hiroyuki Yotsuyanagi and Masaki Hashizume : Supply Current Testing of Open Defects at Interconnects in 3D ICs with IEEE 1149.1 Architecture, International 3D System Integration Conference, 8-2-1-8-2-6, Osaka, Feb. 2012. (Summary) In this paper, a supply current test method of 3D ICs is proposed to detect open defects occurring at interconnects between two dies in which IEEE 1149.1 architecture is implemented and locate the defective interconnects. Also, a testable design method is proposed for the test method and a testable designed IC is prototyped. Furthermore, testability of the test method is evaluated by some experiments with the prototyped IC and by Spice simulation. The simulation results show that an open defect can be detected within 10nsec which generates only additional delay of 0.7nsec. (Link to Publication Site) ● Publication site (DOI): 10.1109/3DIC.2012.6262968 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-84866875445 (DOI: 10.1109/3DIC.2012.6262968, Elsevier: Scopus)
98.	(名) Widianto, Hiroyuki Yotsuyanagi, Akira Ono, Masao Takagi and Masaki Hashizume : A Built-in Test Circuit for Open Defects at Interconnects between Dies in 3D ICs, International 3D System Integration Conference, P-2-31-1-P-2-31-5, Osaka, Feb. 2012. (Summary) In this paper, a built-in test circuit is proposed to detect open defects that occur at interconnects between dies inside 3D ICs. An inverter gate is used in the test circuit as an open sensor. Open defects are detected by means of supply current of the inverter gate flowing when an AC voltage signal is provided to targeted interconnects as a stimulus. The interconnect at which an open defect occurs can be located with the test circuit. Feasibility of tests with the test circuit is examined by circuit simulation. The results promise us that open defects can be detected and also defective interconnects can be located with the test circuit. (Link to Publication Site) ● Publication site (DOI): 10.1109/3DIC.2012.6263041 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-84866841641 (DOI: 10.1109/3DIC.2012.6263041, Elsevier: Scopus)
99.	Hiroyuki Yotsuyanagi, Hiroyuki Makimoto and Masaki Hashizume : A Boundary Scan Circuit with Time-to-Digital Converter for Delay Testing, Proc. 20th Asian Test Symposium, 539-544, New Delhi, Nov. 2011. (Summary) This paper presents a design-for-testability method for detecting delay faults. In order to observe the effect of small delay defects, we present modified boundary scan cells in which a time-to-digital converter (TDC) is embedded. In our boundary scan cells, flip-flops are utilized for both making a scan path and capturing circuit response. The architecture of the boundary scan design is proposed to detect delay from the other cores or chips or its interconnects. The basic operation of the design is evaluated by simulation and by experimental ICs. Experimental results show that the measurement of the transition delay can be achieved by the boundary scan design with the time-to-digital converter. (Link to Publication Site) ● Publication site (DOI): 10.1109/ATS.2011.63 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-84856203460 (DOI: 10.1109/ATS.2011.63, Elsevier: Scopus)
100.	Masaki Hashizume, Yutaka Hata, Hiroyuki Yotsuyanagi and Yukiya Miura : A Supply Current Testable Register String DAC of Decoder Type, Proc. of 11th International Symposium on Communications and Information Technologies, 58-63, China, Hangzhou, Oct. 2011. (Summary) In this paper, we propose a supply current testable resistor string DAC of decoder type whose area overhead is small and a supply current test method. Open defects and short ones in the DAC can be detected by the test method with about 50% of the exhausted test vectors. It is shown by some experiments that most of the targeted defects in our testable DACs of 4 and 8 bits can be detected by the test method. (Link to Publication Site) ● Publication site (DOI): 10.1109/ISCIT.2011.6092183 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/ISCIT.2011.6092183 (DOI: 10.1109/ISCIT.2011.6092183)
101.	Lee Heejin, Hiroyuki Yotsuyanagi, Sohn Kyungrak and Masaki Hashizume : Feasibility of Operating Point Estimation in Lighting Circuit with Measured I-V Characteristics of LEDs, Proc. of 2011 International Technical Conference on Circuits/Systems, Computers and Communications, 1026-1029, Gyeongju, Korea, Jun. 2011. (Summary) We proposed a numerical analysis method for estimating an operating point of an LED lighting circuit that is based on measured DC characteristics of LEDs used in it. In this paper, we examine feasibility of the estimation of operating points of LED lighting circuits. The results show us that this analysis method can be used for designing LED lighting circuits.
102.	Yoshihiko Miyamori, Hiroyuki Yotsuyanagi and Masaki Hashizume : Practical Testability of Supply Current Testable DACs of Resistor Type, Proc. of 2011 International Technical Conference on Circuits/Systems, Computers and Communications, 1015-1018, Gyeongju, Korea, Jun. 2011. (Summary) We proposed supply current testable DACs of resistor string type. In order to examine practical testability of the DACs, we examine testability of 3 bits and 8 bits DACs by TR analysis of a circuit simulator. The results show us that all of defects in MOSs can not be detected by our test method but the test method can be used in the first stage of production tests of DACs owing to the short test time.
103.	Tomoaki Konishi, Hiroyuki Yotsuyanagi and Masaki Hashizume : Feasibility of Electrical Testing for Lead Opens of QFP ICs, Proc. of 2011 International Technical Conference on Circuits/Systems, Computers and Communications, 688-691, Gyeongju, Korea, Jun. 2011. (Summary) In this paper, an electrical test method is proposed to detect open leads of CMOS QFP ICs. When a circuit is tested, current is made to flow through one of targeted leads. An open defect is detected by means of the difference between the current of a defect-free circuit and the measured one. Feasibility of tests with the test method is examined by some experiments. It is shown that an open lead in a CMOS QFP IC can be detected by the test method at a speed of 1MHz.
104.	Shohei Kondo, Hiroyuki Yotsuyanagi and Masaki Hashizume : Faulty Effect of Soft Open Defect in TSV Caused by Logic Values of Neighboring TSVs, Proc. of 2011 International Technical Conference on Circuits/Systems, Computers and Communications, 692-695, Gyeongju, Korea, Jun. 2011. (Summary) In this paper, faulty effect of a soft open defect in Through Silicon Via(TSV) that is caused by logic values of the neighboring TSVs is examined with a 3 dimensional electromagnetic simulator. The results show us that propagation delay depends on the size of an open defect and the logic signals of the neighboring TSVs. Also, when a soft open defect caused by a void occurs in a TSV, logical errors can be generated.
105.	Katsuya Manabe, Hiroyuki Yotsuyanagi, Toshiyuki Tsutsumi, Koji Yamazaki, Yoshinobu Higami, Hiroshi Takahashi, Yuzo Takamatsu and Masaki Hashizume : Estimation of Faulty Effects Caused by a Clack at an Interconnect Line in 90nm ICs, Proceedings of ICEP2011, 737-742, Nara, Japan, Apr. 2011. (Keyword) Open / CMOS / Test
106.	Shohei Kondo, Hiroyuki Yotsuyanagi and Masaki Hashizume : Fault Analysis of Soft Open Defects in TSVs with Electromagnetic Simulator, Proceedings of ICEP2011, 727-731, Nara, Japan, Apr. 2011. (Keyword) Open / 3D IC / Test / TSV
107.	Masaki Hashizume, Yutaka Hata, Hiroyuki Yotsuyanagi and Yukiya Miura : A Supply Current Testable DAC of Resistor String Type, Proc. RISP International Workshop on Nonlinear Circuit and Signal Processing, 13-16, TianJin,China, Mar. 2011.
108.	Masashi Ishikawa, Hiroyuki Yotsuyanagi and Masaki Hashizume : Test Data Reduction for BIST-aided Scan Test Using Compatible Flip-flops and Shifting Inverter Code, Proc. of 19th Asian Test Symposium, 163-166, Shanghai, Dec. 2010. (Summary) In this paper, a method for reducing test data volume of BIST-aided scan test (BAST) is proposed. In our BAST method, scan chains are ordered using compatible flip-flops to reduce the conflicting bits between ATPG pattern and random pattern obtained by LFSR. The inverter block in BIST-aided scan architecture is modified for shifting inverter code such that the random pattern produced by LFSR has less conflicting bits with ATPG patterns when providing the test pattern to the scan chains. The experimental results show the method can reduce the test data volume than the previous method. (Link to Publication Site) ● Publication site (DOI): 10.1109/ATS.2010.37 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/ATS.2010.37 (DOI: 10.1109/ATS.2010.37)
109.	Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi and Masaki Hashizume : A Method for Diagnosing Resistive Open Faults with Considering Adjacent Lines, Proc. of 10th International Symposium on Communications and Information Technologies, 609-614, Tokyo, Oct. 2010. (Summary) It is believed that resistive open faults can cause small delay defects at wires, contacts, and/or vias of a circuit. However, it remains to be elucidated whether any methods could diagnose resistive open faults. We propose a method for diagnosing resistive open faults by using a diagnostic delay fault simulation with the minimum detectable delay fault size. We also introduce a fault excitation function for the resistive open fault to improve the accuracy of the diagnostic result. The fault excitation function for the resistive open fault can determine a size of an additional delay at a faulty line with considering the effect of the adjacent lines. We demonstrated that the proposed method is capable of identifying fault locations for the resistive open fault with a small computation cost. (Link to Publication Site) ● Publication site (DOI): 10.1109/ISCIT.2010.5665061 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/ISCIT.2010.5665061 (DOI: 10.1109/ISCIT.2010.5665061)
110.	Katsuya Manabe, Yuichi Yamada, Hiroyuki Yotsuyanagi, Toshiyuki Tsutsumi, Koji Yamazaki, Yoshinobu Higami, Hiroshi Takahashi, Yuzo Takamatsu and Masaki Hashizume : Output Voltage Estimation of a Floating Interconnect Line Caused by a Hard Open in 90nm ICs, Proc. of 10th International Symposium on Communications and Information Technologies, 603-608, Tokyo, Oct. 2010. (Summary) Faulty effects caused by a hard open defect at an interconnect line in a 90nm CMOS IC are analyzed by device simulation in this paper. The simulation results reveal us that output voltage of the floating interconnect line is obtained as linear sum of effects from logic signals of the adjacent interconnect lines and the defective one. Also, an estimation model of voltage at the floating interconnect line is proposed. Feasibility of the estimation is examined in this paper. The result shows us that the voltage can be estimated within error of about 0.03V. (Link to Publication Site) ● Publication site (DOI): 10.1109/ISCIT.2010.5665062 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/ISCIT.2010.5665062 (DOI: 10.1109/ISCIT.2010.5665062)
111.	Lee Heejin, Hiroyuki Yotsuyanagi and Masaki Hashizume : Lighting Circuit Analysis Method with Measured I-V Characteristics of LEDs, Proc. of 2010 International Technical Conference on Circuits/Systems, Computers and Communications, 1262-1265, Pattaya,Thailand, Jul. 2010.
112.	Masaki Hashizume, Shohei Kondo and Hiroyuki Yotsuyanagi : Possibility of Logical Error Caused by Open Defects in TSVs, Proc. of 2010 International Technical Conference on Circuits/Systems, Computers and Communications, 907-910, Pattaya,Thailand, Jul. 2010.
113.	Masaki Hashizume, Kazuya Nakaminami, Hiroyuki Yotsuyanagi, Yukunori Nakajima and Kozo Kinoshita : Current-Based Testable Design of Level Shifters in Liquid Crystal Display Drivers, Proc. of 2010 15th European Test Symposium, 262, Prague, May 2010. (Summary) We propose a testable design method of level shifters inside a liquid crystal display driver IC. The design method enables us to detect open defects in level shifters by supply current testing that are difficult to be tested by voltage testing. Also, we show by circuit simulation that more resistive open defects may be detected by supply current testing than voltage testing, if the level shifter is designed by using the proposed DFT method. (Link to Publication Site) ● Publication site (DOI): 10.1109/ETSYM.2010.5512731 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/ETSYM.2010.5512731 (DOI: 10.1109/ETSYM.2010.5512731)
114.	Masaki Hashizume, Kenichi Uchikura, Akira Ono, Hiroyuki Yotsuyanagi and Masao Takagi : Built-in Test Circuit for Opens at Interconnects between Dies inside SiPs, Proceedings of ICEP2010, 705-710, Sapporo, Japan, Apr. 2010. (Keyword) Open / SiP / Test
115.	Shohei Kondo, Katsuya Manabe, Masao Takagi, Hiroyuki Yotsuyanagi and Masaki Hashizume : Faulty Effects on Logic Signal of a Hard Open Via from Adjacent Ones, Proceedings of ICEP2010, 711-715, Sapporo, Japan, Apr. 2010. (Keyword) Open / CMOS / Test
116.	Ryota Kuribayashi, Hiroyuki Yotsuyanagi and Masaki Hashizume : Test Generation for Open Faults Considering the Effects of Adjacent Lines, 10th IEEE Workshop on RTL and High Level Testing (WRTLT09), 61-66, Hong Kong, Nov. 2009. (Summary) Open faults are difficult to test since the voltage at the floating line is unpredicted and depends on the voltage at the adjacent lines. This paper presents a procedure to generate test pattern for open faults considering the effects of adjacent lines. The experimental results for the benchmark circuits are shown.
117.	Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi and Masaki Hashizume : New Class of Tests for Open Faults with Considering Adjacent Lines, Proc. of 18th Asian Test Symposium, 305-310, Taichung, Taiwan, Nov. 2009. (Summary) Under the open fault model with considering the effects of adjacent lines, the open fault excitation is depended on the tests. Therefore, the layout information is needed to generate a test for an open fault. However, it is not easy to extract accurate circuit parameters of a deep sub-micron LSI. We have already proposed an open fault model without using the accurate circuit parameters. In this paper, we propose a new class of the pair of tests for the open fault called Ordered Pair of Tests (OPT). OPT is generated based on the fault excitation function as a threshold function of the adjacent lines. Also we propose a method for generating OPTs from the given stuck-at fault test set. The proposed method generates OPTs using only information about adjacent lines of the target open fault. Experimental results show that the proposed method can generate the OPTs for the open faults with high fault coverage. (Link to Publication Site) ● Publication site (DOI): 10.1109/ATS.2009.39 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/ATS.2009.39 (DOI: 10.1109/ATS.2009.39)
118.	Isao Tsukimoto, Hiroyuki Yotsuyanagi and Masaki Hashizume : Feasibility of IDDQ Tests for Shorts in Deep Submicron ICs, Proc. of 2009 International Technical Conference on Circuits/Systems, Computers and Communications, 794-796, Jeju,Korea, Jul. 2009. (Summary) Quiescent supply current (IDDQ) in deep submicron ICs is derived by circuit simulation and feasibility of IDDQ tests is examined for short defects in ICs fabricated with 0.18 um CMOS process. The results show that IDDQ of each gate depends on input logic values and that shorts can be detected by IDDQ testing if some process variation are small.
119.	Toshiyuki Tsutsumi, Yasuyuki Kariya, Masaki Hashizume, Hiroyuki Yotsuyanagi, Koji Yamazaki, Yoshinobu Higami, Hiroshi Takahashi and Yuzo Takamatsu : Preliminary Analysis of Interconnect Full Open Faults using TEG chips, Proc. of 2009 International Technical Conference on Circuits/Systems, Computers and Communications, 679-682, Jeju, Korea, Jul. 2009. (Summary) As LSIs are scale-down, there is an increasing need to take measures against open faults. However, no practical model for open faults exists at present. Therefore, we fabricated Test Element Group (TEG) chips that intentionally incorporated full (complete) open defects and electrically measured the output signals relevant to its defective lines in order to create a new model for open fault behavior. This study reveals the effect boundary of adjacent signal lines on the line containing the full open defect for the first time using the TEG chips.
120.	Masaki Hashizume, Yutaka Hata, Hiroyuki Yotsuyanagi and Yukiya Miura : Current Testable Design of Resistor String DACs for Short Defects, Proc. of 2009 International Technical Conference on Circuits/Systems, Computers and Communications, 428-431, Jeju,Korea, Jul. 2009. (Summary) In this paper, we propose a DFT method for resistor string DACs that enables us to test them easily by supply current test method. The targeted defects are shorts in the DACs. It is shown by some experiments that all of the targeted defects in a DAC designed with the DFT method can be detected with a smaller number of test vectors.
121.	Akira Ono, Hiroyuki Yotsuyanagi, Masao Takagi and Masaki Hashizume : Open Lead Detection of QFP ICs Using Logic Gates as Open Sensors, Proc. of 2009 International Conference on Electronics Packaging, 434-439, Kyoto,Japan, Apr. 2009.
122.	Hiroyuki Yotsuyanagi, Masaki Hashizume, Toshiyuki Tsutsumi, Koji Yamazaki, Takashi Aikyo, Yoshinobu Higami, Hiroshi Takahashi and Yuzo Takamatsu : Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC, Proc. of 22nd International Conference on VLSI Design, 91-96, New Delhi, India, Jan. 2009. (Summary) Open faults are difficult to test since the voltage at the floating line is unpredicted and depends on the voltage at the adjacent lines. The modeling for open faults with considering adjacent lines has been proposed. In this work, the 90 nm IC is designed and fabricated to evaluate how the voltage at adjacent lines affect the defective line. The open fault macros with a transmission gate and with an intentional break are included in the IC. The nine lines are placed in parallel in three layers to observe the effect of the coupling capacitance when an open occurs. The benchmark circuits with the open fault macro are also included in the IC. The simulation and experimental results show that the relationship between the floating line and the adjacent lines. The experimental results are also compared with the open fault model that calculate the weighted sum of voltages at the adjacent lines. (Link to Publication Site) ● Publication site (DOI): 10.1109/VLSI.Design.2009.60 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/VLSI.Design.2009.60 (DOI: 10.1109/VLSI.Design.2009.60)
123.	Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi and Masaki Hashizume : A Novel Approach for Improving the Quality of Open Fault Diagnosis, Proc. of 22nd International Conference on VLSI Design, 85-90, New Delhi, India, Jan. 2009. (Summary) With the shrinking process technologies and the use of copper process, open defects on interconnect wires, contacts and vias often cause failure. Development of an efficient fault diagnosis method for open faults is desired. However, the diagnosis method for open faults has not been established yet. In this paper, we propose a novel approach for improving the diagnostic quality of open faults by introducing a threshold function in which the logical value of the line with open defect depends on the weighted logical values of its adjacent lines. By using the threshold function, we can deduce not only a faulty line but also an open defect site at the faulty line. Experimental results show that the proposed method can identify an exact faulty line in most cases with a very small computation cost. The proposed method can also identify the open defect site within 25%-length of the faulty line. (Link to Publication Site) ● Publication site (DOI): 10.1109/VLSI.Design.2009.53 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/VLSI.Design.2009.53 (DOI: 10.1109/VLSI.Design.2009.53)
124.	Masayuki Yamamoto, Hiroyuki Yotsuyanagi and Masaki Hashizume : Scan Chain Configuration for BIST-aided Scan Test using Compatible Scan Flip-flops, 9th Workshop on RTL and High Level Testing (WRTLT08), 99-104, Sapporo, Nov. 2008. (Summary) In this paper, the scan chain configuration for BIST-aided scan test for reducing test data and test application time is proposed. The scan flip-flops are arranged based on compatible set of flip-flops to attain less conflicts between the random pattern generated by LFSR and ATPG test pattern. The experimental results for some benchmark circuits are shown.
125.	Masaki Hashizume, Akihito Shimoura, Masahiro Ichimiya and Hiroyuki Yotsuyanagi : Test Circuit for Locating Open Leads of QFP ICs, IEEE 7-th International Board Test Workshop, Fort Collins, USA, Sep. 2008. (Summary) In this paper, a test circuit is proposed, with which open leads of CMOS QFP ICs are located without generating test input vectors. Open leads are located by means of supply current of the test circuit that flows when an AC voltage signal is provided to targeted leads with test probes as a stimulus. Also, a design method of the test circuit is proposed. It is examined by circuit simulation whether the test circuit will be designed by the design method. The result shows that an open lead in CMOS QFP ICs of 50 leads will be located with the test circuit.
126.	Yutaka Hata, Masaki Hashizume, Hiroyuki Yotsuyanagi and Yukiya Miura : Current Testble Design of Resistor String DACs for Open Defects, Proc. of 2008 International Technical Conference on Circuits/Systems, Computers and Communications, 1533-1536, Shimonoseki, Japan, Jul. 2008. (Summary) In this paper, a DFT method of resistor string digital-to-analog converters (DACs) is proposed so as to be tested fully by supply current testing. Targeted defects are opens in the DACs. Testability of opens in testable designed DACs is examined experimentally. The results show that all of the opens in an N-bits testable designed DAC will be detected with test vectors of about 2(N-1) by supply current testing.
127.	Akira Ono, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Masao Takagi and Masaki Hashizume : Open Lead Detection Based on Logical Change Caused by AC Voltage Signal Stimulus, Proc. of 2008 International Technical Conference on Circuits/Systems, Computers and Communications, 241-244, Shimonoseki,Japan, Jul. 2008. (Summary) In this paper, we propose a new test method for detecting an open lead which occurs when an IC is mounted on a printed circuit board. In the method, an open lead is detected by observing output logical change of an open lead detector. Since the test method is a vectorless test one, test generation and test input application are not needed. Testability of the test method is examined by some experiments. The results show that open leads of SSIs and LSIs will be detected by the method.
128.	Masaki Hashizume, Yuichi Yamada, Hiroyuki Yotsuyanagi, Toshiyuki Tsutsumi, Koji Yamazaki, Yoshinobu Higami, Hiroshi Takahashi and Yuzo Takamatsu : Fault Analysis of Interconnect Opens in 90nm ICs with Device Simulator, Proc. of 2008 International Technical Conference on Circuits/Systems, Computers and Communications, 249-252, Shimonoseki, Japan, Jul. 2008. (Summary) In this paper, faulty effects of interconnect opens in logic ICs fabricated with a 90nm CMOS process are analyzed by device simulation. In the analysis, it is examined whether a logical error can be caused at an opened input signal line by logic signals of the neighboring signal lines. The simulation results suggest us that a logical error may occur at an interconnect surrounding by 8 interconnects if the interconnects are longer than 5μm and the width of an open defect is greater than 2.0nm.
129.	Akira Ono, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Masao Takagi and Masaki Hashizume : Test Method for DetectingOpen Leads of Low Voltage LSIs, Proceedings of ICEP2008, 457-462, Tokyo, Jun. 2008. (Keyword) Lead Open / CMOS / PCB Test
130.	Masaki Hashizume, Masahiro Ichimiya, Akira Ono and Hiroyuki Yotsuyanagi : Test Circuit for Vectorless Open Lead Detection of CMOS ICs, IEEE 6-th International Board Test Workshop, Fort Collins, Oct. 2007. (Summary) In this paper, a test circuit for a test method is proposed, with which open leads of CMOS logic ICs are detected without generating test input vectors. Open leads are detected by means of supply current of the test circuit that flows when an AC voltage signal is provided to targeted leads with test probes as a stimulus. It is examined by some experiments whether open leads will be detected with the test circuit. The empirical results show that open leads of CMOS ICs will be detected within 5μsec after attachment of test probes to targeted leads.
131.	Masaki Hashizume, Yuuki Ogata, Mitsuru Tojo, Masahiro Ichimiya and Hiroyuki Yotsuyanagi : Interconnect Open Detection by Supply Current Testing under AC Electric Field Application, IEEE International Workshop on Current and Defect Based Testing, 25-29, Santa Clara, Oct. 2007. (Summary) In this paper, it is examined by some experiments whether interconnect opens are detected by a supply current test method. The test method is based on supply current of a targeted IC that flows when AC electric field is provided outside of the IC. ICs fabricated with 0.35um CMOS process, into which open defects are inserted, are used in the experiments. The experimental results show that interconnect opens are detected by the test method except for opened interconnect lines coupled strongly with the neighboring ones. Also, it is shown that by embedding an electrode, which is used to generate AC electric field, inside a targeted IC, interconnect opens will be detected with smaller AC voltage supplied to the electrode.
132.	Hiroyuki Yotsuyanagi, Takeshi Iihara and Masaki Hashizume : On SoC Testing Using Multiple Scan Chains with Scan Tree Configurations, 8th Workshop on RTL and High Level Testing (WRTLT07), 151-156, Beijing, Oct. 2007. (Summary) In this paper, we propose a method to configure multiple scan chains for SoC testing. The method utilizes two scan tree modes for each core: fully compatible mode and folding mode. Experimental results are obtained for the case that three ISCAS 89 and ITC99 benchmark circuits are assumed as the cores. Test application time required for providing the test pattern can be reduced with the method.
133.	Masaki Hashizume, Yutaka Hata, Tomomi Nishida, Hiroyuki Yotsuyanagi and Yukiya Miura : Current Testable Design of Resistor String DACs, Proc. of 16th Asian Test Symposium, 399-403, Beijing, Oct. 2007. (Summary) In this paper, a DFT method of resistor string digital-to-analog converters (DACs) is proposed so as to be tested fully by supply current testing. Targeted defects are opens and shorts in the DACs. Testability of a testable designed DAC is examined experimentally. The results show that shorts and opens in a testable designed DAC will be detected with a smaller number of test vectors by supply current testing. (Link to Publication Site) ● Publication site (DOI): 10.1109/ATS.2007.94 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/ATS.2007.94 (DOI: 10.1109/ATS.2007.94)
134.	Hiroshi Takahashi, Yoshinobu Higami, Shuhei Kadoyama, Takashi Aikyo, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi and Masaki Hashizume : Clues for Modeling and Diagnosing Open Faults with Considering Adjacent Lines, Proc. of 16th Asian Test Symposium, 39-44, Beijing, Oct. 2007. (Summary) Under the modern manufacturing technologies, the open defect is one of the significant issues to maintain the reliability of DSM circuits. However, the modeling and techniques for test and diagnosis for open faults have not been established yet. In this paper, we give an important clue for modeling an open fault with considering the affects of adjacent lines. Firstly, we use computer simulations to analyze the defective behaviors of a line with the open defect. From the simulation results, we propose a new open fault model that is excited depending on the logic values at the adjacent lines assigned by a test. Next, we propose a diagnosis method that uses the pass/fail information to deduce the candidate open fault. Finally, experimental results show that the proposed method is able to diagnose the open faults with good resolution. It takes about 6 minutes to diagnose the open fault on the large circuit (2M gates).
135.	Hiroshi Takahashi, Yoshinobu Higami, Toru Kikkawa, Takashi Aikyo, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi and Masaki Hashizume : Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines, IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, 243-251, Rome, Italy, Sep. 2007. (Summary) In order to ensure high quality of DSM circuits, testing for the open defect in the circuits is necessary. However, the modeling and techniques for test generation for open faults have not been established yet. In this paper, we propose a method for generating tests and diagnostic tests based on a new open fault model. Firstly, we show a new open fault model with considering adjacent lines [9]. Under the open fault model, we reveal more about the conditions to excite the open fault. Next we propose a method for generating tests for open faults by using a stuck-at fault test with don't cares. We also propose a method for generating a diagnostic test that can distinguish the pair of open faults. Finally, experimental results show that (1) the proposed method is able to achieve 100% fault coverages for almost all benchmark circuits and (2) the proposed method is able to reduce the number of indistinguished open fault pairs. (Link to Publication Site) ● Publication site (DOI): 10.1109/DFT.2007.11 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/DFT.2007.11 (DOI: 10.1109/DFT.2007.11)
136.	Ono Akira, Masaki Hashizume, Masahiro Ichimiya and Hiroyuki Yotsuyanagi : Open Lead Detection of CMOS Logic Circuits by Low Pressure Probing, Proceedings of ICEP2007, 359-364, Tokyo, Apr. 2007. (Keyword) Lead Open / CMOS / PCB Test
137.	Eiji Tasaka, Masaki Hashizume, Seiichi Nishimoto, Hiroyuki Yotsuyanagi, Takahiro Oie, Ikuro Morita and Toshihiro Kayahara : At Speed Testing of Bus Interconnects in Microcomputers, 7th Workshop on RTL and High Level Testing (WRTLT06), 123-127, Fukuoka, Nov. 2006.
138.	Hiroyuki Yotsuyanagi, Tomohiko Nagashima and Masaki Hashizume : Test Time Reduction for Scan Circuits by Selection of a Flip-flop with Hold Operation, 7th Workshop on RTL and High Level Testing (WRTLT06), 81-85, Fukuoka, Nov. 2006. (Summary) This paper presents a test time reduction method for scan circuits. The method finds the last consecutive 0's and 1's in test vectors for a scan chain. To reduce the scan shifts one of the flip-flops in a scan chain is selected to hold the value to provide the last flip-flops on the chain.
139.	Masato Nakanishi, Masaki Hashizume, Hiroyuki Yotsuyanagi and Yukiya Miura : A BIC Sensor Capable of Adjusting IDDQ Limit in Tests, Proc. of 15th Asian Test Symposium, 69-74, Fukuoka, Nov. 2006. (Summary) A built-in-current sensor (BIC sensor) is proposed whose IDDQ limit is able to be adjusted in each IC test. IDDQ tests of identical IDDQ limit can be realized with the current sensor, even if process variation occurs in the sensor. Also, an IDDQ test method is proposed for ICs, in each of which the BIC sensor is implemented. It is shown by some experiments that IDDQ limit of 10mu A will be able to be set and IDDQ test results based on the limit will be obtained by adjusting the limit for each IC if size variation of MOSs in the BIC sensor is less than 50% (Link to Publication Site) ● Publication site (DOI): 10.1109/ATS.2006.260995 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/ATS.2006.260995 (DOI: 10.1109/ATS.2006.260995)
140.	Tojo Mitsuru, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Masaki Hashizume : Current Testing of Interconnect Opens between CMOS LSIs Having Scan Cells, IEEE International Workshop on Current and Defect Based Testing, 39-42, Santa Clara, Oct. 2006.
141.	Masaki Hashizume and Hiroyuki Yotsuyanagi : Test Circuit for Open Lead Detection of CMOS ICs Based on Supply Current, the IEEE European Board Test Workshop, Southampton, UK, May 2006. (Summary) In this paper, a test circuit is proposed for detecting open leads of CMOS logic ICs by means of supply current of a circuit under test. The circuit consists of a supply current measurement circuit and a test stimulus generator. The test stimulus generator is designed so that high speed test can be realized. Also, it is shown by some experiments that open leads of CMOS ICs will be detected at test speed of 1MHz with the test circuit.
142.	Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Open Lead Detection Based on Supply Current of CMOS Logic Circuits by AC Voltage Signal Application, Proceedings of ICEP2006, 147-152, Tokyo, Apr. 2006. (Keyword) Lead Open / CMOS / PCB Test
143.	Tomohiko Nagashima, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Test Time Reduction Method for Scan Design with Clock-Control DFT, Proc. RISP International Workshop on Nonlinear Circuit and Signal Processing, 441-444, Honolulu, Mar. 2006. (Summary) This paper presents a test generation method for sequential circuits. Our method utilizes the test vectors obtained for full scan design. In this parer, we combined two design-for- testability(DFT) method:one is transparent scan, the other is clock-control DFT. The simulation results for some benchmark circuits are shown.
144.	Masaki Hashizume, Tomomi Nishida, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Yukiya Miura : Current Testable Design of Resistor String DACs, The IEEE International Workshop on Electronic Design, Test and Applications, 197-200, Kuala Lumpur, Malaysia, Jan. 2006. (Summary) In this paper, supply current testability is examined experimentally for opens and shorts in a general 3 bit resistor string digital/analog converter (DAC). The results show that all of the shorts and the opens are detected by supply current testing, while opens of the MOS switches are not detected. A DFT method for resistor string DACs is proposed in this paper to detect the opens by supply current testing. Also, testability of a resistor string DAC designed with the DFT method is examined. It is shown that all of the targeted shorts and opens in the testable designed DAC are detected by supply current testing. (Link to Publication Site) ● Publication site (DOI): 10.1109/DELTA.2006.28 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/DELTA.2006.28 (DOI: 10.1109/DELTA.2006.28)
145.	Tomohiko Nagashima, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Test Generation for Scan Circuits Using Random Selection of the Operations of Scan Flip-flops, 6th Workshop on RTL and High Level Testing (WRTLT05), 79-83, Harbin, China, Jul. 2005. (Summary) This paper presents a test generation method for scan circuits. In the proposed method control signals of scan flip-flops are treated as the same as the primary inputs. Our method utilizes the test vectors obtained for full scan design and apply the vectors repeatedly in the given order to achieve low test data volume. For each test vector, the operation of scan flip-flops is selected from one of the following: normal, scan and freeze operation. The simulation results for some benchmark circuits are shown.
146.	Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Electric Field for Detecting Open Leads in CMOS Logic Circuits by Supply Current Testing, Proc. of IEEE International Symposium on Circuits and Systems, 2995-2998, Kobe, May 2005. (Summary) Open leads are one type of defect occurring frequently when logic circuits are implemented on printed circuit boards (PCBs) with ICs. A powerful supply current test method has been proposed for detecting an open lead in a CMOS logic circuit. The method is based on the supply current of a circuit under test which flows when a time-varying electric field is supplied from the outside of the circuit. The paper proposes a time-varying electric field which enables us to detect open leads in a CMOS logic circuit with an inexpensive test setup. (Link to Publication Site) ● Publication site (DOI): 10.1109/ISCAS.2005.1465257 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/ISCAS.2005.1465257 (DOI: 10.1109/ISCAS.2005.1465257)
147.	Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Vectorless Open Pin Detection Method for CMOS Logic Circuits, Proc. of International Conference on Electronics Packaging, 391-396, Tokyo, Apr. 2005.
148.	Takashi Sakaguchi, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Tetsuo Tada, Takeshi Koyama, Yasuhiro Miyagawa, Seiji Tanaka and Toshihiro Kayahara : Fail-Safe Evaluation Method for Boiler Control Circuits by Circuit Simulation, Proc. RISP International Workshop on Nonlinear Circuit and Signal Processing, 395-398, Honolulu, Mar. 2005. (Summary) The fail-safe property is strongly requested for boiler control circuits. A boiler control circuit is a microprocessor based circuit and the operation is specified by a control program. Until now, there have been no methods to evaluate fail-safe property of boiler control circuits. In this paper, a fail safe evaluation method is proposed for boiler control circuits. The method utilizes a circuit simulator to check it. It is checked by the method whether it is stopped supplying fuel to a boiler when a fault occurs inside the boiler control circuit in operation. In order to evaluate the feasibility of fail-safe evaluation by the method, fail-safe property in a general boiler control circuit is examined by using the method. The result shows that fail-safe property will be checked by using the evaluation method.
149.	Seiichi Nishimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Electrical Detection of Pin Shorts by Supply Current of PIC, Proc. RISP International Workshop on Nonlinear Circuit and Signal Processing, 171-174, Honolulu, Mar. 2005. (Summary) In this paper, we propose a new test method for detecting pin shorts of a PIC. This test method is based on supply current of the PIC. Targeted faults of this test method are input/output pins of the PIC. The property is used for detecting the shorts in the test method that input/output mode of each of the pins is programmable. Each of the fault is excited by executing a test program so that supply current change can appear. We checked the feasibility of the test method by some experiments. The results shows that the shorts will be detected by the test method.
150.	Masahiro Ichimiya, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Test Equipment for CMOS Lead Open Detection Based on Supply Current under AC Electric Field Application, Proc. of the ECWC 10 Conference, P03-5-1-P03-5-5, Anaheim, Feb. 2005. (Summary) Open leads have often occurred in logic circuits implemented on printed circuit boards with the state-of-art technology. We proposed an electrical test method to detect them with high fault coverage. The test method is based on supply current change of a circuit under test that is caused with AC electric field supplied from the outside of the circuit. In this paper, we propose a test equipment for the test method. A voltage signal that is obtained by mixing a rectangle waveform signal and a sine waveform one is supplied between electrodes to generate the electric field. Amplitude of the signal continues to increase in proportion to time during a specified time. When supply current change that is larger than a threshold value appears, it stops increasing the amplitude and it is concluded that open leads occur in the circuit. If the supply current change does not appear within the specified time, it is concluded that no open leads occur in the circuit. In this paper, it is shown experimentally that an open lead at a CPLD of PLCC package is detected with the test equipment.
151.	Masaki Hashizume, Daisuke Yoneda, Hiroyuki Yotsuyanagi, Tetsuo Tada, Takeshi Koyama, Ikuro Morita and Takeomi Tamesada : IDDQ Test Method Based on Wavelet Transformation for Noisy Current Measurement Environment, Proc. of 13th Asian Test Symposium, 112-117, Kenting, Taiwan, Nov. 2004. (Summary) An IDDQ test method is proposed in this paper, which is applicable even if supply current measurement is impaired by noise. Wavelet transformation is used for noise elimination in the test method. In this paper, it is shown by some experiments that bridging faults will be detected by using the proposed test method. Since expert knowledge on filter design is not needed in noise elimination of the IDDQ test method, it is expected that the test method will be used in many IDDQ tests. (Link to Publication Site) ● Publication site (DOI): 10.1109/ATS.2004.50 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/ATS.2004.50 (DOI: 10.1109/ATS.2004.50)
152.	Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Test Circuit for CMOS Lead Open Detection by Supply Current Testing under AC Electric Field Application, Proc. of the 2004 47-th Midwest Symposium on Circuits and Systems, I-557-I-560, Hiroshima, Jul. 2004. (Summary) A test circuit is proposed for detecting lead opens of CMOS ICs by measuring the supply current of a CMOS circuit made of the ICs which flows when AC electric field is applied from the outside. A signal of a sine waveform is provided to the test circuit. In the test circuit, the amplitude of the signal increases in proportion to time during a prespecified time. The amplified signal is provided to electrodes for AC electric field to be supplied to a circuit under test. When supply current change which is larger than a threshold value appears, it stops increasing the amplitude and the test circuit concludes that a lead open occurs in the circuit. If the elevated supply current change does not appear within the specified time, the test circuit concludes that the circuit is fault-free. It is shown by our experiments that lead opens in a CMOS IC is detected with the test circuit. (Link to Publication Site) ● Publication site (DOI): 10.1109/MWSCAS.2004.1354051 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/MWSCAS.2004.1354051 (DOI: 10.1109/MWSCAS.2004.1354051)
153.	Takagi Masao, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Tsukimoto Isao and Takeomi Tamesada : AC Electric Field for Detecting Pin Opens by Supply Current of CMOS ICs, Proc. of International Conference on Electronics Packaging, 217-222, Tokyo, Apr. 2004.
154.	Daisuke Ezaki, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : A Power Supply Circuit Recycling Charge in Adiabatic Dynamic CMOS Logic Circuits, Proc. of the second IEEE International Workshop on Electronic Design, Test, and Applications, 306-311, Perth, Australia, Jan. 2004. (Summary) In this paper, a power supply circuit is proposed for adiabatic dynamic CMOS logic circuit. Charge in load capacitors of gates can be recycled by using this power supply circuit. It leads to lower power consumption than without recycling. In this paper, source voltage of adiabatic dynamic CMOS inverter chain circuits is supplied with the circuit to evaluate the usefulness of the circuit. The results show that the circuits can work with smaller power consumption than without recycling. (Link to Publication Site) ● Publication site (DOI): 10.1109/DELTA.2004.10022 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/DELTA.2004.10022 (DOI: 10.1109/DELTA.2004.10022)
155.	Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume and Kozo Kinoshita : On Configuring Scan Trees to Reduce Scan Shifts based on a Circuit Structure, Proc. of the second IEEE International Workshop on Electronic Design, Test, and Applications, 269-274, Perth, Australia, Jan. 2004. (Summary) In this paper, a new method for reducing test application time of sequential circuits with scan design is proposed. Scan design is one of most popular design for testability techniques. To reduce scan shifts required to provide the scan pattern, a fully testable scan tree configuration is proposed. The method can configure scan trees before generating test vectors without degrading fault coverage by considering a circuit structure. In a fully testable scan tree, flip-flops are placed in parallel in case that they have no overlap in the set of the outputs connected from them. To reduce much scan shifts, a folding scan tree, which is configured based on a fully testable scan tree by placing more flip-flops in parallel, is also configured. Moreover, a scan tree configuration considering scan-out operation is also presented. Experimental results for benchmark circuits are shown. (Link to Publication Site) ● Publication site (DOI): 10.1109/DELTA.2004.10014 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/DELTA.2004.10014 (DOI: 10.1109/DELTA.2004.10014)
156.	Isao Tsukimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Practical Fault Coverage of Supply Current Tests for Bipolar ICs, Proc. of the second IEEE International Workshop on Electronic Design, Test, and Applications, 189-194, Perth, Australia, Jan. 2004. (Summary) Bipolar logic circuits are indispensable for implementing high-speed logic circuits. Since quiescent supply current flows into the circuits without faults, they can not be tested by a conventional IDDQ test method. We proposed a quiescent supply current test method which is applicable for the bipolar circuit tests, and examined the testability of open faults under an ideal assumption that there are not any process variations. Actually, there are some variations in the quiescent supply current of each gate in implemented logic circuits. Thus, It is necessary to examine the practical testability of the test method before applying to production tests of bipolar logic ICs. In this paper, the practical testability obtained under an assumption that there are some unit-to-unit variations of supply current among gates is examined for ISCAS-85 benchmark circuits. The experimental results show that larger fault coverage can be obtained with a smaller number of test input vectors by our supply current test method than the functional test one based on stuck-at fault models. (Link to Publication Site) ● Publication site (DOI): 10.1109/DELTA.2004.10035 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/DELTA.2004.10035 (DOI: 10.1109/DELTA.2004.10035)
157.	Masaki Hashizume, Tetsuo Akita, Hiroyuki Yotsuyanagi and Takeomi Tamesada : CMOS Open Fault Detection by Appearance Time of Switching Supply Current, Proc. of the second IEEE International Workshop on Electronic Design, Test, and Applications, 183-188, Perth, Australia, Jan. 2004. (Summary) In this paper, a new dynamic supply current test method is proposed for detecting open defects on signal lines in CMOS logic circuits. The method is based on the appearance time of dynamic supply current that flows when a test input vector is provided to a circuit under test. Also, we introduce our designed sensor circuit of the appearance time. Feasibility of tests based on the test method is examined by some experiments. The experimental results show that open defects on signal lines in CMOS logic circuits will be detected by the test method. (Link to Publication Site) ● Publication site (DOI): 10.1109/DELTA.2004.10036 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/DELTA.2004.10036 (DOI: 10.1109/DELTA.2004.10036)
158.	Masaki Hashizume, Teppei Takeda, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura and Kozo Kinoshita : A BIST Circuit for IDDQ Tests, Proc. of Twelfth Asian Test Symposium, 390-395, Xi'an, Nov. 2003. (Summary) In this paper, an IDDQ test time reduction method is proposed which is suitable for BIST approaches. Also, a BIST circuit for IDDQ tests, based on the method, is proposed. The layout of a CMOS logic circuit having the BIST circuit is designed and the performance is evaluated by SPICE simulation. The results show us that IDDQ test time can be reduced by using this test circuit. (Link to Publication Site) ● Publication site (DOI): 10.1109/ATS.2003.1250843 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/ATS.2003.1250843 (DOI: 10.1109/ATS.2003.1250843)
159.	Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume and Kozo Kinoshita : Reducing Scan Shifts using Folding Scan Trees, Proc. of Twelfth Asian Test Symposium, 6-11, Xi'an, Nov. 2003. (Summary) In this paper, a new method for reducing scan shifts is presented. Scan design is one of the most popular design for test technologies for sequential circuits. However, it requires much test application time and test data when applied to circuits with many flip-flops. The new scan method utilizes two configurations of scan chains, a folding scan tree and a fully compatible scan tree. A test pattern including many don't care values is used to configure a fully compatible scan tree in order to reduce the scan shift without degrading fault coverage. And then a folding scan tree is configured to reduce the length of the scan chain and thus reduce the scan shift. Experimental results for benchmark circuits shows this scan method can reduce many scan shifts. (Link to Publication Site) ● Publication site (DOI): 10.1109/ATS.2003.1250772 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/ATS.2003.1250772 (DOI: 10.1109/ATS.2003.1250772)
160.	Masaki Hashizume, Makoto Kawajiri, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Testability of Supply Current Test in an AGC Circuit, Proc. of 2003 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.2, 836-839, Kang-Won Do, Korea, Jul. 2003. (Summary) In this paper, it is examined whether AGC circuits can be tested by measuring supply current of the circuits. A general AGC circuit is designed and a fault, which is one of shorts, opens and parametric faults, is inserted to the circuit. Supply current waveforms of faulty circuits are derived by circuit simulation and compared to the one of the fault-free circuit. The experimental results show that many faults in the AGC circuit can be detected by measuring the supply current.
161.	Takagi Masao, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Testability of Pin Open in Small Outline Package ICs by Supply Current Test, Proc. of the 2003 International Technical Conference on Circuits/Systems, Computers and Communications, 832-835, Kang-Won Do, Korea, Jul. 2003.
162.	Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Electric Field Application Method Effective for Pin Open Detection Based on Supply Current in CMOS Logic Circuits, Proc. of International Conference on Electronics Packaging, 75-80, Tokyo, Apr. 2003.
163.	Masaki Hashizume, Teruyoshi Matsushima, Takashi Shimamoto, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Akio Sakamoto : Simplification of Incompletely Specified Machine Based on Genetic Algorithm Implementing Dormant Mechanism, 3rd Workshop on RTL and High Level Testing (WRTLT02), 74-78, Guam, USA, Nov. 2002.
164.	Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Test Time Reduction for IDDQ Testing by Arranging Test Vectors, Proc. of Eleventh Asian Test Symposium, 423-428, Guam, USA, Nov. 2002. (Summary) In this paper, test time reduction for IDDQ testing is discussed. Although IDDQ testing is known to be effective in detecting faults in CMOS circuits, the test time of IDDQ testing is larger than that of logic testing. It is shown that the test time of IDDQ test mostly depends on the switching current. To reduce the test time of IDDQ testing, a procedure to arrange test vectors such that the switching current quickly disappears is proposed for combinational circuits. The procedure utilizes a unit delay model to estimate the time of the last transition of logic values from low to high in a circuit. Experimental results for benchmark circuits show the effectiveness of the procedure. (Link to Publication Site) ● Publication site (DOI): 10.1109/ATS.2002.1181748 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/ATS.2002.1181748 (DOI: 10.1109/ATS.2002.1181748)
165.	Masaki Hashizume, Nobuyuki Inou, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Oscillation Frequency Estimation for Detecting Feedback Bridging Faults, Proc. of 2002International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 1980-1983, Phuket, Thailand, Jul. 2002. (Summary) When a feedback bridging fault is activated in a circuit, logical oscillation may occur at a signal line. If the oscillation appears, the fault may not be detected by logic testing. In order to detect such bridging faults, output logic values of the circuit should be measured at higher frequency than frequency of the logical oscillation. In this paper, a method for estimating the maximum frequency of logical oscillation is proposed to detect such bridging faults in a circuit by logic testing. Also, it is shown by some experiments that such bridging faults can be detected by measuring output logic values at the frequency obtained by the method.
166.	Isao Tsukimoto, Masaki Hashizume, Yukiko Mushiaki, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Testability of Current Testing for Open Faults Undetected by Functional Testing in TTL Combinational Circuits, Proc. of 2002International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 1972-1975, Phuket, Thailand, Jul. 2002. (Summary) A new test approach based on a supply current test method is proposed for testing open faults in bipolar logic circuits. In the approach, only the open faults are detected by the supply current test method, which are difficult to be detected by functional test methods. The effectiveness of the approach is examined experimentally on open fault detection in TTL combinational circuits. The results shows that higher fault coverage can be established by applying a small number of test input vectors of the supply current test method after test vectors of functional test methods based on stuck-at models.
167.	Masaki Hashizume, Tasaka Eiji, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Toshihiro Kayahara : Power-off Vectorless Test Method for Pin Opens in CMOS Logic Circuits, Proc. of International Conference on Electronics Packaging, 416-420, Tokyo, Apr. 2002. (Summary) A new test method is proposed in this paper for detecting pin opens in CMOS logic circuits fabricated on printed circuit boards, which are generated by missing solder and so on. Our test method is based on the current which flows through a protection circuit connecting to each pin by supplying a voltage source between the targeted pin and VSS line of a circuit under test. The test method does not require test input generation. When a pin open occurs, smaller current will be supplied from the voltage source than in the case of the fault-free circuit. Our test method uses the property for detecting pin opens. In this paper, the feasibility of the test method is evaluated by some experiments.
168.	Masaki Hashizume, Masashi Sato, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Power Supply Circuit for High Speed Operation of Adiabatic Dynamic CMOS Logic Circuits, Proc. of the IEEE International Workshop on Electronic Design, Test, and Applications, 459-461, Christchurch, New Zealand, Jan. 2002. (Summary) In this paper, a power supply circuit is proposed for adiabatic dynamic CMOS logic circuits proposed by K. Takahashi et. al. With this supply circuit, the circuits can work at higher speed. In this paper, source voltage of adiabatic dynamic CMOS inverter gates is supplied by the circuit and the power consumption is examined. The results show that the gates can work with smaller power dissipation than conventional static CMOS circuits (Link to Publication Site) ● Publication site (DOI): 10.1109/DELTA.2002.994673 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/DELTA.2002.994673 (DOI: 10.1109/DELTA.2002.994673)
169.	Hiroyuki Yotsuyanagi, Masaki Hashizume, Taisuke Iwakiri, Masahiro Ichimiya and Takeomi Tamesada : Random Pattern Testability of the Open Defect Detection Method using Application of Time-variable Electric Field, Proc. of the IEEE International Workshop on Electronic Design, Test, and Applications, 387-391, Christchurch, New Zealand, Jan. 2002. (Summary) In this paper, random pattern testability of the open defect detection method is discussed. In the test method, time-variable electric field is applied from the outside of ICs so as to vary the voltage at floating nodes caused by a defect. To detect opens the excessive supply current caused by the applied electric field is measured. The test pattern requirements for detecting opens are shown. The fault coverage for open defects is calculated for benchmark circuits. The experimental results shows random pattern can be effectively utilized for the test method even if it cannot attain high fault coverage for stuck-at-faults (Link to Publication Site) ● Publication site (DOI): 10.1109/DELTA.2002.994656 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/DELTA.2002.994656 (DOI: 10.1109/DELTA.2002.994656)
170.	Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : CMOS Open Defect Detection Based on Supply Current in Time-variable Electric Field and Supply Voltage Application, Proc. of Tenth Asian Test Symposium, 117-122, Kyoto, Nov. 2001. (Summary) In this paper, a new test method is proposed for detecting open defects in CMOS ICs. The method is based on supply current of ICs generated by applying time-variable supply voltage and electric field from the outside of the ICs. The feasibility of the test is examined by some experiments. The empirical results show that, by using the method, open defects in CMOS ICs can be detected. Also, the test input vectors for the test method are proposed and it is shown that they can be generated more easily than functional test methods based on stuck-at fault models (Link to Publication Site) ● Publication site (DOI): 10.1109/ATS.2001.990269 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/ATS.2001.990269 (DOI: 10.1109/ATS.2001.990269)
171.	Teppei Takeda, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Yukiya Miura and Kozo Kinoshita : IDDQ Sensing Technique for High Speed IDDQ Testing, Proc. of Tenth Asian Test Symposium, 111-116, Kyoto, Nov. 2001. (Summary) In this paper, a useful technique is proposed for realizing high speed IDDQ tests. By using the technique, load capacitors of the CMOS logic gates can be charged quickly, where the output logic level changes L to H by applying a test input vector to a circuit under test. The technique is applied to built-in IDDQ sensor design and external IDDQ sensor design. It is shown experimentally that high speed IDDQ tests can be realized by using the technique (Link to Publication Site) ● Publication site (DOI): 10.1109/ATS.2001.990268 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/ATS.2001.990268 (DOI: 10.1109/ATS.2001.990268)
172.	Hiroyuki Yotsuyanagi, Shinsuke Hata, Masaki Hashizume and Takeomi Tamesada : Sequential Redundancy Removal Using Test Generation and Multiple Unreachable States, Proc. of Tenth Asian Test Symposium, 23-28, Kyoto, Nov. 2001. (Summary) In this paper, a procedure to reduce sequential circuits by removing undetectable faults in sequential circuits is proposed. To identify whether an undetectable fault is removable or not, strongly unreachable states, which are the states with no incoming transitions, are utilized. It is proved that part of undetectable faults related to strongly unreachable states can be removed from a circuit. Test generation method is used to find undetectable faults related to two or more strongly, unreachable states. Experimental results for ISCAS benchmark circuits are shown (Link to Publication Site) ● Publication site (DOI): 10.1109/ATS.2001.990253 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/ATS.2001.990253 (DOI: 10.1109/ATS.2001.990253)
173.	Hiroyuki Yotsuyanagi, Masaki Hashizume, Taisuke Iwakiri, Masahiro Ichimiya and Takeomi Tamesada : Test Pattern for Supply Current Test of Open Defects by Applying Time-variable Electric Field, Proc. of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 287-295, San Francisco, Oct. 2001. (Summary) Test input vectors for a supply current test method are discussed which is used for detecting open defects in CMOS ICs. In the test method, time-variable electric field is applied from the outside of ICs so as to vary the voltage at a floating node. To generate excessive supply current by the induced voltage change at the floating node, test pattern must be provided so that a conducting path from VDD to GND can be generated in the faulty circuit. In this paper, the requirements are denoted to be satisfied as a test input vector of the test method. Also, it is shown that test pattern of functional tests based on stuck-at fault models can be used for the open defect detection method. Furthermore, the experimental results in this paper promise that high fault coverage can be achieved by applying the subset of the stuck-at test pattern to the detection of open defects (Link to Publication Site) ● Publication site (DOI): 10.1109/DFTVS.2001.966781 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-0035202383 (DOI: 10.1109/DFTVS.2001.966781, Elsevier: Scopus)
174.	Teppei Takeda, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : A High Speed IDDQ Sensor Circuit, Proc. of 2001 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.2, 438-441, Tokushima, Jul. 2001.
175.	Masaki Hashizume, Eiji Tasaka, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Toshihiro Kayahara : Fault Simulator for Test Program Generation in Supply Current Tests of Microprocessor Based Boiler Control Circuits, Proc. of 2001 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 446-449, Tokushima, Jul. 2001.
176.	Akihiro Tsuji, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Pin Open Detection Method Based on Supply Current in Time-variable Magnetic Field, Proc. of 2001 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 438-441, Tokushima, Jul. 2001.
177.	Masaki Hashizume, Akihiro Tsuji, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Supply Current Test for Pin Opens in CMOS Logic Circuits, Proc. of International Conference on Electronics Packaging, 363-368, Tokyo, Apr. 2001.
178.	Masaki Hashizume, Masahiro Ichimiya, Hiroshi Hoshika, Hiroyuki Yotsuyanagi and Takeomi Tamesada : CMOS Open Defect Detection by Supply Current Test, Proc. of Design, Automation and Test in Europe Conference 2001, 509-513, Munich, Mar. 2001. (Summary) In this paper, a new test method is proposed for detecting open defects in CMOS ICs. The method is based on supply current of ICs generated by applying time-variable electric field from the outside of the ICs. The feasibility of the test is examined by some experiments. The empirical results promised that, by using the method, open defects in CMOS ICs can be detected by measuring supply current which flows when time-variable electric field is applied (Link to Publication Site) ● Publication site (DOI): 10.1109/DATE.2001.915071 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/DATE.2001.915071 (DOI: 10.1109/DATE.2001.915071)
179.	Masaki Hashizume, Hiroyuki Yotsuyanagi, Masahiro Ichimiya, Takeomi Tamesada and Masashi Takeda : High Speed IDDQ Test and Its Testability for Process Variation, IEEE Asian Test Symposium, 344-349, TAIPEI TAIWAN, Dec. 2000. (Summary) A new high speed IDDQ test method is proposed. It is based on charge current for load capacitances of gates whose output logic values are changed from L to H by test input vector application. In this paper, the testability of the test method is examined for some process variations generated in CMOS IC production (Link to Publication Site) ● Publication site (DOI): 10.1109/ATS.2000.893647 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-0034497760 (DOI: 10.1109/ATS.2000.893647, Elsevier: Scopus)
180.	Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Masashi Takeda : Testability Analysis of IDDQ Testing with Large Threshold Value, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 367-375, Yamanashi Japan, Oct. 2000. (Summary) By using large threshold value in IDDQ tests, test time can be shortened. However, the fault coverage of the IDDQ tests will be affected by process variation. In this paper, effects on fault coverage of IDDQ tests generated by variations of zero biased threshold voltage of each MOS transistor in a circuit under test are examined with a circuit simulator. The result suggests us that IDDQ testing with large threshold value is applicable to production tests of CMOS ICs (Link to Publication Site) ● Publication site (DOI): 10.1109/DFTVS.2000.887177 (Link to Search Site for Scientific Articles) ● Summary page in Scopus @ Elsevier: 2-s2.0-0034517501 (DOI: 10.1109/DFTVS.2000.887177, Elsevier: Scopus)
181.	Masashi Sato, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Power Supply Circuits with Small Size for Adiabatic Dynamic CMOS Logic Circuits, Proc. of 2000 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 179-182, Busan, Jul. 2000.
182.	Yukiko Mushiaki, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Practical Fault Coverage of Supply Current Testing for Open Fault in TTL Combinational Circuits, Proc. of 2000 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 383-386, Busan, Jul. 2000.
183.	Takahiro Ohnishi, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : A Test Input Sequence for Test Time Reduction of IDDQ Testing, Proc. of 2000 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 367-370, Busan, Jul. 2000. (Summary) It is shown that IDDQ testing is very useful for shipping fault-free CMOS ICs. However, test time of IDDQ testing is extremely larger than one of logic testing. In this paper, a new test input sequence generation methodology is proposed to reduce the test time of lDDQ testing. At first, it is shown that IDDQ test time will be denominated by charge supply current for load capacitance of gates whose output logic values are changed by test input vector application and the charge current depends on input sequence of test vectors. After that, a test input sequence generation methodology is proposed, The feasibility is checked by some experiments.
184.	Hiroshi Hoshika, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : IDDQ Testable Design of Static CMOS PLAs with Low Power Consumption, Proc. of 2000 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 351-354, Busan, Jul. 2000.
185.	Sou Yamamoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Oscillation Frequency Estimation of Feedback Bridging Faults for Test Circuit Design, Proc. of 2000 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 343-346, Busan, Jul. 2000.
186.	Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Synthesis for Testability by Adding Transitions of Undefined States to State Transition Tables, Proc. of 2000 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 355-358, Busan, Jul. 2000. (Summary) In this paper we propose procedures to enhance testability by modifying state transition tables. In these procedures, transitions about undefined states, which are not described in state transition tables but exist in a synthesized gate level circuit, are added to a state transition table. Experimental results for MCNC benchmarks are shown.
187.	Masaki Hashizume, Hiroshi Hoshika, Hiroyuki Yotsuyanagi and Takeomi Tamesada : IDDQ Testable Design of Static CMOS PLAs, IEEE International Workshop on Defect Based Testing, 70-75, Montreal, Apr. 2000. (Summary) A new IDDQ testable design method is proposed for static CMOS PLA circuits. A testable PLA circuit of NOR-NOR type is designed by using this method. It is shown that all bridging faults in NOR planes of the testable designed PLA circuit can be detected by IDDQ testing with 4 kinds of test input vectors. The test input vectors are independent of the logical functions to be realized in the PLA circuit. PLA circuits are designed by using this method so that quiescent supply current generated when they are tested can be zero. Thus, high resolution of IDDQ tests for the PLA circuits can be obtained by using this testable design method. (Link to Publication Site) ● Publication site (DOI): 10.1109/DBT.2000.843693 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/DBT.2000.843693 (DOI: 10.1109/DBT.2000.843693)
188.	Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Identification of Feedback Bridging Faults with Oscillation, IEEE Eighth Asian Test Symposium, 25-30, Shanghai, Nov. 1999. (Summary) When a feedback bridging fault occurs in a combinational circuit and it is activated, logical oscillation may be generated in the circuit. In this paper, the necessary conditions are presented for feedback bridging faults to generate logical oscillation. Also, a method is proposed to identify such faults in feedback bridging ones. It is based on piecewise-linearized models obtained from input/output characteristics of logic gates and does not require circuit simulation of large size of circuits to identify them. In the experiments for evaluating the method, all of the feedback bridging faults to generate logical oscillation are identified by using the method (Link to Publication Site) ● Publication site (DOI): 10.1109/ATS.1999.810725 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/ATS.1999.810725 (DOI: 10.1109/ATS.1999.810725)
189.	Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Eiji Tasaka and Toshihiro Kayahara : Supply Current testing for Bridging Faults in Microprocessor Based Sequence Control Circuits, Proc. of Electronic Circuits World Convention 8, 31-37, Tokyo, Sep. 1999.
190.	Masaki Hashizume, Masashi Sato, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Power Supply Circuit for Adiabatic Dynamic CMOS Logic Circuits, Proc. of 1999 International Technical Conference on Circuits/Systems, Computers and Communications, Vol.1, 162-165, Niigata, Jul. 1999.
191.	Hiroyuki Yotsuyanagi and Kozo Kinoshita : Undetectable Fault Removal of Sequential Circuits Based on Unreachable States, Proc. of 16th IEEE VLSI Test Symposium, 176-181, Monterey, Apr. 1998. (Summary) We present a procedure to reduce sequential circuits by removing undetectable faults based on unreachable states. Procedures for obtaining unreachable stares and for identifying undetectable faults which can be the target of fault removal are presented. Experimental results for ISCAS benchmark circuits are shown (Link to Publication Site) ● Publication site (DOI): 10.1109/VTEST.1998.670866 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/VTEST.1998.670866 (DOI: 10.1109/VTEST.1998.670866)
192.	Hiroyuki Yotsuyanagi, Seiji Kajihara and Kozo Kinoshita : Synthesis for Testability by Redundancy Removal Using Retiming, Proc. 25th International Symposium on Fault-Tolerant Computing, 33-40, Pasadena, California, USA, Jun. 1995. (Summary) The existence of sequential redundancy will degrade testability of sequential circuits. By using retiming which rearranges flip-flops, some sequential redundancy are converted into combinational redundancy, which can be easily identified and removed by a combinational test generation technique. In this paper retiming is utilized for two purposes: one is for finding sequential redundancy and another is for reducing the number of flip-flops. Applying retiming and redundancy removal techniques concurrently, testability of sequential circuits will be enhanced. Experimental results for ISCAS'89 benchmark circuits show effectiveness of this method to optimize the circuits. (Link to Publication Site) ● Publication site (DOI): 10.1109/FTCS.1995.466981 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/FTCS.1995.466981 (DOI: 10.1109/FTCS.1995.466981)
193.	Hiroyuki Yotsuyanagi, Seiji Kajihara and Kozo Kinoshita : Resynthesis for Sequential Circuits Designed with a Specified Initial State, Proc. 13th IEEE VLSI Test Symposium, 152-157, Princeton, New Jersey, USA, May 1995. (Summary) This paper presents a retiming and redundancy removal method for a sequential circuit with a specified initial state so that the resynthesized circuit has a state corresponding to the initial state and gives same behavior for any input sequences of the original circuit. Experimental results show the proposed method can optimize circuits as well as the method which does not consider the specified initial state (Link to Publication Site) ● Publication site (DOI): 10.1109/VTEST.1995.512630 (Link to Search Site for Scientific Articles) ● Search Scopus @ Elsevier (DOI): 10.1109/VTEST.1995.512630 (DOI: 10.1109/VTEST.1995.512630)

Proceeding of Domestic Conference:

1.	Daichi Akamatsu, Shogo Tohkai, Hiroyuki Yotsuyanagi and Masaki Hashizume : On Reducing Area Overhead of BIST for Approximate Multiplier Considering Truncated Bits, IEICE Technical Report, Vol.123, No.260, 156-161, Nov. 2023.
2.	Hiroto Komatsubara, Ohmatsu Masao, Hiroyuki Yotsuyanagi and Masaki Hashizume : Temperature Dependence on Amplitude of Invertor in Comparator of Offset Cancellation Type, Shikoku-Section Joint Convention Record of the Institutes of Electrical and Related Engineers, 10-13, Sep. 2023.
3.	Kohji Arimoto, Hiroyuki Yotsuyanagi, Yuya Okumoto, Koki Miyatani and Masaki Hashizume : On the Evaluation of Boundary Scan Design for Testing Interconnects between ICs in a Stand-by Mode, Shikoku-Section Joint Convention Record of the Institutes of Electrical and Related Engineers, 10-12, Sep. 2023.
4.	Ohmatsu Masao, Yuto Ohtera, Hiroyuki Yotsuyanagi, Masaki Hashizume and Shyue-Kung Lu : アナログ素子のみで構成する弛緩発振器によるIC間抵抗断線の検出可能性調査, 第33回マイクロエレクトロニクスシンポジウム論文集, 393-396, Sep. 2023.
5.	Kohji Arimoto, Hiroyuki Yotsuyanagi and Masaki Hashizume : A Study on Boundary Scan Design for Testing Interconnects between ICs in a Stand-by Mode, 第37回エレクトロニクス実装学会春季講演大会, 6-9, Mar. 2023.
6.	Shogo Tohkai, Hiroyuki Yotsuyanagi and Masaki Hashizume : On reduction of test patterns for a Multiplier Using Approximate Computing, IEICE Technical Report, Vol.122, No.285, 25-30, Nov. 2022.
7.	KEIGO Takami, Hiroyuki Yotsuyanagi and Masaki Hashizume : Evaluation of testing TSVs using the delay testable circuit implemented in a 3D IC, IEICE Technical Report, Vol.122, No.285, 162-167, Nov. 2022.
8.	Eisuke Ohama, Hiroyuki Yotsuyanagi and Masaki Hashizume : On the Performance Evaluation of a PUF Circuit Using the Delay Testable Circuit under Temperature Effects, IEICE Technical Report, Vol.122, No.285, 156-161, Nov. 2022.
9.	KOHKI Kawano, Hiroyuki Yotsuyanagi and Masaki Hashizume : On Testing Resistive Open at Interconnections between an IC with Boundary-scan with Embedded TDC and a Non-JTAG Device, Shikoku-Section Joint Convention Record of the Institutes of Electrical and Related Engineers, 10-3, Sep. 2022.
10.	TOMOYA Inage, Hiroyuki Yotsuyanagi and Masaki Hashizume : Combination of Test Pattern for Discrimination of a Resistive Open and Delay Fault, Shikoku-Section Joint Convention Record of the Institutes of Electrical and Related Engineers, 10-2, Sep. 2022.
11.	Kohsuke Hara, Hiroyuki Yotsuyanagi and Masaki Hashizume : On Input Dependency of Open Fault Detection Method Using a Charge Pump, Shikoku-Section Joint Convention Record of the Institutes of Electrical and Related Engineers, 10-1, Sep. 2022.
12.	Shota Katayama, Kohji Arimoto, Hiroyuki Yotsuyanagi and Masaki Hashizume : On a circuit to identify scan segments to be observed for optimizing scan operation of boundary scan with embedded TDC, 第36回エレクトロニクス実装学会春季講演大会, 215-218, Mar. 2022.
13.	Eisuke Ohama, Haruka Chino, Hiroyuki Yotsuyanagi and Masaki Hashizume : Applicability Evaluation of the Delay Testable Circuit to PUF, IEICE Technical Report, Vol.121, No.388, 24-29, Mar. 2022.
14.	Koji Makino, Hiroyuki Yotsuyanagi and Masaki Hashizume : Delay Fault Test Pattern Generation of Fault Tolerant Design Using Approximate Computing, IEICE Technical Report, Vol.121, No.388, 39-44, Mar. 2022.
15.	Naoki Ikeda, Hiroyuki Yotsuyanagi and Masaki Hashizume : A study on the application of a testable design of pixel circuits in interconnect testing of stacked CMOS image sensor, IEICE Technical Report, Vol.FIIS21, No.546, 1-6, Oct. 2021.
16.	Shunta Hosomi, Hiroyuki Yotsuyanagi and Masaki Hashizume : On testing interconnects of stacked chips in a stacked CMOS image sensor using voltage-to-delay cells, 電気・電子・情報関係学会四国支部連合大会講演論文集, 10-8, Sep. 2021.
17.	Haruka Chino, Hiroyuki Yotsuyanagi and Masaki Hashizume : A study on application of a delay test architecture to Physically Unclonable Function (PUF), 電気・電子・情報関係学会四国支部連合大会講演論文集, 10-7, Sep. 2021.
18.	Kohji Arimoto, Koji Makino, Hiroyuki Yotsuyanagi and Masaki Hashizume : On Test Time Reduction by Selecting Cells for Observing Delay Using Boundary Scan with Embedded TDC, 第35回エレクトロニクス実装学会春季講演大会, 18B2-02-1-18B2-02-4, Mar. 2021.
19.	Kohsuke Fukuda, Hiroyuki Yotsuyanagi and Masaki Hashizume : A Study on Test Clock Control Circuit for the Design-for-Testability Circuit to Detect Small Delay Faults, 第35回エレクトロニクス実装学会春季講演大会, 18B2-01-1-18B2-01-4, Mar. 2021.
20.	Kohsuke Fukuda, Hiroyuki Yotsuyanagi and Masaki Hashizume : A Clock Control Circuit in Design-for-Testability Method for Delay Fault in 3D IC, 電気・電子・情報関係学会四国支部連合大会講演論文集, 10-2, Sep. 2020.
21.	Kanami Nagata, Hiroyuki Yotsuyanagi and Masaki Hashizume : A target path selection method for delay test using design-for-testability circuit, 電気・電子・情報関係学会四国支部連合大会講演論文集, 10-1, Sep. 2020.
22.	Sako Fumiya, yuki ikiri, Masaki Hashizume, Hiroyuki Yotsuyanagi, Yokoyama Hiroshi and Shyue-Kung Lu : Temperature Sensingwith a Built-in Relaxation Oscillator in CMOS ICs, 電気・電子・情報関係学会四国支部連合大会講演論文集, 9-2, Sep. 2020. (Keyword) sensor / Relaxation Oscillator / analog electronic circuits
23.	Yuto Ohtera, Fumiya Sako, Yuki Ikiri, Hiroyuki Yotsuyanagi, Masaki Hashizume and Shyue-Kung Lu : Temperature Measurement in CMOS ICs with a Relaxation Oscillator Made of Analog Elements, Proceedings of the Society Conference of IEICE, 55, Sep. 2020.
24.	Yuya Okumoto, Hanna Soneda, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Resistance Estimationof Open Defects between Dies in 3D ICs from pMOS On-Resistance for Open Defect Detection by Supply Current Test Method, Proceedings of the Society Conference of IEICE, 54, Sep. 2020.
25.	Sachihiro Deguchi, Yuta Matsumoto, Hiroyuki Yotsuyanagi, Masaki Hashizume and Shyue-Kung Lu : Experimental Examination of Open Defect Detectability by Injected Charge Volume in CMOS ICs, Proceedings of the Society Conference of IEICE, 53, Sep. 2020.
26.	Koji Makino, Hiroyuki Yotsuyanagi and Masaki Hashizume : Development of a Die Selection Circuit in the Delay Test Architecture for 3D IC, Proceedings of the Society Conference of IEICE, 52, Sep. 2020.
27.	Hiroshi Yamazaki, Yuta Ishiyama, Tatsuma Matsuta, Toshinori Hosokawa, Masayoshi Yoshimura, Masayuki Arai, Hiroyuki Yotsuyanagi and Masaki Hashizume : A Test Generation Method for Resistive Open Faults Using Partial MAX-SAT solver, IEICE Technical Report, Vol.119, No.443, 215-220, Mar. 2020. (Summary) 従来，VLSIのテストでは，縮退故障モデルや遷移故障モデルが広く用いられてきた．しかしながら，半導体微細化技術の進展に伴い，従来使用されてきた故障モデルを対象としたテストでは検出困難な欠陥が増加している．このような欠陥の一つは，抵抗性オープン故障モデルでモデル化できる．抵抗性オープン故障は，回路内の配線の導電率の低下を表現しており，タイミング故障を引き起こす微小遅延故障である．そのため，可能な限り長い経路でテスト生成を行うことが重要である．また，抵抗性オープン故障の付加的な遅延サイズは，その隣接信号線の値と並走距離によって変化する．そのため，抵抗性オープン故障のテスト生成では，故障伝搬経路と隣接信号線の考慮が重要である．本論文では，パーシャルMaxSATを用いて故障伝搬経路と隣接信号線を考慮した抵抗性オープン故障のテスト生成法を提案する．さらに，生成したテスト集合を故障シミュレーションによって評価する．
28.	Kanami Nagata, Hiroyuki Yotsuyanagi and Masaki Hashizume : Selection of target paths for reducing test application time of delay test using design-for-testability circuit, 第34回エレクトロニクス実装学会春季講演大会, 4C1-01-1-4C1-01-3, Mar. 2020.
29.	Haruka Chino, Shuya Kikuchi, Hiroyuki Yotsuyanagi and Masaki Hashizume : A study on a monitoring system for detecting delay defects using boundary scan circuit, 第34回エレクトロニクス実装学会春季講演大会, 4C1-04-1-4C1-04-3, Mar. 2020.
30.	Ryotaroh Nakanishi, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yoshinobu Higami and Hiroshi Takahashi : A study on temperature dependence on discrimination of resistive opens using machine learning-based anomaly detection, IEICE Technical Report, Vol.119, No.420, 13-18, Feb. 2020. (Summary) A resistive open with high resistance results in a small delay. Small delay by a resistive open is difficult to test since circuit delay varies depending on various factors such as crosstalk and process variations. In this paper, we consider the method for discriminating a resistive open using delay distribution obtained by various input signals provided to adjacent lines. This paper describes our method and shows the results of temperature dependencies of the discrimination method.
31.	Jumpei Kawano, Hiroyuki Yotsuyanagi and Masaki Hashizume : On Design and Evaluation for Standard Cell of Boundary Scan with Embedded TDC, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 85, Sep. 2019.
32.	Kento Nakanishi, Hiroyuki Yotsuyanagi and Masaki Hashizume : Evaluation of delay resolution of PFD used for path delay ranking, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 84, Sep. 2019.
33.	Kanami Nagata, Hiroyuki Yotsuyanagi and Masaki Hashizume : Selection of target paths for reducing test application time in delay test using design-for-testability circuit, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 83, Sep. 2019.
34.	Takuto Nishikawa, Hiroyuki Yotsuyanagi and Masaki Hashizume : Effect of Inter-chip Delay Variation for Resistive Open Fault Detection by Path Delay Ranking, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 82, Sep. 2019.
35.	Yuta Matsumoto, Masaki Hashizume and Hiroyuki Yotsuyanagi : Charge Injection Control Circuit for Detecting Resistive Open Defects in ICs, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 80, Sep. 2019.
36.	Ken Ishihara, Masaki Hashizume and Hiroyuki Yotsuyanagi : Open Defect Detection in a Differential Amplifier with Electrical Test Circuit Based on Injected Charge Volume, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 79, Sep. 2019.
37.	Koki Miyatani, Michiya Kanda, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Feasibility of Defective Level Monitoring of Resistive Open Defects in Assembled PCBs with a Comparator of Offset Cancellation Type, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 78, Sep. 2019.
38.	Hanna Soneda, Michiya Kanda, Hiroyuki Yotsuyanagi, Masaki Hashizume and Shyue-Kung Lu : 電気試験法による実装基板内抵抗断線の出荷後検出法, 第29回マイクロエレクトロニクスシンポジウム論文集, 131-134, Sep. 2019.
39.	Kosuke Ikeuchi, Michiya Kanda, Hiroyuki Yotsuyanagi, Masaki Hashizume and Shyue-Kung Lu : バウンダリスキャンテストによる3D IC内ダイ間抵抗断線検出可能性調査, 第29回マイクロエレクトロニクスシンポジウム論文集, 127-130, Sep. 2019.
40.	Ryoya Ohtsuka, Hiroyuki Yotsuyanagi, Masaki Hashizume and Chia-Yu Yao : A study on applying a PLL circuit to detect delay faults, 電子情報通信学会総合大会講演論文集, 44, Mar. 2019.
41.	Shuya Kikuchi, Soma Shinkai, Hiroyuki Yotsuyanagi and Masaki Hashizume : Evaluation of the effect of delay variations on small delay testing using boundary scan circuits with embedded TDC, 第33回エレクトロニクス実装学会春季講演大会, 12D1-03-1-12D1-03-3, Mar. 2019.
42.	Kosuke Ikeuchi, Michiya Kanda, Satoshi Hirai, Hiroyuki Yotsuyanagi and Masaki Hashizume : A Test Access Port Controller for Stand-by Mode Electrical Testing with Boundary Scan Flip Flops, 第33回エレクトロニクス実装学会春季講演大会, 12D1-01-1-12D1-01-4, Mar. 2019.
43.	Satoshi Hirai, Hiroyuki Yotsuyanagi and Masaki Hashizume : Test Time Reduction by Separating Delay Lines in Boundary Scan Circuit with Embedded TDC, IEICE Technical Report, Vol.118, No.335, 119-124, Dec. 2018. (Summary) 3D die-stacking technique using TSVs has gained much attention as a new integration method of IC. However, faulty TSVs may cause small delay faults because of defects in TSVs such as voids and pinholes during the manufacturing process. We have been proposed a DFT(Design-For-Testability) method for TSVs using a boundary scan circuit with embedded TDC(TDCBS). The TDCBS has a circuit component called delay line that has two roles. One is to observe a delay in TSVs and the other is to apply a transition signal to TSV. In this paper, we present a design to separate the delay lines into two parts for delay observation and for transition signal application in order to reduce test application time on TDCBS. The proposed design can reduce test application time since the length of the scan chain is shortened by separating the delay lines.
44.	Yuta Matsumoto, Hiroyuki Yotsuyanagi, Masaki Hashizume and Shyue-Kung Lu : Effects of Injection Timing on Open Defect Detectability in Charge Injection Tests of SoCs, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 83, Sep. 2018.
45.	Hanna Soneda, Michiya Kanda, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Detectability of Resistive Open Defects in 3D ICs with an Electrical Interconnect Test Circuit Made of Diodes under Process Variation, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 82, Sep. 2018.
46.	Shunsuke Shibata, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yoshinobu Higami and Hiroshi Takahashi : On the effectiveness of the discrimination method for resistive open using signal transitions on adjacent lines against temperature, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 80, Sep. 2018.
47.	Noriko Miyatake, Hiroyuki Yotsuyanagi, Hiroshi Yokoyama, Masaki Hashizume and Tetsuo Tada : Effect of Process Variation on Oscillation Frequency in Interconnect Tests of 3D ICs with a Ring Oscillator, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 81, Sep. 2018.
48.	Michiya Kanda, Hiroyuki Yotsuyanagi and Masaki Hashizume : 実装基板回路内抵抗断線のバウンダリスキャンテストによる出荷後検出能力評価, 第28回マイクロエレクトロニクスシンポジウム講演論文集, 185-188, Sep. 2018.
49.	Satoshi Hirai, Hiroyuki Yotsuyanagi and Masaki Hashizume : Reduction of Wire Length by Reordering Delay Elements in Boundary Scan Circuit with Embedded TDC, IEICE Technical Report, Vol.117, No.444, 13-18, Feb. 2018. (Summary) TSV attracts attention as a new implementation method of interconnects between dies in 3DICs. However, faulty TSVs may cause small delay faults because of defects in TSVs such as voids and pinholes during the manufacturing process. We have been proposed a DFT(Design-For-Testability) method for TSVs using a boundary scan circuit with embedded TDC(TDCBS). We proposed the design method for reducing variation of additional delay by reordering delay elements. However, in this method, the wire for forming a loop becomes long compared with other wires. In this paper, we present the design method for reducing the wire length of the feedback wire by reordering delay elements under consideration of a loop.
50.	Ayumu Kambara, Kouhei Ohtani, Hiroyuki Yotsuyanagi and Masaki Hashizume : Design of TDC Embedded in Scan FFs for Testing Small Delay Faults, IEICE Technical Report, Vol.117, No.274, 125-130, Nov. 2017. (Summary) Increasing open defects has become a problem. We proposed a supply current test method with a built-in sensor for detecting open defects on signal lines in CMOS logic circuits. The test method is based on an appearance time of dynamic supply current that flows when a test input vector is provided to a device under test. We propose the improved test method to make the difference of IDDT appearance time greater. In addition, SPICE simulation results show that open defects are detected by the improved sensor.
51.	Michiya Kanda, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu : Feasibility of Defective Level Monitoring of Open Defects in 3D ICs with a Comparator of Offset Cancellation Type, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 82, Sep. 2017.
52.	Masashi Okamoto, Hiroyuki Yotsuyanagi, Masaki Hashizume and Shyue-Kung Lu : Effect of Process Variation in a Built-in Test Circuit Based on Quiescent Current Flowing through Interconnects of 3D ICs, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 81, Sep. 2017.
53.	Noriko Miyatake, Hiroyuki Yotsuyanagi, Hiroshi Yokoyama, Masaki Hashizume and Tetsuo Tada : Temperature Dependence of Ocsillation Frequency in Interconnect Tests of 3D ICs with a Ring Oscillator, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 80, Sep. 2017.
54.	須崎晴登, Isao Tsukimoto, Hiroyuki Yotsuyanagi and Masaki Hashizume : Evaluation of Detectability for Soldered LSI with Resistive Open Fault by Supply Current Test Method, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 79, Sep. 2017.
55.	Tomohiro Katayama, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yoshinobu Higami and Hiroshi Takahashi : Evaluation of the Feasibility of Resistive Open Fault Detection by Difference of Path Delay Ranking, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 86, Sep. 2017.
56.	Daisuke Yabui, Hiroyuki Yotsuyanagi and Masaki Hashizume : BC1タイプのバウンダリスキャンテスト回路を用いた実装基板のオンライン配線検査法, 第27回マイクロエレクトロニクスシンポジウム講演論文集, 351-354, Aug. 2017.
57.	Ayumu Kambara, Hiroyuki Yotsuyanagi and Masaki Hashizume : On Fault Coverage by Low Transition Pattern for IDDT-based Open Fault Testing, 電子情報通信学会総合大会講演論文集, 139, Mar. 2017.
58.	Kouhei Ohtani, Daisuke Suga, Hiroyuki Yotsuyanagi and Masaki Hashizume : Test Circuit for Interconnect Tests Based on The Number of Charging Times, 第31回エレクトロニクス実装学会春季講演大会, 62-65, Mar. 2017.
59.	Daisuke Yabui, Hiroyuki Yotsuyanagi and Masaki Hashizume : Online Interconnect Test Method of Assembled PCB Circuits with IEEE 1149.1 Test Circuits, 第31回エレクトロニクス実装学会春季講演大会, 58-61, Mar. 2017.
60.	Morito Niseki, Toshinori Hosokawa, Masayoshi Yoshimura, Masayuki Arai, Hiroyuki Yotsuyanagi and Masaki Hashizume : An Untestable Fault Identification Method for Sequential Circuits Based on SAT Using Unreachable States, IEICE Technical Report, Vol.116, No.466, 29-34, Feb. 2017.
61.	Shingo Kawatsuka, Hiroyuki Yotsuyanagi and Masaki Hashizume : Design of TDC Embedded in Scan FFs for Testing Small Delay Faults, IEICE Technical Report, Vol.116, No.331, 105-110, Nov. 2016. (Summary) With improvement of semiconductor manufacturing process, small delay becomes more important cause of timing failures. Small delay faults may cause circuit malfunction due to aging deterioration. Therefore, test method for small delay faults is required. We have proposed small delay measurement circuit using TDC(Time-to-Digital Converter) to detect small delay faults on circuit paths. In this paper, we propose new scan FF design that can from a TDC with less area overhead and evaluate its feasibility to detect small delay faults by circuit simulation.
62.	Ryosuke Mori, Hiroyuki Yotsuyanagi and Masaki Hashizume : Calibration of inter-chip delay variation using TDC-embedded boundary scan, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 96, Sep. 2016.
63.	Daichi Miyoshi, Hiroyuki Yotsuyanagi and Masaki Hashizume : An investigation on the effectiveness of detecting un-propagatable open faults using IDDT appearance time sensor, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 95, Sep. 2016.
64.	Kazui Fujitani, Hiroyuki Yotsuyanagi and Masaki Hashizume : Effects of the selection of adjacent lines for assigning logic value and threshold value for fault excitation on open fault test pattern generation time, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 94, Sep. 2016.
65.	Kotaro Ise, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yoshinobu Higami and Hiroshi Takahashi : Effectiveness of discrimination method for resistive open using signal transitions on adjacent lines against defect site at the fault line, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 93, Sep. 2016.
66.	Shingo Kawatsuka, Hiroyuki Yotsuyanagi and Masaki Hashizume : Investigation on effect of variations for delay resolution of scan FFs with embedded TDC, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 92, Sep. 2016.
67.	Yohei Kakee, Hiroyuki Yotsuyanagi and Masaki Hashizume : Experimental Feasibility Analysis of Open Defect Detection with Built-in IDDT Appearance Time Sensor, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 88, Sep. 2016.
68.	Kouhei Ohtani, Daisuke Suga, Hiroyuki Yotsuyanagi and Masaki Hashizume : Open Defect Detection with Electrical Test Circuit Based on Injected Charge Volume, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 87, Sep. 2016.
69.	Seiya Tanaka, Isao Tsukimoto, Hiroyuki Yotsuyanagi and Masaki Hashizume : Voltage for Applying AC Electric Filed from Adjacent Trace to Detect Output Lead Open by Supply Current Test, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 86, Sep. 2016.
70.	Akihiro Odoriba, Hiroyuki Yotsuyanagi, Masaki Hashizume and Shyue-Kung Lu : Feasibilty of Changing Process Monitoring of Capacitive Open Defects in 3D ICs with a Built-in Electrical Test Circuit, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 85, Sep. 2016.
71.	Masashi Okamoto, Akihiro Odoriba, Fara Binti Ali Ashikin, Hiroyuki Yotsuyanagi, Masaki Hashizume and Shyue-Kung Lu : Feasibility of Capacitive Open Defect Detection with a Built-in Electrical Test Circuit Made of Diodes and nMOS Switches, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 84, Sep. 2016.
72.	Yuki Ikiri, Kousuke Nanbara, Hiroyuki Yotsuyanagi, Masaki Hashizume and Shyue-Kung Lu : Threshold Values of Electrical Interconnect Tests with Built-in Test Circuit Made of nMOS Diodes, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 83, Sep. 2016.
73.	Fara Ashikin Binti Ali, Shoichi Umizu, Yuki Ikiri, Hiroyuki Yotsuyanagi, Masaki Hashizume and Lu Shyue-Kung : Electrical Interconnect Test Method of Assembled PCBs without Boundary Scan Flip Flops, 第30回エレクトロニクス実装学会春季講演大会, 195-197, Mar. 2016.
74.	Takumi Miyabe, Hiroyuki Yotsuyanagi, Masaki Hashizume and Roth Zvi : Feasibility of Electrical Test of Opened Leads in Assembled PCBs with Built-in Test Circuit by DC Stimulus, 第30回エレクトロニクス実装学会春季講演大会, 198-200, Mar. 2016.
75.	Kazui Fujitani, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yoshinobu Higami and Hiroshi Takahashi : Reduction of open fault test pattern generation time by selection of adjacent lines for assigning logic value, IEICE Technical Report, Vol.115, No.449, 13-18, Feb. 2016.
76.	Kotaro Ise, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yoshinobu Higami and Hiroshi Takahashi : On discrimination method of a resistive open using delay variation induced by signal transitions on adjacent lines, IEICE Technical Report, Vol.115, No.339, 31-36, Dec. 2015.
77.	Ryosuke Mori, Hiroyuki Yotsuyanagi and Masaki Hashizume : A study on multiple path selection conditions in delay testing using design-for-testability circuit, IEICE Technical Report, Vol.115, No.339, 25-30, Dec. 2015.
78.	Seiya Tanaka, Isao Tsukimoto, Hiroyuki Yotsuyanagi and Masaki Hashizume : Comparison of IDDQ Flowing Time by Voltage Wave-Form for Applying AC Electric Filed on Supply Current Test, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 104, Sep. 2015.
79.	Takumi Miyabe, Hiroyuki Yotsuyanagi, Masaki Hashizume and Zvi Roth : Feasibility of Electrical Interconnect Tests of Hard Open Defects with Built-in Test Circuit by a Triangle Waveform Stimulus, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 103, Sep. 2015.
80.	Kousuke Nanbara, Hiroyuki Yotsuyanagi, Masaki Hashizume and Shyue-Kung Lu : Threshold Values in Electrical Interconnect Tests with Built-in Electrical Test Circuit Made of nMOS Switches, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 102, Sep. 2015.
81.	Shunsuke Kajitani, Hiroyuki Yotsuyanagi and Masaki Hashizume : Testability Analysis of Defects in CMOS Pixel Circuits by Circuit Simulation, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 101, Sep. 2015.
82.	Yuki Ikiri, Hiroyuki Yotsuyanagi, Masaki Hashizume, Hiroshi Yokoyama, Tetsuo Tada and Shyue-Kung Lu : Propagation Delay of TSV Repair Circuit in a 3D Stacked Memory IC, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 100, Sep. 2015.
83.	Akihiro Odoriba, Hiroyuki Yotsuyanagi, Masaki Hashizume and Shyue-Kung Lu : Feasibility of Electrical Tests for Capacitive Interconnect Open Defects in 3D ICs by a Built-in Test Circuit with Diodes, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 99, Sep. 2015.
84.	Daisuke Suga, Hiroyuki Yotsuyanagi and Masaki Hashizume : Feasibility of Supply Current Tests by Amount of Charge Injected into Interconnects between ICs, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 96, Sep. 2015.
85.	Daichi Miyoshi, Hiroyuki Yotsuyanagi and Masaki Hashizume : A study on test pattern ordering for detecting open faults using IDDT appearance time, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 121, Sep. 2015.
86.	Motoki Usui, Hiroyuki Yotsuyanagi and Masaki Hashizume : Test Data Reduction by BAST Architecture using PRPG Feedback Loop Control and Reseeding Circuit, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 120, Sep. 2015.
87.	Ryosuke Mori, Hiroyuki Yotsuyanagi and Masaki Hashizume : Experimental Evaluation of two-path delay measurement using TDC-embedded boundary scan, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 118, Sep. 2015.
88.	Takayuki Ishiba, Hiroyuki Yotsuyanagi and Masaki Hashizume : Improvement of the delay element in delay measurement circuit for testing small delay faults, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 117, Sep. 2015.
89.	Kotaro Ise, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yoshinobu Higami and Hiroshi Takahashi : On the detectability of a resistive open by multivariate analysis using signal transitions on adjacent lines, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 114, Sep. 2015.
90.	Kazui Fujitani, Hiroyuki Yotsuyanagi and Masaki Hashizume : Reduction of candidate adjacent lines for assigning logic value considering parallel length in open fault testing, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 113, Sep. 2015.
91.	Youhei Miyamoto, Hiroyuki Yotsuyanagi and Masaki Hashizume : Evaluation of delay detection capability of VDL in TSV fault detection circuit, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 112, Sep. 2015.
92.	Keigo Hamada, Hiroyuki Yotsuyanagi and Masaki Hashizume : On Fault Detection of TSV by Boundary-Scan for delay faults, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 111, Sep. 2015.
93.	Masaki Hashizume, Akihiro Odoriba, Shoichi Umezu, Ashikin Ali Fara Binti, Hiroyuki Yotsuyanagi and Lu Shyue-Kung : An Electrical Interconnect Test Circuit for Detecting Resistive Open Defects in 3D ICs, 第29回エレクトロニクス実装学会講演大会, 431-432, Mar. 2015.
94.	Yudai Shiraishi, Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Yokoyama, Tetsuo Tada and Lu Shyue-Kung : Threshold Setting Method of Electrical Test Method for Open Defects at a Data Bus in SRAM Circuit, 第29回エレクトロニクス実装学会講演大会, 433-434, Mar. 2015.
95.	Youhei Miyamoto, Hiroyuki Yotsuyanagi and Masaki Hashizume : Investigation of the area reduction of control part and observation part in TSV fault detection circuit, IEICE Technical Report, Vol.114, No.329, 3-8, Nov. 2014. (Summary) 故障TSVで発生する遅延量は極めて小さく，故障検出が困難である．そこで，隣接TSVを考慮したTSV故障検出回路が提案されている．しかし，従来回路では各TSVにFFを追加し検査対象TSVの指定を行うため，TSVの増加に伴い回路面積の増大が問題となる．また，遅延検出回路として使用されるVDL(Vernier Delay Line)の分解能と回路面積の関係についての評価はされていなかった．本研究では，TSV故障検出回路の回路面積の削減のため，コア検査用として組み込まれているBSC(Boundary Scan Cell)を利用しての制御部の改良とVDL回路部内のゲート段数評価を行った．
96.	Shoichi Umezu, Hiroyuki Yotsuyanagi and Masaki Hashizume : A Built-in Electrical Test Circuit for Soft Open Defects at Interconnects between Dies in 3D ICs, Proceedings of the Society Conference of IEICE, 85, Sep. 2014.
97.	Akihiro Fujiwara, Hiroyuki Yotsuyanagi and Masaki Hashizume : On defecting a fault in TSV away using double ring oscillators, Proceedings of the Society Conference of IEICE, 47, Sep. 2014.
98.	Hiroki Sakurai, Hiroyuki Yotsuyanagi and Masaki Hashizume : Verification of Measured Timing Slack Using Time-to-Digital Converter Embedded in Boundary Scan, Proceedings of the Society Conference of IEICE, 46, Sep. 2014.
99.	Ryota Mori, Hiroyuki Yotsuyanagi and Masaki Hashizume : Test Data Reduction Method for BIST-Aided Scan Test by Controlling Scan Shift, Proceedings of the Society Conference of IEICE, 45, Sep. 2014.
100.	Fang Chih-Chan, Hiroyuki Yotsuyanagi and Masaki Hashizume : A Test Pattern Matching Method on BAST Architecture to Reduce Bit-flipping and Skipping of Random Patterns, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 114, Sep. 2014.
101.	Motoki Usui, Hiroyuki Yotsuyanagi and Masaki Hashizume : On BAST Scheme Using Loop Control of PRPG for Test Data Reduction, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 113, Sep. 2014.
102.	Keigo Hamada, Hiroyuki Yotsuyanagi and Masaki Hashizume : Design of timing slack measurement circuit for delay fault testing, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 112, Sep. 2014.
103.	Takayuki Ishiba, Hiroyuki Yotsuyanagi and Masaki Hashizume : Delay measurement circuit for testing small delay faults on paths in sequential circuits, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 111, Sep. 2014.
104.	Takuma Matsuda, Hiroyuki Yotsuyanagi and Masaki Hashizume : On Feasibility of Diagnosis Using Test Pattern Generation Method for Via Open Faults by Preventing the Overlap of Assignment to Adjacent Lines, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 110, Sep. 2014.
105.	Yuki Himeo, Masatake Akutagawa, Hiroyuki Yotsuyanagi, Masaki Hashizume and Shyue-Kung Lu : Test Input Reduction of Electrical Tests for Open Defects at Bi-directional Interconnects in PCB circuits, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 103, Sep. 2014.
106.	Kousuke Nanbara, Hiroyuki Yotsuyanagi and Masaki Hashizume : Threshold Values in Electrical Interconnect Tests with Testable Designed ESD Input Protection Circuits, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 102, Sep. 2014.
107.	Daisuke Suga, Hiroyuki Yotsuyanagi and Masaki Hashizume : Feasibility of Supply Current Tests by Amount of Charge Injected into ICs, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 101, Sep. 2014.
108.	Shoichi Umezu, Hiroyuki Yotsuyanagi and Masaki Hashizume : 組み込み型電気検査回路によるICのピン浮き検査可能性実験, 第24回マイクロエレクトロニクスシンポジウム論文集, 375-378, Sep. 2014.
109.	Shoichi Umezu, Hiroyuki Yotsuyanagi and Masaki Hashizume : Tests of Capacitive Open Defects between ICs with a Built-in Electrical Test Circuit, 2014 年電子情報通信学会総合大会情報・システム講演論文集1, 125, Mar. 2014.
110.	Shoichi Umezu, Hiroyuki Yotsuyanagi and Masaki Hashizume : A Built-in Current Sensor for Supply Current Tests of Pin Opens in Assembled PCBs, 第28回エレクトロニクス実装学会講演大会, 239-240, Mar. 2014.
111.	Masaki Hashizume, Yudai Shiraishi, Hiroyuki Yotsuyanagi and Lu Shyue-Kung : Electrical Test Method of Open Defects at a Data Bus in SRAM ICs, 第28回エレクトロニクス実装学会講演大会, 237-238, Mar. 2014.
112.	Ryota Mori, Hiroyuki Yotsuyanagi and Masaki Hashizume : Test Data Reduction Method for BIST-Aided Scan Test by Controlling Scan Shift and Partial Reset of Inverter Code, IEICE Technical Report, Vol.113, No.430, 55-60, Feb. 2014.
113.	Hiroki Sakurai, Hiroyuki Yotsuyanagi and Masaki Hashizume : On Feasibility of Delay Detection by Time-to-Digital Converter Embedded in Boundary-Scan, IEICE Technical Report, Vol.113, No.430, 7-12, Feb. 2014.
114.	Ryo Ando, 月本功, Masao Takagi, Hiroyuki Yotsuyanagi and Masaki Hashizume : Detection of Open Faults in Solder Ball of BGA LSI by Supply Current Test under AC Electric Field, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 100, Sep. 2013.
115.	Shohei Matsukawa, Hiroshi Takahashi, Yoshinobu Higami, Hiroyuki Yotsuyanagi and Masaki Hashizume : Generating diagnostic tests for resistive open faults, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 125, Sep. 2013.
116.	Hiroto Ohguri, Hiroyuki Yotsuyanagi and Masaki Hashizume : Analysis of Delay Caused by a Resistive Open Considering Signal Direction of Adjacent Lines, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 129, Sep. 2013.
117.	Seiki Hanabusa, Masaki Hashizume and Hiroyuki Yotsuyanagi : Test Data Reduction Method of BIST-Aided Scan Test by Scan Chain Replacement with Design Constraints Scan Chains, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 128, Sep. 2013.
118.	Ryota Mori, Masaki Hashizume and Hiroyuki Yotsuyanagi : Test Data Reduction Method by BIST-Aided Scan Test Using Partial Reset of Inverter Code, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 127, Sep. 2013.
119.	Jun Yamashita, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yoshinobu Higami and Hiroshi Takahashi : A Study on SAT-based Test Generation for Detecting Small Delay Faults Considering Effect of Adjacent Lines, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 126, Sep. 2013.
120.	Shoichi Umezu, Masaki Hashizume and Hiroyuki Yotsuyanagi : Feasibility of Electrical Interconnect Testing with Testable Designed Circuit Preventing from ESD Protection Capability Reduction, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 114, Sep. 2013.
121.	Yuki Himeo, Masatake Akutagawa, Hiroyuki Yotsuyanagi, Masaki Hashizume and Shyue-Kung Lu : Experimental Evaluation of Electrical Test Method for Open Defects at Bi-directional Interconnects, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 113, Sep. 2013.
122.	Shohei Suenaga, Hiroyuki Yotsuyanagi and Masaki Hashizume : Built-in IDDT Appearance Time Sensor Design for Experimental Evaluation, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 112, Sep. 2013.
123.	Shingo Saijo, Hiroyuki Yotsuyanagi and Masaki Hashizume : Feasibility of Electrical Testing for Layout Designed CMOS Sensor Circuit, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 111, Sep. 2013.
124.	Takanobu Nimiya, Hiroyuki Yotsuyanagi and Masaki Hashizume : Delay Test Method Considering Process Variations Using Time-to-Digital Converter Embedded in Boundary Scan, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 106, Sep. 2013.
125.	Daisuke Ikeji, Hiroyuki Yotsuyanagi and Masaki Hashizume : On Feasibility of Delay Test for Multiple Paths Using the Delay-Testable Circuit, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 105, Sep. 2013.
126.	Masanori Nakamura, Hiroyuki Yotsuyanagi and Masaki Hashizume : On Fault Detection of TSV for Control Signal of TSV Test Circuit, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 104, Sep. 2013.
127.	Akihiro Fujiwara, Hiroyuki Yotsuyanagi and Masaki Hashizume : On the proposal and evaluation of ring-oscillator for TSV fault detection considering the effect of adjacent TSVs, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 103, Sep. 2013.
128.	Ei Haraguchi, Hiroyuki Yotsuyanagi, Tetsuo Tada, Shyue-Kung Lu, Zvi Roth and Masaki Hashizume : High Precision Estimation Method of Output Voltage at Hard Opened TSV from Electromagnetic Simulation Results, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 102, Sep. 2013.
129.	Takao Kusaka, Hiroyuki Yotsuyanagi and Masaki Hashizume : On Feasibility of Diagnosis Method of Via-Open Defects on the Same Line using the Coupling Effects, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 101, Sep. 2013.
130.	Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Yotsuyanagi, Masaki Hashizume, Koji Yamazaki and Toshiyuki Tsutsumi : 3次元LSIにおけるTSVの故障検査および特性評価に関する研究, STARCワークショップ2013, Sep. 2013.
131.	小野安季良, 高木正夫, Hiroyuki Yotsuyanagi and Masaki Hashizume : パッケージ内に電極を内蔵したICの入力部断線の交流電界印加時の電流テスト, 第27回エレクトロニクス実装学会講演大会, 53-54, Mar. 2013.
132.	Masaki Hashizume, Masatake Akutagawa, Lu Shyue-Kung and Hiroyuki Yotsuyanagi : Electrical Testing of Bidirectional Interconnects with IEEE1149.1 Architecture, 第27回エレクトロニクス実装学会講演大会, 55-56, Mar. 2013.
133.	Masanori Nakamura, Hiroyuki Yotsuyanagi and Masaki Hashizume : On Fault detection method considering adjacent TSVs for a delay fault in TSV, IEICE Technical Report, Vol.112, No.429, 31-36, Feb. 2013.
134.	Hiroto Ohguri, Hiroyuki Yotsuyanagi, Masaki Hashizume, Toshiyuki Tsutsumi, Koji Yamazaki, Yoshinobu Higami and Hiroshi Takahashi : Characteristic Analysis of Signal Delay for Resistive Open Fault Detection, IEICE Technical Report, Vol.112, No.429, 25-30, Feb. 2013.
135.	Takao Kusaka, Hiroyuki Yotsuyanagi and Masaki Hashizume : On Identification of Via-Open Defects Using the Coupling Effects of Adjacent Lines, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 153, Sep. 2012.
136.	Jun Yamashita, Hiroyuki Yotsuyanagi, Masaki Hashizume and Kozo Kinoshita : On Test Detectability Analysis Using SAT Solver for Detecting Open Faults Considering Adjacent Line Effects, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 151, Sep. 2012.
137.	Daisuke Ikeji, Yuuki Suenobu, Hiroyuki Makimoto, Hiroyuki Yotsuyanagi and Masaki Hashizume : Derivation of the Additional Delay Required for the Design for Delay Fault Testing Using a STA, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 149, Sep. 2012.
138.	Yasuhiko Okada, Hiroyuki Yotsuyanagi and Masaki Hashizume : Test Data Reduction Method by BIST-Aided Scan Test Using Controlling the Number of Shifting Inverter Code, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 148, Sep. 2012.
139.	Shingo Saijo, Hiroyuki Yotsuyanagi, Masaki Hashizume and Kozo Kinoshita : Feasibility of Electrical Testing for Functional Faults in CMOS Pixel Circuits, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 127, Sep. 2012.
140.	Shohei Suenaga, Hiroyuki Yotsuyanagi and Masaki Hashizume : Necessary Condition of Detecting Open Fault by Built-in Sensor for IDDT Testing, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 129, Sep. 2012.
141.	Yoshihiko Miyamori, Hiroyuki Yotsuyanagi and Masaki Hashizume : Testability by TR Analysis of Supply Current Testable DACs of Resistor String Type, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 130, Sep. 2012.
142.	Ei Haraguchi, Shohei Kondo, Hiroyuki Yotsuyanagi, Tetsuo Tada and Masaki Hashizume : An Estimation Method for Output Voltage of Hard Opened TSV, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 138, Sep. 2012.
143.	Hiroto Ohguri, Hiroyuki Yotsuyanagi and Masaki Hashizume : An Analysis of the Delay Caused by Resistive Open Fault in Congested Routing, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 139, Sep. 2012.
144.	Masanori Nakamura, Hiroyuki Yotsuyanagi and Masaki Hashizume : Fault Analysis of an Open Defect in TSV Array, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 140, Sep. 2012.
145.	Takeshi Okumura, 小西朝陽, Hiroyuki Yotsuyanagi and Masaki Hashizume : Feasibility of Electrical Testing for Open Defects at Fan-out Branch in PCB Circuits, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 141, Sep. 2012.
146.	Masamune Fuji, Hiroyuki Yotsuyanagi, Masaki Hashizume and Tomoaki Konishi : Testability of Resistive Open Interconnects between ICs by Electrical Testing, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 142, Sep. 2012.
147.	Tomoaki Konishi, Hiroyuki Yotsuyanagi and Masaki Hashizume : Experimental Evaluation of Electrical Test Circuit for Open Defects between ICs, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 143, Sep. 2012.
148.	Hiroshi Takahashi, Yoshinobu Higami, Toshiyuki Tsutsumi, Koji Yamazaki, Hiroyuki Yotsuyanagi and Masaki Hashizume : Empirical study for signal integrity-defects, IEICE Technical Report, Vol.112, No.102, 21-26, Jun. 2012.
149.	Jun Yamashita, Kozo Kinoshita, Hiroyuki Yotsuyanagi and Masaki Hashizume : 隣接線を考慮したパターン併合によるオープン故障用テストパターン生成, 電子情報通信学会総合大会講演論文集, D-10-3, Mar. 2012.
150.	Tomoaki Konishi, Hiroyuki Yotsuyanagi and Masaki Hashizume : ESD入力保護能力を低下させないIC間断線の電気的検査用回路, 電子情報通信学会総合大会講演論文集, D-10-4, Mar. 2012.
151.	小野安季良, Hiroyuki Yotsuyanagi, 高木正夫 and Masaki Hashizume : QFP ICの半断線故障に対する電流テスト検査法, 第26回エレクトロニクス実装学会講演大会, 168-169, Mar. 2012.
152.	Tomoaki Konishi, Hiroyuki Yotsuyanagi and Masaki Hashizume : IC接続部断線の電気的検査を可能にする組み込み型検査用回路, 第26回エレクトロニクス実装学会講演大会, 166-167, Mar. 2012.
153.	Yasuhiko Okada, Hiroyuki Yotsuyanagi and Masaki Hashizume : A BIST-Aided Scan Test using Shifting Inverter Code and a TPG Method for Test Data Reduction, IEICE Technical Report, Vol.111, No.325, 133-138, Nov. 2011.
154.	Hiroyuki Makimoto, Hiroyuki Yotsuyanagi and Masaki Hashizume : On the design for testability method using Time to Digital Converter for detecting delay faults, IEICE Technical Report, Vol.111, No.325, 185-190, Nov. 2011.
155.	Takafumi Amo, Hiroyuki Yotsuyanagi and Masaki Hashizume : X-Filling Method for Reducing Localized IR Drop using Weighted Switching Estimation at Flip-flops, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 143, Sep. 2011.
156.	Kenji Gouda, 奥山奨太郎, Hiroyuki Yotsuyanagi and Masaki Hashizume : Test Patern Generation for Via-Open Defects Considering Fanout Branches and the Coupling Effects of Adjacent Lines, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 142, Sep. 2011.
157.	Takeshi Murakami, Hiroyuki Yotsuyanagi and Masaki Hashizume : Testability of Capacitive Open Defects in Current Testable Level Shifter by Current Testing, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 141, Sep. 2011.
158.	Ryosuke Saeki, Hiroyuki Yotsuyanagi and Masaki Hashizume : Test Pattern Generation by Focusing on the Number of Don't Cares for Reducing Pattern-dependent Deviation of IDDQ, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 140, Sep. 2011.
159.	Katsuya Manabe, Hiroyuki Yotsuyanagi and Masaki Hashizume : Estimation Model of Output Voltage on a Hard Opened Metal Wire in ICs, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 138, Sep. 2011.
160.	西川大樹, 富田泰基, 月本功, Masao Takagi, Hiroyuki Yotsuyanagi and Masaki Hashizume : Affect of Reducing Current Draw on Supply Current Test for Detecting Lead Opens of CMOS LSI, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 130, Sep. 2011.
161.	(名) Widianto, Akira Ono, Hiroyuki Yotsuyanagi, Masao Takagi and Masaki Hashizume : Feasibility of Open Lead Detection with Built-in Current Sensor, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 119, Sep. 2011.
162.	Masaki Hashizume, Yutaka Hata, Hiroyuki Yotsuyanagi and 三浦幸也 : A Supply Current Testable DAC of Decoder Type, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 118, Sep. 2011.
163.	Shohei Kondo, Hiroyuki Yotsuyanagi, Tetsuo Tada and Masaki Hashizume : Output Voltage of Completely Opened TSV by Electromagnetic Simulation, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 116, Sep. 2011.
164.	Tomoaki Konishi, Hiroyuki Yotsuyanagi and Masaki Hashizume : Feasibility of Electrical Testing for Lead Short of QFP ICs, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 117, Sep. 2011.
165.	Masaki Hashizume, Yutaka Hata, Hiroyuki Yotsuyanagi and 三浦幸也 : 抵抗ラダー型DAC 内MOS 短絡の電流テスト容易化設計, 2011年電子情報通信学会総合大会, 121, Mar. 2011.
166.	Shohei Kondo, Hiroyuki Yotsuyanagi and Masaki Hashizume : 電磁界シミュレータによるTSVの半断線で生じる故障動作解析, 第25回エレクトロニクス実装学会講演大会, 205-206, Mar. 2011.
167.	Masaki Hashizume, Tomoaki Konishi and Hiroyuki Yotsuyanagi : バウンダリスキャンテスト機構を流用する部品実装基板の電気的テストとその可能性, 第25回エレクトロニクス実装学会講演大会, 201-204, Mar. 2011.
168.	Masashi Ishikawa, Hiroyuki Yotsuyanagi and Masaki Hashizume : Test Data Reduction method for BIST-aided Scan Test Using Shifting Inverter Code, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 102, Sep. 2010.
169.	Ryosuke Saeki, Hiroyuki Yotsuyanagi and Masaki Hashizume : Test Pattern Generation to Reduce the Variations in IDDQ due to Vector Dependencies, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 101, Sep. 2010.
170.	Takeshi Murakami, Hiroyuki Yotsuyanagi and Masaki Hashizume : Testability of Capacitive Open Defects in Level Shifter, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 100, Sep. 2010.
171.	Yuichi Ihokura, Hiroyuki Yotsuyanagi, Masaki Hashizume and Kozo Kinoshita : Feasibility of Electrical Testing for CMOS Pixel Circuits in Prototyped ICs, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 99, Sep. 2010.
172.	Shohei Kondo, Hiroyuki Yotsuyanagi, Tetsuo Tada and Masaki Hashizume : Fault Analysis of Hard Open Vias in ICs by Electromagnetic Simulation, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 98, Sep. 2010.
173.	Satoru Okada, Hiroyuki Yotsuyanagi, Masaki Hashizume, Toshiyuki Tsutsumi, Koji Yamazaki, Yoshinobu Higami and Hiroshi Takahashi : An Analysis of the Signal Delay Caused by a Resistive Open Fault in Interconnect Lines, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 97, Sep. 2010.
174.	T. Tomida, Isao Tukimoto, Masao Takagi, Hiroyuki Yotsuyanagi and Masaki Hashizume : Quiescent Supply Current of Deep Submicron Process FPGAs with Lead Open, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 81, Sep. 2010.
175.	Shingo Harada, Ogawa Shintaro, Hiroyuki Yotsuyanagi, Hiroyoshi Sei and Masaki Hashizume : An LED Lighting Control Circuit to Measure Light Wavelength Dependence on Circadian Rhythm in Mice, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 80, Sep. 2010.
176.	Masaki Hashizume, 内倉健一, 小野安季良, Hiroyuki Yotsuyanagi and 高木正夫 : IC内組込型インターコネクトオープン検出回路, 第24回エレクトロニクス実装学会講演大会, 48-49, Mar. 2010.
177.	Toshiyuki Tsutsumi, Yasuyuki Kariya, Koji Yamazaki, Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Takahashi, Yoshinobu Higami and Yuzo Takamatsu : Consideration of Open Faults Model Based on Digital Measurement of TEG Chip, IEICE Technical Report, Vol.109, No.416, 75-80, Feb. 2010.
178.	Hiroshi Takahashi, Yoshinobu Higami, Yuta Shudo, Yuji Takamune, Yuzo Takamatsu, Toshiyuki Tsutsumi, Koji Yamazaki, Hiroyuki Yotsuyanagi and Masaki Hashizume : Modeling resistive open faults and generating their tests, IEICE Technical Report, Vol.109, No.416, 19-24, Feb. 2010.
179.	Takaaki Nakano, Hiroyuki Yotsuyanagi and Masaki Hashizume : On multiple scan chains considering localized IR-drop, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 134, Sep. 2009.
180.	Ryota Kuribayashi, Hiroyuki Yotsuyanagi and Masaki Hashizume : Test Generation for Open Faults Considering Parallel Wire Lengths of Adjacent Lines, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 133, Sep. 2009.
181.	Hiroshi Tarumi, Hiroyuki Yotsuyanagi and Masaki Hashizume : On Testability Evaluation of Open-via Defects Using Test Pattern for Stuck-at Faults, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 132, Sep. 2009.
182.	Katsuya Manabe, Yuichi Yamada, Takuya Yoshida, Hiroyuki Yotsuyanagi and Masaki Hashizume : Effects on Opened Interconnection Line by Logic Signal in the Layer, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 131, Sep. 2009.
183.	Yuichi Yamada, Takuya Yoshida, Hiroyuki Yotsuyanagi and Masaki Hashizume : Effects on Signal Propagation at Opened Interconnection Line by Shape of Open Defect, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 130, Sep. 2009.
184.	Isao Tukimoto, T. Tomida, Masao Takagi, Hiroyuki Yotsuyanagi and Masaki Hashizume : Mesurement of Quiescent Supply Current of 90nm FPGA with Lead Open under AC Electric Field, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 115, Sep. 2009.
185.	Kenichi Uchikura, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Masaki Hashizume, Mitsuo Shimotani, Tetsuo Tada and Takeshi Koyama : Test Probe for Detecting Open Leads of QFP ICs by Current Testing, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 114, Sep. 2009.
186.	Yuichi Ihokura, Hiroyuki Yotsuyanagi, Masaki Hashizume, K. Shimada and Kozo Kinoshita : Feasibility of Electrical Tests for Opens in CMOS Pixel Circuits, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 113, Sep. 2009.
187.	Shingo Harada, Tomoyuki Kuroyama, Hiroyuki Yotsuyanagi and Masaki Hashizume : Current Testability of Opens and Shorts in Operational Amplifier, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 112, Sep. 2009.
188.	Kazuya Nakaminami, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yukinori Nakajima and Kozi Kinoshita : DFT for Current Testing of Level Shifters, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 111, Sep. 2009.
189.	Masaki Hashizume, Yutaka Hata, Hiroyuki Yotsuyanagi and Yukiya Miura : A Current Testable Design of Resistor Ladder DACs, 電子情報通信学会総合大会講演論文集, 155, Mar. 2009.
190.	Ryota Kuribayashi, Hiroyuki Yotsuyanagi and Masaki Hashizume : Test Generation for Open Faults with Assignment of the Logic Value to Adjacent Lines, 電子情報通信学会総合大会講演論文集, 157, Mar. 2009.
191.	Hiroshi Tarumi, Hiroyuki Yotsuyanagi and Masaki Hashizume : On Via-open Defects Corresponding to Multiple Stuck-at Faults and Test Generation for These Defects, 電子情報通信学会総合大会講演論文集, 156, Mar. 2009.
192.	Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, 小野安季良 and 高木正夫 : QFP ICのリード浮きの電気的検出用回路, 第23回エレクトロニクス実装学会講演大会, 75-77, Mar. 2009.
193.	小野安季良, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, 高木正夫 and Masaki Hashizume : Open Lead Detection of Power Supply Leads by Measuring Supply Current of Test Circuit, Proceedings of the 23rd JIEP Annual Meeting, 79-80, Mar. 2009.
194.	Tetsuya Watanabe, Hiroshi Takahashi, Yoshinobu Higami, Toshiyuki Tsutsumi, Koji Yamazaki, Hiroyuki Yotsuyanagi, Masaki Hashizume and Yuzo Takamatsu : On Tests to Detect Open faults with Considering Adjacent Lines, IEICE Technical Report, Vol.108, No.431, 37-42, Feb. 2009.
195.	Toshiyuki Tsutsumi, Yasuyuki Kariya, Koji Yamazaki, Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Takahashi, Yoshinobu Higami and Yuzo Takamatsu : Analysis of Open Fault using TEG Chip, IEICE Technical Report, Vol.108, No.298, 19-24, Nov. 2008.
196.	Hiroshi Tarumi, Hiroyuki Yotsuyanagi and Masaki Hashizume : Extraction of open-via defects for test generation, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 129, Sep. 2008.
197.	Masayuki Yamamoto, Hiroyuki Yotsuyanagi and Masaki Hashizume : Test Time Reduction method for BAST Architecture by keeping Inversion Signal, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 128, Sep. 2008.
198.	Takaaki Nakano, Hiroyuki Yotsuyanagi and Masaki Hashizume : On the transitions caused by scan testing considering localized IR-drop, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 127, Sep. 2008.
199.	Tatsuya Shimamoto, Eiji Tasaka, Toshihiro Kayahara, Hiroyuki Yotsuyanagi and Masaki Hashizume : At-Speed Test Program for Bus Faults in PIC16F84A, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 126, Sep. 2008.
200.	Keisuke Nishita, Masaki Hashizume and Hiroyuki Yotsuyanagi : Self-Biased IDDT Appearance Time Sensor, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 111, Sep. 2008.
201.	Yutaka Hata, Hiroyuki Yotsuyanagi, Masaki Hashizume and Yukiya Miura : Testability of A Current Testable DAC, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 110, Sep. 2008.
202.	Kazuya Nakaminami, Hiroyuki Yotsuyanagi, Masaki Hashizume and Kozi Kinoshita : Testability of High Resistive Faults in Level Shifter by Delay Testing, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 109, Sep. 2008.
203.	Yuuki Ogata, Hiroyuki Yotsuyanagi and Masaki Hashizume : An analysis of the signal delay caused by a resistive open defect using TCAD, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 108, Sep. 2008.
204.	Yuichi Yamada, Hiroyuki Yotsuyanagi and Masaki Hashizume : Effects on Signal Integrity by High Resisistive Open on Interconnects, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 107, Sep. 2008.
205.	Yuuya Oyamada, Hiroyuki Yotsuyanagi and Masaki Hashizume : Identification of adjacent lines that cause logic error with an open fault, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 105, Sep. 2008.
206.	Kenji Kato, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Masaki Hashizume : Faulty Effect of Interconnect Open in 0.35 CMOS IC, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 104, Sep. 2008.
207.	Isao Tukimoto, Tohru Ikegami, Masao Takagi, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Masaki Hashizume : Effects of Voltage of Nearby Wiring on AC Applied Voltage Needed for Lead Opens Detection of CMOS IC by Supply Current Test under AC Electric Field, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 103, Sep. 2008.
208.	M Matsuo, Akira Ono, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Masao Takagi and Masaki Hashizume : Test Speed of Open Lead Detection Method Based on Output Logical Change of CMOS Logic IC, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 102, Sep. 2008.
209.	Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Mitsuo Shimotani, Tetsuo Tada and Takeshi Koyama : Supply Current Test Circuit for Locating Open Leads of QFP ICs, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 101, Sep. 2008.
210.	Kenichi Uchikura, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Masaki Hashizume : Prototyping of the Circuit to Detect Lead Open, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 100, Sep. 2008.
211.	Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Hiroyuki Yotsuyanagi, Masaki Hashizume and Yuzo Takamatsu : Improving the Diagnostic Quality of Open Faults, IEICE Technical Report, Vol.108, No.99, 29-34, Jun. 2008.
212.	Akira Ono, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Masao Takagi and Masaki Hashizume : Open Lead Detection of QFP CPLD IC by Current Testing, 第22回エレクトロニクス実装学会講演大会, 143-144, Mar. 2008.
213.	Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Syuhei Kadoyama, Tetsuya Watanabe, Yuzo Takamatsu, Toshiyuki Tsutsumi, Koji Yamazaki, Hiroyuki Yotsuyanagi and Masaki Hashizume : Fault Diagnosis for Dyinamic Open Faults with Considering Adjacent Lines, IEICE Technical Report, Vol.107, No.482, 7-12, Feb. 2008.
214.	Hiroyuki Yotsuyanagi : テスト容易化設計/テスト容易化論理合成, 第27回STARCアドバンスト講座テスト技術セミナー, 41-61, Dec. 2007.
215.	Yuuki Ogata, Hiroyuki Yotsuyanagi and Masaki Hashizume : An Analysis of the Voltage at a Floating Line Caused by an Open Defect Using Layout Information, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 108, Sep. 2007.
216.	Yuuya Oyamada, Hiroyuki Yotsuyanagi and Masaki Hashizume : On Test Pattern Generation for Open Fault Detection Using Effects of Multiple Adjacent Signal Lines, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 107, Sep. 2007.
217.	Masayuki Yamamoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Kozo Kinoshita : Testability of Opens in Level Shifter, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 103, Sep. 2007.
218.	Yutaka Hata, Junichi Iino, Hiroyuki Yotsuyanagi, Masaki Hashizume and Yukiya Miura : DFT for Current Testing of Resistor String DACs, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 102, Sep. 2007.
219.	Keisuke Nishita, Masaki Hashizume, Hiroyuki Yotsuyanagi and Tetsuo Akita : A Built-in IDDT Sensor, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 101, Sep. 2007.
220.	Tatsuya Shimamoto, Eiji Tasaka, Toshihiro Kayahara, Hiroyuki Yotsuyanagi, Takahiro Oie and Masaki Hashizume : At-Speed Test Program for Stuck-at Faults at Buses in Z80, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 100, Sep. 2007.
221.	Yusaku Kubota, Masaki Hashizume and Hiroyuki Yotsuyanagi : Analysis of Voltage Change of Open Line Caused by Adjacent Signal Change with TCAD, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 98, Sep. 2007.
222.	Tohru Ikegami, Isao Tukimoto, Masao Takagi, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Masaki Hashizume : Supply Current of CPLD with Lead Open on 4 Layers Printed Circuit Board with Ground Layer, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 86, Sep. 2007.
223.	Kohjiro Yano, Masao Takagi, Isao Tukimoto, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Masaki Hashizume : Detecting Output Lead Opens of CMOS LSIs by Supply Current - Change of Voltage Applied to Electrode by Printed Pattern Length, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 85, Sep. 2007.
224.	Akihito Onishi, Akira Ono, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Masaki Hashizume and Masao Takagi : Testability of Supply Current Test Method for Open Lead Detection of QFP CMOS CPLD IC, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 84, Sep. 2007.
225.	Tokurou Takigawa, Mitsuru Tojo, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Masaki Hashizume : Open Lead Detection of A CMOS IC of 0.35um CMOS process, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 83, Sep. 2007.
226.	Mitsuru Tojo, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Masaki Hashizume : Open Detection in a CMOS IC by Supply Current Testing under AC Electric Field Application, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 82, Sep. 2007.
227.	Masaki Hashizume, Masato Nakanishi, Takeshi Iihara, Hiroyuki Yotsuyanagi, Tetsuo Tada and Takeshi Koyama : Testabillity of IDDQ Test Method Based on Wavelet Transformation, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 81, Sep. 2007.
228.	Masato Nakanishi, Masaki Hashizume, Hiroyuki Yotsuyanagi and Yukiya Miura : Evaluation of BIC Sensor for Variation of Vth, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 80, Sep. 2007.
229.	Akira Ono, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Masaki Hashizume, Isao Tsukimoto and Masao Takagi : Testability of Supply Current Test Method for Resistive Open Lead Detection, マイクロエレクトロニクスシンポジウム, 195-198, Sep. 2007. (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1520290882979424512 (CiNii: 1520290882979424512)
230.	Masaki Hashizume, Masahiro Ichimiya and Hiroyuki Yotsuyanagi : Electrical Testing for Open Leads of CMOS QFP ICs, Proc. of Academic Facilities & Laboratories Poster Program, 41-46, Jun. 2007.
231.	Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Yuzo Takamatsu, Masaki Hashizume and Hiroyuki Yotsuyanagi : A method of locating open faults with considering adjacent nets, LSIテスティングシンポジウム, 187-192, Nov. 2006.
232.	Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Masaki Hashizume and Hiroyuki Yotsuyanagi : A proposal of a fault model for an open fault and its fault diagnosis, LSIテスティングシンポジウム, 181-186, Nov. 2006.
233.	Yohsuke Misaki, Hiroyuki Yotsuyanagi and Masaki Hashizume : On Arranging Flip-flops in Scan Trees for Reducing During Test Transitions, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 87, Sep. 2006.
234.	Koji Ike, Hiroyuki Yotsuyanagi and Masaki Hashizume : On the Scan Tree Configuration Method with Routing Constraint, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 86, Sep. 2006.
235.	Takeshi Iihara, Hiroyuki Yotsuyanagi and Masaki Hashizume : On Reducing Testing Time of Multiple-core for Scan Trees, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 85, Sep. 2006.
236.	Mitsuru Tojo, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Masaki Hashizume : Test Equipment for Supply Current Testing with AC Electric Field Applied, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 72, Sep. 2006.
237.	Kohjiro Yano, Masao Takagi, Isao Tukimoto, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Masaki Hashizume : AC Voltage for Generating Electric Field to Detect Output Lead Opens of CMOS LSIs by Supply Current, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 71, Sep. 2006.
238.	Tohru Ikegami, Isao Tukimoto, Masao Takagi, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Masaki Hashizume : Effects of Ground Layer on Testability of Lead Open Detection by Supply Current Test under AC Electric Field, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 70, Sep. 2006.
239.	Masato Nakanishi, Hiroyuki Yotsuyanagi, Masaki Hashizume and Yukiya Miura : BIC Sensor Capable of Adjusting IDDQ Limit, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 69, Sep. 2006.
240.	Tatsuya Shimizu, Daisuke Ezaki, Hiroyuki Yotsuyanagi and Masaki Hashizume : Power Saving by Block Partitioning in Dynamic Stop Watch Circuit, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 76, Sep. 2006.
241.	Seiichi Nishimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Supply Current Test Program for Pin Short Detection in Z80, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 383, Sep. 2005.
242.	Tatsuya Shimizu, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Power Consumption of a Time Varying Power Supplied Dynamic CMOS Adder, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 132, Sep. 2005.
243.	Hiroshi Ohmura, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Testability Evaluation of Open Faults in Consideration of the Voltage of the Adjacent Lines, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 130, Sep. 2005.
244.	Katsumi Inoue, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Design of Scan Tree Configuration of Sequential Circuits using CAD, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 129, Sep. 2005.
245.	Koji Ike, Hiroyuki Yotsuyanagi, Masaki Hashizume and Kozo Kinoshita : On the Arrangement of Flip-Flops in Scan Trees Based on the Fault Effects, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 128, Sep. 2005.
246.	Takashi Sakaguchi, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Yukiya Miura : Torelance of a Built-in IDDQ Test Circuit for Process Variation, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 120, Sep. 2005.
247.	Takeshi Iihara, Masaki Hashizume, Tetsuo Tada, Takeshi Koyama, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Testabillity Analysis System of IDDQ Testing Based on Wavelet Transformation, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 119, Sep. 2005.
248.	Masao Takagi, Masaki Hashizume, Isao Tukimoto, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Effects on Testability of Logic Value Outputting to Faulty Line in Lead Open Detection by Supply Current Testing, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 118, Sep. 2005.
249.	Tatsuya Shimizu, Daisuke Ezaki, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Power Consumption in a Time Varying Power Supplied Dynamic CMOS Timer Circuit, Proceedings of IEICE Society Conference, 92, Sep. 2005.
250.	Seiichi Nishimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : At-Speed Test for Pin Shorts in Z80 by Supply Current Testing, Proceedings of IEICE Society Conference, 83, Sep. 2005.
251.	Takashi Sakaguchi, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Tetsuo Tada, Takeshi Koyama, Yasuhiro Miyagawa, Seiji Tanaka and Toshihiro Kayahara : Fail-safe Evaluation System for Boiler Control Circuits, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 117, Sep. 2004.
252.	Seiichi Nishimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : A Supply Current Test Method for Pin Shorts in PIC ICs, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 116, Sep. 2004.
253.	Tetsuo Akita, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Mitsuo Shimotani : Detection of Open Fault Realized by Transmission Gate with IDDT Disappearance Time Detection Circuit, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 115, Sep. 2004.
254.	Daisuke Ezaki, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Operating Speed of Dynamic CMOS Logic Circuit Driven by Supply Voltage of Rectangle Waveform, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 114, Sep. 2004.
255.	Junji Murakami, Hiroyuki Yotsuyanagi, Masaki Hashizume and Kozo Kinoshita : On Reducing the Length of Scan Trees based on the Structure of Circuit, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 113, Sep. 2004.
256.	Shintaro Nakayashiki, Masahiro Ichimiya, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : IDDQ Test Circuit with a High Speed External Current Sensor, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 112, Sep. 2004.
257.	Tomomi Nishida, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Yukiya Miura : Testability of Supply Current Testing for DA Converters of Resistor String Type, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 111, Sep. 2004.
258.	Masao Takagi, Masaki Hashizume, H. Ishii, Isao Tukimoto, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Pin Open Detection in CMOS TQFP ICs of Low Supply Voltage by Measuring Supply Current under AC Electric Field, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 110, Sep. 2004.
259.	Isao Tsukimoto, Masao Takagi, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Deterministic Test Vector Generation of Supply Current Test for Open Faults Undetected by Functional Tests in TTL ICs, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 109, Sep. 2004.
260.	Makoto Kawajiri, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Spice Model for Deriving Fault Model of Charge Coupled Devices, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 108, Sep. 2004.
261.	Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Constructing Scan Trees based on a Circuit Structure, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 156, Oct. 2003.
262.	Hirokazu Sano, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Test Generation for Sequential Circuits using Structure Based Partitioning, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 155, Oct. 2003.
263.	Daisuke Ezaki, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : A Power Supply Circuit for Dynamic CMOS Logic Circuits, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 139, Oct. 2003.
264.	Kenji Kaishita, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Low Power Dynamic CMOS Logic Circuits, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 138, Oct. 2003.
265.	Tetsuo Akita, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Mitsuo Shimotani : IDDT Test Circuit for Detecting Open Faults in CMOS ICs, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 137, Oct. 2003.
266.	Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Tetsuo Tada, Takeshi Koyama, Yasuhiro Miyagawa, Seiji Tanaka and Toshihiro Kayahara : Fail-safe Analysis for a Breaker Valve Circuit in a Boiler Control Circuit, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 136, Oct. 2003.
267.	Masao Takagi, Isao Tukimoto, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Pin Open Detection for CMOS Logic ICs of TQFP Package by Measuring Supply Current under AC Electric Field, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 134, Oct. 2003.
268.	Daisuke Yoneda, Masaki Hashizume, Tetsuo Tada, Takeshi Koyama, Hiroyuki Yotsuyanagi and Takeomi Tamesada : IDDQ Testing with Wavelet Transformation Technique, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 133, Oct. 2003.
269.	Isao Tsukimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi, Masao Takagi and Takeomi Tamesada : Practical Fault Coverage of Supply Current Tests for TTL ICs, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 132, Oct. 2003.
270.	Makoto Kawajiri, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Testability of Current Tests in an AGC Circuit, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 131, Oct. 2003.
271.	Satoshi Matsuda, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Bridging Faults for Oscillation Frequency to be Estimated for the Fault Detection, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 130, Oct. 2003.
272.	Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Finding Invalid States Using Strongly Unreachable States, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 149, Oct. 2002.
273.	Yoshihide Shoji, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : An Improvement of Generating Test Sequence for Test Time Reduction of Current Testing, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 148, Oct. 2002.
274.	Hirokazu Sano, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Reduction of Test Vectors by Focusing on the Number of Detection of Stuck-at Faults in Combinational Circuits, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 147, Oct. 2002.
275.	Taisuke Iwakiri, Hiroyuki Yotsuyanagi, Masaki Hashizume, Masahiro Ichimiya and Takeomi Tamesada : Test Set Compaction for Supply Current Test of Open Defects in CMOS ICs, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 146, Oct. 2002.
276.	Daisuke Yoneda, Masaki Hashizume, Takeshi Koyama, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Noise Removal for IDDQ Testing by Wavelet Transformation, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 143, Oct. 2002.
277.	Teppei Takeda, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Feasibility of IDDQ Test Time Reduction by Changing Test Input Application Interval, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 142, Oct. 2002.
278.	Takao Minami, Masaki Hashizume, Eiji Tasaka, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada and Toshihiro Kayahara : A Power-off Test Method for IC Pin Opens, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 141, Oct. 2002.
279.	Naoki Maeda, Masahiro Ichimiya, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Feasibility of Pin Open Detection in BGA ICs by Supply Current Test under AC Magnetic Field, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 140, Oct. 2002.
280.	Masao Takagi, Isao Tsukimoto, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Pin Open Detection for CMOS Logic ICs of PLCC Package by Measuring Supply Current under AC Electric Field, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 139, Oct. 2002.
281.	Isao Tsukimoto, Masaki Hashizume, Yukiko Mushiaki, Hiroyuki Yotsuyanagi, Masao Takagi and Takeomi Tamesada : Effectivity of Current Testing for Open Faults Undetected by Functional Testing in TTL Combinational Circuits, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 138, Oct. 2002.
282.	Takahiro Ohnishi, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Logic Simulator for Test Input Sequence Evaluation for IDDQ Testing, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 151, Sep. 2001.
283.	Taisuke Iwakiri, Hiroyuki Yotsuyanagi, Masaki Hashizume, Masahiro Ichimiya and Takeomi Tamesada : Evaluation of Stuck-at Pattern and Random Pattern in Supply Current Test of Open Defects, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 150, Sep. 2001.
284.	Shinsuke Hata, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Sequential Redundancy Removal Based on Multiple Unreachable States, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 145, Sep. 2001.
285.	Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Finding Unreachable States with Reducing Search Space, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 144, Sep. 2001.
286.	Masaki Hashizume, Masashi Sato, Hiroyuki Yotsuyanagi, Masahiro Ichimiya and Takeomi Tamesada : Power Consumption in High Speed ADCL Circuits, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 143, Sep. 2001.
287.	Teppei Takeda, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Yukiya Miura and Kozo Kinoshita : IDDQ Test Time Reduction by High Speed Charge for Load Capacitors of Gates, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 142, Sep. 2001.
288.	Akihiro Tsuji, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Experimental Evaluation of Pin Open Detection Method with Time-variable Magnetic Field, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, 141, Sep. 2001.
289.	Yukiko Mushiaki, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Fault Coverages of Supply Current Testing for Open Faults in TTL Circuits, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, No.10-10, 150, Oct. 2000.
290.	Akihiro Tsuji, Masahiro Ichimiya, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : A Solder Floating Test by Current Testing with AC Electric Field Applied, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, No.10-9, 149, Oct. 2000.
291.	Tomonari Matsuo, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Eiji Tasaka and Toshihiro Kayahara : Functional Fault Simulator for Bridging Faults in Boiler Control Microcomputer, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, No.10-8, 148, Oct. 2000.
292.	Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Synthesis for Testability by Adding State Transitions and Redundancy Removal, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, No.10-7, 147, Oct. 2000.
293.	Takahiro Ohnishi, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : A Test Input Sequence for Test Time Reduction of I_DDQ Testing, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, No.10-6, 146, Oct. 2000.
294.	Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Open Fault Detection Based on Supply Current in CMOS ICs, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, No.10-5, 145, Oct. 2000.
295.	Sou Yamamoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Oscillation Frequency Estimation Method of Feedback Bridging Faults, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, No.9-5, 133, Oct. 2000.
296.	Hiroshi Hoshika, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Improvement of IDDQ Testable Design for Static CMOS PLAs, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, No.9-4, 132, Oct. 2000.
297.	Kouichi Sugimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : High Speed Current Test Circuit for CMOS Logic Circuits, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, No.9-3, 131, Oct. 2000.
298.	Masashi Sato, Masaki Hashizume, Hiroyuki Yotsuyanagi, Masahiro Ichimiya and Takeomi Tamesada : Power Supply Circuit for High Speed ADCL Circuits, Journal of Shikoku-Section Joint Convention of the Institutes of Electrical and Related Engineers, No.9-2, 130, Oct. 2000.

Et cetera, Workshop:

1.	Shunta Hosomi, Hiroyuki Yotsuyanagi and Masaki Hashizume : 電圧 - 遅延セルを用いる積層型イメージセンサの電気的断線検出回路の設計について, 第86回FTC研究会資料, Jan. 2023.
2.	Kohsuke Hara, Hiroyuki Yotsuyanagi and Masaki Hashizume : 電荷注入量に基づく電気検査法におけるスキャン回路を考慮する検査入力制御, 第84回FTC研究会資料, Jan. 2022.
3.	Ryotaroh Nakanishi, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yoshinobu Higami and Hiroshi Takahashi : On evaluation of transition signals on adjacent lines used for discrimination of resistive opens using machine learning-based anomaly detection, 第81回FTC研究会資料, Jul. 2019.
4.	Kohki Taniguchi, Hiroyuki Yotsuyanagi and Masaki Hashizume : Study on the Applicability of ATPG Pattern for DFT Circuit, IEICE Technical Report, Vol.118, No.335, 131-136, Dec. 2018. (Summary) With high integration of IC, small delay faults have occurred as the cause of a circuit failure. As a design-for-testability (DFT) method for delay testing a measurement method for delay fault size using TDC mechanism has been proposed. However, conventional automatic test pattern generator tools (ATPG) do not take account of delay fault size. In this paper, we investigate delay fault size by circuit simulation using given ATPG pattern and evaluate the feasibility of testing multiple paths by the TDC embedded circuit. (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1520009408094422016 (CiNii: 1520009408094422016)
5.	Takuto Nishikawa, Hiroyuki Yotsuyanagi and Masaki Hashizume : Effects of Signal Transition Timing on the Resistive Open Fault Detection by Path Delay Comparison, DAシンポジウム2018, 154-159, Aug. 2018. (Summary) Detecting resistive open faults becomes important due to miniaturization. Crosstalk effect causes an extra delay on signal transition on a defective line with a resistive open fault. For testing small delay faults, a test method for resistive open fault by path delay ranking has been proposed. In the method, a pattern pair of a fixed signal and reverse phase transition signal is applied to adjacent lines for detecting faults. However, the delay size changes depending on timing skew of signal transitions on the defective line and its adjacent line, hence the generated test pattern pair may not detect a fault. In this paper, we design an example circuit with resistive open TEG and investigate the effects of the timing skew of signal transitions on the proposed test method.
6.	Toshiaki Satoh, Hiroyuki Yotsuyanagi and Masaki Hashizume : On the Effectiveness of ATPG Pattern for Testing Multiple Paths using Delay Fault Testable Scan Design, 第79回FTC研究会資料, Jul. 2018.
7.	Tomohiro Katayama, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yoshinobu Higami and Hiroshi Takahashi : Evaluation of the Feasibility of Resistive Open Fault Detection by Difference of Path Delay Ranking Considering Process Variation, 第78回FTC研究会資料, Jan. 2018.
8.	Shunsuke Shibata, Hiroyuki Yotsuyanagi and Masaki Hashizume : A Study on Line Length and Temperature Dependencies on Discrimination of Resistive Opens using Transition on Adjacent Lines, 第78回FTC研究会資料, Jan. 2018.
9.	Soma Shinkai, Hiroyuki Yotsuyanagi and Masaki Hashizume : Delay Detection Evaluation for Delay Element in Scan Design with Embedded TDC, 第78回FTC研究会資料, Jan. 2018.
10.	Kohki Taniguchi, Hiroyuki Yotsuyanagi and Masaki Hashizume : Two-path delay testing by experimental design-for-testability circuit, 第64回機能集積情報システム研究会, Oct. 2017.
11.	Shunsuke Shibata, Hiroyuki Yotsuyanagi and Masaki Hashizume : Delay Analysis of Microbump Defect in 3-D IC, 第64回機能集積情報システム研究会, Oct. 2017.
12.	Soma Shinkai, Hiroyuki Yotsuyanagi and Masaki Hashizume : On Design of Delay Fault Detection Circuit for Design For Testability, 第64回機能集積情報システム研究会, Oct. 2017.
13.	Morito Niseki, Toshinori Hosokawa, Masayoshi Yoshimura, Hiroshi Yamazaki, Masayuki Arai, Hiroyuki Yotsuyanagi and Masaki Hashizume : An Untestable Fault Identification Method for Sequential Circuits Using Unreachable States by Justification of State Cubes, DAシンポジウム2017, 186-191, Sep. 2017.
14.	Shingo Kawatsuka, Hiroyuki Yotsuyanagi and Masaki Hashizume : Evaluation of Small Delay Fault Detection by TDC Embedded in Scan FFs, DAシンポジウム2017, 21-26, Aug. 2017.
15.	Takumi Kawaguchi, Hiroyuki Yotsuyanagi and Masaki Hashizume : Design of a Control Circuit for Testing TSVs Using Boundary Scan Circuit with Embedded TDC, DAシンポジウム2017, 15-20, Aug. 2017.
16.	Satoshi Hirai, Hiroyuki Yotsuyanagi and Masaki Hashizume : On design for reducing delay variation in design-for-testability circuit for delay fault, 2017 Taiwan and Japan Conference on Circuits and Systems, Aug. 2017.
17.	Makoto Nishikiori, Hiroshi Yamazaki, Toshinori Hosokawa, Masayoshi Yoshimura, Masayuki Arai, Hiroyuki Yotsuyanagi and Masaki Hashizume : 抵抗性オープン故障のテスト生成法の評価, 第76回FTC研究会資料, Jan. 2017.
18.	Zheng-Hong Cai, Hiroyuki Yotsuyanagi and Masaki Hashizume : A Modified PRPG for Test Pattern Generation using BAST structure, 2016 Taiwan and Japan Conference on Circuits and Systems, Aug. 2016.
19.	Takumi Kawaguchi, Hiroyuki Yotsuyanagi and Masaki Hashizume : On test signal generation and observation for testing multiple TSVs using Boundary scan circuit with embedded TDC, 第75回FTC研究会資料, Jul. 2016.
20.	Yuuya Ohama, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yoshinobu Higami and Hiroshi Takahashi : On reduction of signal assignments of adjacent lines for resistive open defect detection based on timing information of signal transition, 第75回FTC研究会資料, Jul. 2016.
21.	Kosuke Nanbara, Shoichi Umezu, Hiroyuki Yotsuyanagi, Masaki Hashizume and Shyue-Kung Lu : Threshold Value Estimation Method for Electrical Interconnect Tests of 3D ICs, IEEE CASS Shikoku and Malaysia Chapters Joint Seminar, Oct. 2015.
22.	Kotaro Ise, Jun Yamashita, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yoshinobu Higami and Hiroshi Takahashi : On detectability analysis of delay variation caused by a resistive open using signal transitions on adjacent lines, 第72回FTC研究会資料, Jan. 2015.
23.	Motoki Usui, Hiroyuki Yotsuyanagi and Masaki Hashizume : On BAST Code Generation Method by Controlling Feedback in PRPG, 第72回FTC研究会資料, Jan. 2015.
24.	Hiroki Sakurai, Hiroyuki Yotsuyanagi and Masaki Hashizume : Measured Delay Evaluation by Time-to-Digital Converter Embedded in Boundary-scan, 第70回FTC研究会資料, Jan. 2014.
25.	Akihiro Fujiwara, Hiroyuki Yotsuyanagi and Masaki Hashizume : On ring-oscillator structures for TSV fault detection considering the effect of adjacent TSVs, 第70回FTC研究会資料, Jan. 2014.
26.	Takanobu Nimiya, Hiroyuki Makimoto, Hiroyuki Yotsuyanagi and Masaki Hashizume : Multiple path test for detecting delay faults using boundary scan with time-to-digital converter, 第67回FTC研究会資料, Jul. 2012.
27.	Hiroyuki Makimoto, Hiroyuki Yotsuyanagi and Masaki Hashizume : On the design for testability method for detecting delay faults using delay detection circuit, 第65回FTC研究会資料, Jul. 2011.
28.	Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Hiroyuki Yotsuyanagi, Masaki Hashizume and Yuzo Takamatsu : しきい値関数を利用したファンナウト中のオープン故障の診断法, 第63回FTC研究会資料, Jul. 2010.
29.	Kenji Gouda, Hiroyuki Yotsuyanagi and Masaki Hashizume : On Detectability Evaluation of Via-Open Defects Considering the Defect Location and the Coupling Effects of Adjacent Lines, 第63回FTC研究会資料, Jul. 2010.
30.	Kenji Katou, Hiroyuki Yotsuyanagi and Masaki Hashizume : Supply Current Testing of Interconnects Between ICs, 第62回FTC研究会資料, Jan. 2010.
31.	Yuuya Oyamada, Hiroyuki Yotsuyanagi and Masaki Hashizume : On Estimation of Open Fault Effects Considering the Feedback between Adjacent lines, 第58回FTC研究会資料, Jan. 2008.
32.	Mitsuru Tojo, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Masaki Hashizume : Open Detection in CMOS ISs of 0.35μm Process by Supply Current Testing under AS Electric Field Application, 第57回FTC研究会資料, Jul. 2007.
33.	Masato Nakanishi, Hiroyuki Yotsuyanagi, Masaki Hashizume and Yukiya Miura : IDDQ Test Method with a BIC Sensor Tolerating for Process Variations, 第55回FTC研究会資料, Jul. 2006.
34.	Seiichi Nishimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : At-Speed Current Test Method of Open and Short Defects at Buses in Microcomputers, 第54回FTC研究会資料, Jan. 2006.
35.	Takeshi Iihara, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : On Configuring Scan Trees for Multiple-core Design Based on Circuit Structure, 第54回FTC研究会資料, Jan. 2006.
36.	Tomohiko Nagashima, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : On Test Generation for Sequential Circuits Using Limited Scan Operation Considering Initial States, 第52回FTC研究会資料, Jan. 2005.
37.	Yoshiteru Fujimoto, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Extraction of Fault Candidate Areas with Layout Information, IEICE Technical Report, Vol.104, No.478, 79-84, Dec. 2004. (Summary) In this paper, we present a method for extracting fault candidate areas using layout information obtained by CAD. In highly-integrated circuits, a bridging fault may affect not only between two signal lines, but also among multiple signal lines. In this work, we propose a procesure for extracting fault candidate areas of bridging faults between two lines and bridging faults among three lines. The procedure extracts pairs of signal lines whose distance is within the given distance and identifies them as the fault candidate of a bridging fault, and also extracts groups of three signal lines within the given distance and identifies them as the fault candidate of a multinode bridging fault. The procedure that utilizes a layout information obtained from CAD tools to extract fault candidate areas of bridging faults among two or three lines is shown. The experimental results for benchmark circuits are shown for the comparison between the number of the fault candidate areas obtained by the proposed method and the number of the bridging faults between two lines assumed from gate-level. (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1520009408554202240 (CiNii: 1520009408554202240)
38.	Junji Murakami, Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume and Kozo Kinoshita : Configuration of Scan Trees Based on the Structure of Circuit without Test pattern, 第51回FTC研究会資料, Jul. 2004.
39.	Daisuke Yoneda, Masaki Hashizume, Hiroyuki Yotsuyanagi, Tetsuo Tada, Takeshi Koyama and Takeomi Tamesada : IDDQ Testing Based on Wavelet Transform, 第50回FTC研究会資料, Jan. 2004.
40.	Hirokazu Sano, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Test Generation for Sequential Circuits by Logic Simulation using State Partitioning, IEICE Technical Report, No.DC2003-34, 1-6, Nov. 2003. (Summary) 本論文では,状態集合分割を用いた論理シミュレーションによるテスト生成について述べる.本研究で行うテスト生成では,複数の候補ベクトルを作成し,未到達状態へ遷移可能なベクトルをテストベクトルとして採用する.故障検出に有効な状態遷移を得るために,フリップフロップを複数の集合に分割し,重み付けによる状態変化の優先度の設定を行う.状態集合の分割法として,フリップフロップの論理値の制御容易性に基づく分割法と,未検出故障への影響の大きいフリップフロップを回路構造から求め集合分割を行う手法の2つを用いる.本研究では各未検出故障の励起,伝搬に必要なフリップフロップを考慮した集合分割を用いることで,未検出故障の検出に必要な状態遷移を優先する.提案する集合分割法をテスト生成に適用した結果により,集合分割法の有効性について示す. (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1520009409437334144 (CiNii: 1520009409437334144)
41.	Tetsuo Akita, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Built-in Supply Current Sensor Circuit for Detecting Open Faults in CMOS ICs, 第49回FTC研究会資料, Jul. 2003.
42.	Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : AC Electric Field Application Method in Supply Current Tests for IC Pin Open Detection, 第48回FTC研究会資料, Jan. 2003.
43.	Nobuyuki Inoo, Masaki Hashizume, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Oscillation Frequency Estimation for Detecting Feedback Bridging Faults, 第47回FTC研究会資料, Jul. 2002.
44.	Takahiro Ohnishi, Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : A Test Input Sequence for Test Time Reduction of IDDQ Testing, 第46回FTC研究会資料, Jan. 2002.
45.	Akihiro Tsuji, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Pin Open Detection Method Based on Supply Current in Time-variable Magnetic Field, 第45回FTC研究会資料, Jul. 2001.
46.	Hiroyuki Yotsuyanagi, Masaki Hashizume, Takeomi Tamesada and Masahiro Ichimiya : On Detecting CMOS Open Defect by Applying Electric Field and Generating Its Test Pattern, 第44回FTC研究会資料, Jan. 2001.
47.	Hiroyuki Yotsuyanagi, Masaki Hashizume and Takeomi Tamesada : Adding Transitions of Undefined States to State Transition Tables for Testability Enhancement, Workshop on RTL ATPG & DFT (WRTLT00), Sep. 2000. (Summary) In this paper we propose procedures to enhance testability by adding transitions of undefined states to state transition tables. In these procedures, transitions about undefined states, which are not described in state transition tables but exist in a synthesized gate level circuit, are added to a state transition table. Experimental results for MCNC benchmarks are shown.
48.	Masaki Hashizume, Masashi Sato, Hiroyuki Yotsuyanagi and Takeomi Tamesada : Power Supply Circuit for Adiabatic Dymanic CMOS Circuits, IEICE Technical Report, No.FTS99-6, 1-6, Apr. 1999. (Summary) 本論文では，断熱的ダイナミックCMOS論理回路用の電源回路を提案している．断熱的ダイナミックCMOS回路では従来のCMOS論理回路の場合のような一定電圧でなく, 正弦波や三角波のような時変電圧を発生する電源を必要とする．断熱的ダイナミックCMOS回路の動作速度はその電源波形の周波数で決まることから, 高速に電源電圧を変化させ, かつ寄生容量に蓄積されたエネルギーを急速に回収できる電源が必要である．本論文ではそれが可能な電源回路を提案し, 断熱的ダイナミックCMOSインバータ回路を駆動し, その消費電力を回路シミュレーションにより調査している．その結果は, ADCL回路を本電源回路で駆動することにより, 従来のCMOS回路に比べ大幅な低消費電力化が実現できることを示している． (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1520009410310609536 (CiNii: 1520009410310609536)
49.	Hiroyuki Yotsuyanagi, Masaki Hashizume, Takeomi Tamesada and Kozo Kinoshita : A Method for Removing Sequentially Redundant Lines Simultaneously Based on Unreachable States, IEICE Technical Report, No.FTS98-124, 9-16, Feb. 1999. (Summary) We propose a redundancy removal method based on strongly unreachable states, which are states that have no incoming transition from any state. If a fault affects the output sequence or the state transition only when the circuit starts from strongly unreachable states, then the fault is undetectable. More over, if the unreachable states are also strongly unreachable in the faulty circuit, the line corresponding the fault is redundant. In this paper, we present the theorem that the undetectable faults obtained from a strongly unreachable state remain undetectable for the circuit after removing the redundant lines corresponding to one of the faults. We also consider the condition for removing redundant lines simultaneously. Experimental results for benchmark circuits are shown. (Link to Search Site for Scientific Articles) ● CiNii @ National Institute of Informatics (CRID): 1571698602307652224 (CiNii: 1571698602307652224)

Patent:

1.	矢崎徹, 植松裕, 池田康浩, Masaki Hashizume, Hiroyuki Yotsuyanagi and Yuki Ikiri : 半導体装置，及び半導体集積回路, 2017-107547 (May 2017), 2018-206829 (Dec. 2018), 2017-107547 (Dec. 2018).
2.	Masaki Hashizume, Masahiro Ichimiya and Hiroyuki Yotsuyanagi : 電子回路の断線故障検査法とその検査容易化回路, 2006-309430 (Nov. 2006), 2008-122338 (May 2008), .
3.	口井敏匡 and Hiroyuki Yotsuyanagi : 半導体集積回路，スキャン回路設計方法，テストパターン生成方法，および，スキャンテスト方法, 2004-225962 (Aug. 2004), 2006-047013 (Feb. 2006), .
4.	Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, 茅原敏広 and 田坂英司 : ディジタル電子計算機回路の故障検査方法, 009177 (Jan. 1999), .

Grants-in-Aid for Scientific Research (KAKEN Grants Database @ NII.ac.jp)

Design for Testability for Electrical Tests of Interconnects between Dies after Shipment (Project/Area Number: 23K11039 )
On design-for-testability circuit design of pattern generation and propagation for detecting faults at interconnects in stacked ICs (Project/Area Number: 18K11218 )
Open Defect Detection at Interconnects among IC Chips with Relaxation Oscilators (Project/Area Number: 17H01715 )
Design-for-testability circuit for detecting delay faults at interconnects in 3D stacked ICs (Project/Area Number: 15K00079 )
Timing failure diagnosis using pre-silicon test and post-silicon test (Project/Area Number: 25330063 )
Design and evaluation of design-for-testability circuits for delay faults using built-in time-to-digital converter (Project/Area Number: 24500067 )
Search by Researcher Number (90304550)

Associate Professor : Yotsuyanagi, Hiroyuki

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Grants-in-Aid for Scientific Research (KAKEN Grants Database @ NII.ac.jp)